Patch set updated for coreboot: b640523 iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned

[Sebastian Andrzej Siewior]

Sebastian Andrzej Siewior ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1631

-gerrit

commit b640523330fd7600ec96e81a04e37f338168aff3
Author: Sebastian Andrzej Siewior 
Date:   Fri Oct 26 19:02:44 2012 +0200

iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned

The PCI registers should be accessed aligned and 0x62 is not 32bit
    aligned therefore this patch changes it to a 16bit access.

Change-Id: I00725a4569f471eedb061834f626911b42e734fb
    Signed-off-by: Sebastian Andrzej Siewior 
---
 src/mainboard/iwave/iWRainbowG6/romstage.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c
index 833d930..83ae657 100644
--- a/src/mainboard/iwave/iWRainbowG6/romstage.c
+++ b/src/mainboard/iwave/iWRainbowG6/romstage.c
@@ -321,11 +321,11 @@ static void poulsbo_setup_Stage1Regs(void)

static void poulsbo_setup_Stage2Regs(void)
 {
-	u32 reg32;
+	u16 reg16;

printk(BIOS_DEBUG, "Reserved");
-	reg32 = pci_read_config32(PCI_DEV(0, 0x2, 0), 0x62);
-	pci_write_config32(PCI_DEV(0, 0x2, 0), 0x62, (reg32 | 0x3));
+	reg16 = pci_read_config16(PCI_DEV(0, 0x2, 0), 0x62);
+	pci_write_config16(PCI_DEV(0, 0x2, 0), 0x62, (reg16 | 0x3));
    /* Slot capabilities */
    pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500);
    pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500);