Sebastian Andrzej Siewior (sebastian(a)breakpoint.cc) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1632
-gerrit
commit bab8fab0f11b511a5b4007e6cb0dc689b34e311b
Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
Date: Fri Oct 26 19:03:14 2012 +0200
northbridge/sch: move the \n so it reads a little better
Without this, the output of "Setting up ACPI…" continues right
after the output of stepping.
Change-Id: I2ad7cc3e55884ff509600b01274258b8e8250981
Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
---
src/northbridge/intel/sch/early_init.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/northbridge/intel/sch/early_init.c b/src/northbridge/intel/sch/early_init.c
index b4d8eab..f402ccc 100644
--- a/src/northbridge/intel/sch/early_init.c
+++ b/src/northbridge/intel/sch/early_init.c
@@ -153,7 +153,7 @@ static void sch_detect_chipset(void)
/* Others reserved. */
printk(BIOS_INFO, "Unknown (%02x)", reg16);
}
- printk(BIOS_INFO, " Chipset\n");
+ printk(BIOS_INFO, " Chipset ");
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x8);
switch (reg8) {
@@ -173,6 +173,7 @@ static void sch_detect_chipset(void)
/* Others reserved. */
printk(BIOS_INFO, "Unknown (%02x)", reg8);
}
+ printk(BIOS_INFO, "\n");
}
static void sch_setup_non_standard_bars(void)
Sebastian Andrzej Siewior (sebastian(a)breakpoint.cc) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1631
-gerrit
commit 84f9417cb9512e2bb965726dccafc254d9fee57b
Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
Date: Fri Oct 26 19:02:44 2012 +0200
iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned
The PCI registers should be accessed aligned and 0x62 is not 32bit
aligned therefore this patch changes it to a 16bit access.
Change-Id: I00725a4569f471eedb061834f626911b42e734fb
Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
---
src/mainboard/iwave/iWRainbowG6/romstage.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c
index 833d930..02bd1a5 100644
--- a/src/mainboard/iwave/iWRainbowG6/romstage.c
+++ b/src/mainboard/iwave/iWRainbowG6/romstage.c
@@ -324,8 +324,8 @@ static void poulsbo_setup_Stage2Regs(void)
u32 reg32;
printk(BIOS_DEBUG, "Reserved");
- reg32 = pci_read_config32(PCI_DEV(0, 0x2, 0), 0x62);
- pci_write_config32(PCI_DEV(0, 0x2, 0), 0x62, (reg32 | 0x3));
+ reg32 = pci_read_config16(PCI_DEV(0, 0x2, 0), 0x62);
+ pci_write_config16(PCI_DEV(0, 0x2, 0), 0x62, (reg32 | 0x3));
/* Slot capabilities */
pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500);
pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500);
Sebastian Andrzej Siewior (sebastian(a)breakpoint.cc) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1630
-gerrit
commit b8d9fcb56ded4896110febcdfdea61e46d60926c
Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
Date: Fri Oct 26 19:02:10 2012 +0200
iwave/iWRainbowG6: remove USE_DCACHE_RAM
This is not available as a config option anymore.
Change-Id: Icac173d62928423a08671321ec21d4af82c5cded
Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
---
src/mainboard/iwave/iWRainbowG6/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig
index 6802d5c..d429a32 100644
--- a/src/mainboard/iwave/iWRainbowG6/Kconfig
+++ b/src/mainboard/iwave/iWRainbowG6/Kconfig
@@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select HAVE_SMI_HANDLER
select BOARD_ROMSIZE_KB_1024
- select USE_DCACHE_RAM
select GFXUMA
config MAINBOARD_DIR
Sebastian Andrzej Siewior (sebastian(a)breakpoint.cc) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1629
-gerrit
commit 364609066b3ad1be8c5827405d6d3813c72a65a6
Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
Date: Fri Oct 26 19:01:45 2012 +0200
northbridge/sch: read the size of main memory from the proper register
I don't know if the size main memory supposed to be in PCI(0,0) reg 0x9c
but it is not written there. The size of memory is written in
src/northbridge/intel/sch/raminit.c to SCH port(2, 8, 4) (look for
"Setting up TOM").
Change-Id: Iea04a5185bda56f61d1c382533d5a0dac429ebbd
Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
---
src/northbridge/intel/sch/northbridge.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index 4ca1248..4c41d68 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -111,10 +111,10 @@ static void pci_domain_set_resources(device_t dev)
printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
- tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
- printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud << 24);
+ tolud = sch_port_access_read(2, 8, 4);
+ printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud);
- tomk = tolud << 14;
+ tomk = tolud / 1024;
tomk_stolen = tomk;
/* Note: subtract IGD device and TSEG. */
Sebastian Andrzej Siewior (sebastian(a)breakpoint.cc) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1628
-gerrit
commit 9ca468c393884f342b167d4c2d4028b8d976e60b
Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
Date: Fri Oct 26 19:01:17 2012 +0200
northbridge/sch: Read the GPU memory from the correct PCI device
The GGC register which contains the size of memory that is used for GPU
is in PCI device 2,0 and not 0,0. It is set to to 4MiB in
src/mainboard/iwave/iWRainbowG6/romstage.c.
Change-Id: Ie9f1cc60544ecd9cad770f34c83c33564a6129d4
Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
---
src/northbridge/intel/sch/northbridge.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index fb3bff8..4ca1248 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -144,7 +144,7 @@ static void pci_domain_set_resources(device_t dev)
tseg_memory_size = tseg_size * 1024ULL;
}
- reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(2, 0)), GGC);
if (!(reg16 & 2)) {
int uma_size = 0;
printk(BIOS_DEBUG, "IGD decoded, subtracting ");
Sebastian Andrzej Siewior (sebastian(a)breakpoint.cc) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1627
-gerrit
commit 9e467ca71a7eb2f1d723a7880a6eda635b4bc7eb
Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
Date: Fri Oct 26 19:00:22 2012 +0200
northbridge/sch: don't overwrite hightables with GPU / TSEG memory
Without this, the hightables are placed just before the end of memory.
However we might have the GPU memory located at the exact same spot,
that is in the last 4 MiB. So without this patch, this area won't remain
marked as "CONFIGURATION TABLES" within coreboot's memory table but
becomes "RESERVED" because it is part of the PCI(2,0) device.
Change-Id: Ibd111c167c2f6ac03b0ba68581a74ecbd2c9c160
Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de>
---
src/northbridge/intel/sch/northbridge.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index 16ada2f..fb3bff8 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -188,7 +188,9 @@ static void pci_domain_set_resources(device_t dev)
#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables. */
- high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
+ high_tables_base = tomk * 1024 - HIGH_MEMORY_SIZE;
+ high_tables_base -= uma_memory_size;
+ high_tables_base -= tseg_memory_base;
high_tables_size = HIGH_MEMORY_SIZE;
#endif
}
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1624
-gerrit
commit 91f016fb77ca94e50ecb6723035bf29b1547aaf8
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Mon Sep 24 10:48:43 2012 +0200
Fix reading of number of interrupts for IO-APICs
The number read from the io-apic register represents the index of the
highest interrupt redirection entry, i.e. the number of interrupts
minus one.
Change-Id: I54c992e4ff400de24bb9fef5d82251078f92c588
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
src/arch/x86/lib/ioapic.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c
index 57b99e2..018a42c 100644
--- a/src/arch/x86/lib/ioapic.c
+++ b/src/arch/x86/lib/ioapic.c
@@ -85,8 +85,11 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
/* Read the available number of interrupts. */
ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
- if (!ioapic_interrupts || ioapic_interrupts == 0xff)
- ioapic_interrupts = 24;
+ if (ioapic_interrupts == 0xff)
+ ioapic_interrupts = 23;
+ ioapic_interrupts += 1; /* Bits 23-16 specify the maximum redirection
+ entry, which is the number of interrupts
+ minus 1. */
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
#if CONFIG_IOAPIC_INTERRUPTS_ON_FSB