coreboot February 2017

coreboot@coreboot.org

66 participants
212 discussions

No external PCIe GPU possible/working on Gigabyte g41m-es2l
by i1w5d7gf38keg＠tutanota.com 28 Feb '17

28 Feb '17

Hardware: Gigabyte g41m-es2l, latest coreboot git, latest seabios git, two nvidia gpu cards tested I tried to use some external GPU on a g41m-es2l to get some digial screen output. It does not seem to work. When having build coreboot with native vga-init for the internal intel gpu, i never get a output from the nvidia card. When i connect the analog VGA cable to the internal intel gpu and boot up i can see many nouveau (memory-space?) errors. Both GPUs (nvidia and intel) are then enabled at once. Kernel 4.10 cant boot. I tried removing the native vga-init. The only change is then that the Intel GPU works only when the kernel have load. Nvidia card deliver still same errors. With OEM-bios the intel card gets disabled and a PCIe GPU works fine.

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BUGs: Payload Tint
by i1w5d7gf38keg＠tutanota.com 28 Feb '17

28 Feb '17

Hardware: Gigabyte g41m-es2l. Coreboot git + seabios git + native graphics (FLOSS-only) I am using a PS2 keyboard. There is about 1-2 seconds in between when pressing a button until the brick moves in the direction it should move. In the meantime it is went of course many times downwards. This makes the game unplayable hard. At the end of the game i can see the player statistics and the system is not usable any more. I have to press on/off ATX button. Is that like it should be? I tried pressing ctrl+alt+del but nothing happens. I tried about any button on the keyboard. When i press "q" for quit then there is a "Bye" written on the right side of the screen. The Bye when the game ends is written on the left side of the screen together with the statistics.

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Re: [coreboot] ApolloLake Oxbohill CRB GRUB2 menu on serial Console
by Gailu Singh 28 Feb '17

28 Feb '17

Hi, Tried to change --unit=0 to --unit=2 as the serial port index used in coreboot is 2. Still grub2 menu is not shown on serial console. On Mon, Feb 27, 2017 at 4:34 PM, Gailu Singh <gailu96(a)gmail.com> wrote: > Hi Experts, > > I have built grub2 with coreboot platform support (./configure --with-platform=coreboot) > and managed to load it as elf payload in coreboot. I have added terminal > support in grub configuration coreboot.cfg as follows > > serial --speed=115200 --unit=0 --word=8 --parity=no --stop=1 > terminal_input --append serial terminal_output --append serial > terminal_input --append usb_keyboard #add keyboard support. > > menuentry 'Boot From Hard Disk (Linux)' { insmod (cbfsdisk)/ahci.mod linux > (ahci1,msdos1)/boot/bzImage root=/dev/sda1 resume=/dev/sda5 > console=ttyS0,115200 } > > > While I see coreboot logs on serial console, I do not see grub2 menu on > serial console. I can see grub2 menu on HDMI display though, however my > USB keyboard is not working so not able to control grub either through > display or serial console. > > Any help is appreciated. > > Thanks > >

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USB Support on Apollo Lake
by Gailu Singh 28 Feb '17

28 Feb '17

Hi Experts, Does coreboot support USB port initialization in legacy mode on Apollo Lake as some of the BIOS does so that grub or other payloads can use it as USB2.0? There is no USB2.0 port on this board and Grub2 doesn't support xhci so we seems to be reaching to a dead end. I am trying to see if the dual role USB ports can be initialized in coreboot/fsp so that they can act as USB2.0 for payloads. Thanks

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Any H8SCM owners? (does it work?)
by Taiidan＠gmx.com 28 Feb '17

28 Feb '17

I am making a beginners guide for the wiki, and I would like to include the low cost H8SCM board on it. (widely available used for around $30 vs $220 for a used KCMA-D8) If anyone has this one I have a few questions: Assume a 42xx series Opteron processor is in use. (41xx is crap and 43xx needs microcode for secure operation and IOMMU) * Does it work with a native equivalent or near native featureset? * Does it use the older open source version of AGESA? (I am not so sure how to easily tell them apart as tim pearson said it wasn't audited for binaries) * Does it need any blobs to work? (besides VGA, as nobody will will want to use the terrible onboard chipset as this isn't a server board) * Does IOMMU work?, in platform_cfg.h IOMMU_SUPPORT_DISABLE is there with a "TODO" - but what would it take to enable this? I know that AGESA has stubs for it but other than that I can't find any documentation - I imagine this is all secret squirrel AMD confidential stuff and if it was easy someone would have done it already. * Does the -F version (with the BMC) work identical to the regular version if you remove the BMC ROM? (maybe a security risk due to the direct data link from the BMC to one of the onboard intel nics according to the block diagram) - Thanks!

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Re: [coreboot] How to reduce formal issues with new contributions from corporations?
by Zaolin 28 Feb '17

28 Feb '17

I guess you misunderstood something. The new documentation system consists of the markdown documentation in the source code repository and an automatic generated homepage via static site generator https://gohugo.io/ . The homepage will be updated everyday from the Documentation directory markdown files. It's also possible to use asciidoc or restructured Text for the documentation. Regards Zaolin On 02/28/2017 01:53 AM, Taiidan(a)gmx.com wrote: > On 02/27/2017 04:37 PM, Stefan Reinauer wrote: > >>> Should this documentation be moved to the repository? A lot of the >>> “guideline Wiki pages” are locked anyway. People knowing the Linux >>> kernel, would expect that to also live in the source code repository? >> Yes, I am in favor of moving relevant documentation into the source >> tree, as I believe that we should obsolete the wiki all together. >> >> Stefan > Removing the wiki increases the learning curve for new users and would > make it more difficult to find information at a glance. > > I personally never would have started using coreboot if I had to view > the source tree for documentation, that scares people away and a text > file is not at all equivalent to a nicely formatted wiki page. >

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How to reduce formal issues with new contributions from corporations?
by Paul Menzel 28 Feb '17

28 Feb '17

Dear coreboot folks, It’s great to see, that there a quite a few contributions – even the majority – from people paid to do coreboot work. Especially Intel and Google seem to employ a lot of developers working on coreboot, and a lot of them push patches up for review. That’s great. My impression is though, that a lot of these contributions have formal issues in the beginning. As the coding style and the commit message guide lines are well documented in our Wiki [1][2], and there are even scripts checking commits, the developers starting to work on coreboot just don’t seem to know about this. How can this be improved? Could the companies make sure, that there developers read those, and use the scripts? Should this documentation be moved to the repository? A lot of the “guideline Wiki pages” are locked anyway. People knowing the Linux kernel, would expect that to also live in the source code repository? Thanks, Paul [1] https://www.coreboot.org/Coding_Style [2] https://www.coreboot.org/Git#Commit_messages

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payload coreinfo - no button press works
by i1w5d7gf38keg＠tutanota.com 27 Feb '17

27 Feb '17

Hardware: g41m-es2l, latest coreboot git, latest seabios git, native vga, ps2 keyboard + usb keyboard I liked to try out coreinfo. It show the CPU Information page at start. When i then press any button (f1,f2,a,b,c,d) nothing happens. I also cant reboot by pressing ctrl+alt+del. Have to press the ATX-power-on/off-button. I then shut down and connected a USB-Keyboard. I pressed in Seabios esc (usb keyboard is working) and then inside coreinfo i was again unable to get any functionality by pressing some button.

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Re: [coreboot] [RFC] Always include coreboot banner in console independent of log level
by Paul Menzel 27 Feb '17

27 Feb '17

Dear Martin, dear Julius, Am Freitag, den 24.02.2017, 16:41 -0700 schrieb Martin Roth: > My argument is that if nothing at all is shown, its difficult to know if > that's because nothing needs to be shown, or because the console is busted. That was my original motivation too. The image for QEMU with log level WARNING, didn’t print anything to the console, so I didn’t know if QEMU was called incorrectly, or if there was another problem with the build. > Maybe we break up the banner, and don't print both romstage and > ramstage banners, but just the romstage banner. I'd say that just printing > the coreboot version should be sufficient, especially since the build date > is based on the commit id: > > So at loglevel 0, we get: > coreboot-4.5-1079-g613350897d But can’t the version for romstage and ramstage differ? (Though very unlikely.) > At loglevel 5 (or whatever) we get the additional text: With the current definitions, it should be log level 6 (INFO). 5 (NOTICE) is “Normal but significant conditions.”, while 6 (INFO) is “Informational messages.”. (No idea how “significant” condition is defined.) > coreboot-4.5-1079-g613350897d Fri Feb 24 14:59:42 UTC 2017 romstage > starting... Julius, do you have any measurements, how much time printing 100 characters over the serial console would take? Also, does that really matter for production systems? What log level are they normally shipped with? Thanks, Paul

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Re: [coreboot] Corboot on IPC-FP4-DP G Series
by Marshall Dawson 27 Feb '17

27 Feb '17

> > ...assume 3rdparty/blobs has working ones. > These have been tested on the Gardenia board, but not on the Embedded DB-FP4-LC. I have no reason to believe they should be different. I had originally looked at the Sapphire site for that board model and had the impression the system was more like Bettong -- the OPNs they cite are Family 15h model 60h-6Fh. However, based on your CPU-Z report, your .config looks correct to me WRT the blobs. How can I know if the COM ports are connected to the APU or to the superIO? > Which is the right configuration in the first case and in the second one? > Your .config is set up for an APU UART. Given that these are memory-mapped and have an unusual register mapping, I doubt this is a common configuration for most shipping systems. The SuperIO is more likely. You should be able to find other mainboard examples for how to add a superio to your mainboard/devicetree.cb file. Unfortunately, if it's correct that Sapphire used an F81803, the coreboot tree doesn't contain that yet so you may have an uphill climb trying to add it. Thanks, Marshall On Mon, Feb 27, 2017 at 4:50 AM, Kyösti Mälkki <kyosti.malkki(a)gmail.com> wrote: > > On Fri, Feb 17, 2017 at 12:03 AM, giuseppe.ferrigni--- via coreboot < > coreboot(a)coreboot.org> wrote: > >> Hi, >> >> I'm trying to flash corboot on a IPC-FP4-DP G Series. The system has the >> following components (from CPU-Z software tool): >> >> CPU: AMD GX-224IJ - 00670F00 - Prairie Falcon (Family 15h Model 70h - >> Stoney Ridge) >> MOTHERBOARD: Gardenia CRB >> CHIPSET: AMD K15IMC >> SOUTHBRIDGE: Carrizo FCH >> LPCIO: Fintek F81803 >> >> It seems that the actual coreboot release is compatible with each >> component, so I configured it as in the attached file. >> Obviously, nothing is so simple. After flashing, nothing on video, >> nothing on COM port. >> I have now some simple questions: >> - is my configuration correct? >> - how can I start debugging, since I have no feedback? >> - Can I test the boot process of the rom in some way using qemu? >> - How can I know if the COM ports are connected to the APU or to the >> superIO? Which is the right configuration in the first case and in the >> second one? >> > > I would check twice the PSP firmware files you have embedded in your > image. Unfortunately I cannot give you any SHA sums of correct files to > have, but I would assume 3rdparty/blobs has working ones. > > There is board-status output of a tested configuration for amd/gardenia > here: > > https://www.coreboot.org/Supported_Motherboards#amd.2Fgardenia > > Kyösti > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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coreboot February 2017