coreboot February 2020

coreboot@coreboot.org

40 participants
31 discussions

Open Source Hackathon Mentor Invitation
by Advai Podduturi 18 Feb '20

18 Feb '20

Hello, My name is Advai Podduturi and I’m reaching out on behalf of the HackIllinois Outreach team. HackIllinois is a 36-hour collegiate Open Source hackathon that takes place annually at the University of Illinois Urbana-Champaign. This year, it will be from February 28th - March 1st, 2020. Our mission is to introduce college students to Open Source, while giving back to the community. We strive to create a collaborative environment in which our attendees can learn from and work with developers to make their own contributions. In past years, we’ve had developers from prominent projects such as npm, Rust, and Apache come to mentor students from our pool of 900+ attendees. We’d love it if you could pass along this message to the coreboot community or any individuals you believe would be interested. We will provide meals throughout the event and can reimburse for travel and lodging up to a certain amount depending on where in the US people are coming from. More information on mentorship can be found at hackillinois.org/mentor <http://ec2-52-26-194-35.us-west-2.compute.amazonaws.com/x/d?c=6287904&l=b31…>. You can also visit opensource.hackillinois.org <http://ec2-52-26-194-35.us-west-2.compute.amazonaws.com/x/d?c=6287904&l=360…> to see what kinds of projects were represented at our event last year. Sincerely, Advai Podduturi -- Advai Podduturi HackIllinois 2020 | Outreach Team advai.podduturi(a)hackillinois.org | 630-765-4099

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How to Install Epson Printer on Mac?
by alexathomson03＠gmail.com 18 Feb '20

18 Feb '20

Epson is among one of the best and oldest printer developing organizations. The company has earned fame by providing top-quality printers, which is fairly evident with the Epson's financial statement. Conversely, people are still facing a problem in choosing the right product according to their work. Dial Epson printer toll-free number to contact the experts and get an answer to your queries. These technicians are providing services 24x7; so, you can reach them whenever you encounter any hassle. Visit here to know the steps : <a href="http://quick-customer-support.com/brother-printer/">Brother Printer Support number </a>. https://gooddirectoery.uk.com/epson-printer-support

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Upgrading Packages
by Vikram Chundawat 15 Feb '20

15 Feb '20

Hello, I have upgraded some packages and they seem work fine without any issues. I have upgraded GCC,GDB,Make,GMP to GCC-9.2.0,GDB-9.1,Make-4.3,GMP-6.2.0. Project compiled successfully with errors. I want to submit my modifications for review but the guide at https://review.coreboot.org/Documentation/user-upload.html#_git_push seems a bit confusing. Can anyone help me? Thank you Vikram Singh Chundawat

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Debugging undetected SATA disk?
by Mogens Jensen 13 Feb '20

13 Feb '20

I have installed coreboot on my CompuLab Intense PC (Ivy Bridge). Intel ME blob was extracted from firmware image dump. This ME version (8.1.20.1336) contains multiple security vulnerabilites, so I have downloaded latest firmware update from vendor website extracted the ME (8.1.72.3002) and used that to build coreboot. However, after flashing updated rom, the SATA disk is no longer detected. The coreboot configuration is identical for both roms, only difference is the ME version. The SATA controller is detected in both cases by coreboot and Linux: SATA: Initializing... SATA: Controller in AHCI mode. 00:1f.2 SATA controller: Intel Corporation 7 Series Chipset Family 6-port SATA Controller [AHCI mode] (rev 04) With newer ME, there are no errors, it's just like the SATA disk is not plugged in. I have compared output of cbmem, line by line in cronological order, from system booted by USB disk with working and non working SATA, cut out blocks with differences and marked them with a *. I don't know if this is a good way, please let me know if I should have done otherwise. SATA disk working: ============================= Update PCI-E configuration space: PCI(0, 0, 0)[a0] = 0 PCI(0, 0, 0)[a4] = 2 * PCI(0, 0, 0)[bc] = 82a00000 PCI(0, 0, 0)[a8] = 7b600000 PCI(0, 0, 0)[ac] = 2 * PCI(0, 0, 0)[b8] = 80000000 PCI(0, 0, 0)[b0] = 80a00000 PCI(0, 0, 0)[b4] = 80800000 PCI(0, 0, 0)[7c] = 7f PCI(0, 0, 0)[70] = fe000000 PCI(0, 0, 0)[74] = 1 * PCI(0, 0, 0)[78] = fe000c00 ============================= SATA disk NOT working: ============================= Update PCI-E configuration space: PCI(0, 0, 0)[a0] = 0 PCI(0, 0, 0)[a4] = 4 * PCI(0, 0, 0)[bc] = 82a00000 PCI(0, 0, 0)[a8] = 7b600000 PCI(0, 0, 0)[ac] = 4 * PCI(0, 0, 0)[b8] = 80000000 PCI(0, 0, 0)[b0] = 80a00000 PCI(0, 0, 0)[b4] = 80800000 PCI(0, 0, 0)[7c] = 7f PCI(0, 0, 0)[70] = fe000000 PCI(0, 0, 0)[74] = 3 * PCI(0, 0, 0)[78] = fe000c00 ============================= SATA disk working: ============================= ME: FWS2: 0x161f012a * ME: Bist in progress: 0x0 ME: ICC Status : 0x1 * ME: Invoke MEBx : 0x1 ME: CPU replaced : 0x0 ============================= SATA disk NOT working: ============================= ME: FWS2: 0x161f012e * ME: Bist in progress: 0x0 ME: ICC Status : 0x3 * ME: Invoke MEBx : 0x1 ME: CPU replaced : 0x0 ============================= SATA disk working: ============================= PASSED! Tell ME that DRAM is ready ME: FWS2: 0x1650012e * ME: Bist in progress: 0x0 ME: ICC Status : 0x3 * ME: Invoke MEBx : 0x1 ME: CPU replaced : 0x0 ============================= SATA disk NOT working: ============================= PASSED! Tell ME that DRAM is ready ME: FWS2: 0x1650012a * ME: Bist in progress: 0x0 ME: ICC Status : 0x1 * ME: Invoke MEBx : 0x1 ME: CPU replaced : 0x0 ============================= SATA disk working: ============================= memcfg channel assignment: A: 1, B 0, C 2 * memcfg channel[0] config (00000000): * ECC inactive enhanced interleave mode off * rank interleave off * DIMMA 0 MB width x8 single rank, selected * DIMMB 0 MB width x8 single rank ============================= SATA disk NOT working: ============================= memcfg channel assignment: A: 0, B 1, C 2 * memcfg channel[0] config (00620020): * ECC inactive enhanced interleave mode on * rank interleave on * DIMMA 8192 MB width x8 dual rank, selected * DIMMB 0 MB width x8 single rank ============================= SATA disk working: ============================= PCH: Remap PCIe function 4 to 3 PCI: 00:1c.4 [8086/1e18] enabled PCI: 00:1c.5: Disabling device PCI: 00:1c.6: Disabling device PCI: 00:1c.6 [8086/1e1c] disabled * PCI: 00:1c.7: Disabling device ============================= SATA disk NOT working: ============================= PCH: Remap PCIe function 4 to 3 PCI: 00:1c.4 [8086/1e18] enabled PCI: 00:1c.5: Disabling device PCI: 00:1c.6: Disabling device * PCI: 00:1c.7: Disabling device ============================= SATA disk working: ============================= PCI: Leftover static devices: PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:1c.4 PCI: 00:1c.5 * PCI: 00:1c.7 PCI: Check your devicetree.cb. ============================= SATA disk NOT working: ============================= PCI: Leftover static devices: PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:1c.4 PCI: 00:1c.5 PCI: 00:1c.6 * PCI: 00:1c.7 PCI: Check your devicetree.cb. ============================= SATA disk working: ============================= Available memory below 4GB: 2048M Available memory above 4GB: 6070M * ============================= SATA disk NOT working: ============================= Available memory below 4GB: 2048M Available memory above 4GB: 14262M * ============================= SATA disk working: ============================= CPU physical address size: 36 bits MTRR: default type WB/UC MTRR counts: 4/4. * MTRR: UC selected as default type. * ============================= SATA disk NOT working: ============================= CPU physical address size: 36 bits MTRR: default type WB/UC MTRR counts: 4/5. * MTRR: WB selected as default type. * ============================= SATA disk working: ============================= Create SMBIOS type 17 SMBIOS tables: 682 bytes. * ============================= SATA disk NOT working: ============================= Create SMBIOS type 17 SMBIOS tables: 782 bytes. * ============================= SATA disk working: ============================= Found 1 serial ports Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 * AHCI/0: Set transfer mode to UDMA-6 * Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0 * AHCI/0: registering: "AHCI/0: Samsung SSD 840 PRO Series ATA-9 Hard-Disk (238 GiBytes)" * PS2 keyboard initialized ============================= SATA disk NOT working: ============================= Found 1 serial ports * * * * PS2 keyboard initialized ============================= Vendor firmware has working SATA with same ME, what could change that makes coreboot not detect the SATA disk anymore? The final goal is to disable ME with me_cleaner, but that also breaks SATA as documented here: https://github.com/corna/me_cleaner/issues/119 But I think if we can get coreboot to detect SATA disk with new ME version, it can also be disabled completely. I'm very interested in getting this to work, but I'm not sure where I should start with the debugging. Can anyone point me in the right direction? I would appreciate any ideas!! Thanks in advance. Regards, Mogense Jensen

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Coreboot (T440P) is unable to initialize i7 Crystalwell CPUs
by ad-min＠mailbox.org 13 Feb '20

13 Feb '20

The stock bios runs Crystalwell CPUs just fine. Coreboot recognizes the CPU but is unable to initialize it correctly. Any ideas? I've already added the missing CPU ID in src/cpu/intel/haswell/haswell_init.c as seen here: https://github.com/archfan/coreboot/commit/447933cdbffb2ceef8032c8cd0af0f86… and here https://github.com/archfan/coreboot/commit/69975c04380be99c97d7941b70df9eb2… > CPU id(40661) ucode:0000001b Intel(R) Core(TM) i7-4960HQ CPU @ 2.60GHz Log output: coreboot-5048aad2ef-dirty Mon Feb 10 21:42:53 UTC 2020 bootblock starting (log level: 8)... Timestamp - end of bootblock: 1303483090 FMAP: area COREBOOT found @ a10200 (2031104 bytes) CBFS @ a10200 size 1efe00 CBFS: 'COREBOOT Locator' located CBFS at [a10200:c00000) CBFS: Locating 'fallback/romstage' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 8884 CBFS: Found @ offset 80 size 8884 Timestamp - starting to load romstage: 1322290502 Timestamp - finished loading romstage: 1324580855 coreboot-5048aad2ef-dirty Mon Feb 10 21:42:53 UTC 2020 romstage starting (log level: 8)... Disabling Watchdog reboot... done. SMBus controller enabled. Setting up static northbridge registers... done. Started PEG10 link training. Temporarily hiding PEG10. Started PEG10 link training. Temporarily hiding PEG10. Initializing IGD... Back from haswell_early_initialization() Timestamp - before ram initialization: 1345318221 CPU id(40661) ucode:0000001b Intel(R) Core(TM) i7-4960HQ CPU @ 2.60GHz AES supported, TXT supported, VT supported PCH type: QM87, device id: 8c4f, rev id 5 Starting UEFI PEI System Agent FMAP: area RW_MRC_CACHE found @ a00000 (65536 bytes) prepare_mrc_cache: at ffe00030, size fd4 FMAP: area COREBOOT found @ a10200 (2031104 bytes) CBFS: Locating 'mrc.bin' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 8884 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 8980 CBFS: File @ offset 8980 size 17000 CBFS: Unmatched 'cpu_microcode_blob.bin' at 8980 CBFS: Checking offset 1fa00 CBFS: File @ offset 1fa00 size 1db5d CBFS: Unmatched 'fallback/ramstage' at 1fa00 CBFS: Checking offset 3d5c0 CBFS: File @ offset 3d5c0 size 436 CBFS: Unmatched 'config' at 3d5c0 CBFS: Checking offset 3da40 CBFS: File @ offset 3da40 size 29d CBFS: Unmatched 'revision' at 3da40 CBFS: Checking offset 3dd40 CBFS: File @ offset 3dd40 size 100 CBFS: Unmatched 'cmos.default' at 3dd40 CBFS: Checking offset 3de80 CBFS: File @ offset 3de80 size 5a7 CBFS: Unmatched 'vbt.bin' at 3de80 CBFS: Checking offset 3e480 CBFS: File @ offset 3e480 size 524 CBFS: Unmatched 'cmos_layout.bin' at 3e480 CBFS: Checking offset 3ea00 CBFS: File @ offset 3ea00 size 5a64 CBFS: Unmatched 'fallback/postcar' at 3ea00 CBFS: Checking offset 444c0 CBFS: File @ offset 444c0 size 36b9 CBFS: Unmatched 'fallback/dsdt.aml' at 444c0 CBFS: Checking offset 47c00 CBFS: File @ offset 47c00 size af60f CBFS: Unmatched 'fallback/payload' at 47c00 CBFS: Checking offset f7280 CBFS: File @ offset f7280 size 98b18 CBFS: Unmatched '' at f7280 CBFS: Checking offset 18fdc0 CBFS: File @ offset 18fdc0 size 2e6e4 CBFS: Found @ offset 18fdc0 size 2e6e4 System Agent: Starting up... System Agent: Initializing PCH install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845} install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276} System Agent: Initializing PCH (SMBUS) System Agent: Initializing PCH (USUSB System Agent Version 1.6.1 Build 2 memcfg DDR3 clock 1600 MHz memcfg channel assignment: A: 0, B 1, C 2 memcfg channel[0] config (00600008): ECC inactive enhanced interleave mode on rank interleave on DIMMA 2048 MB width x8 or x32 single rank, selected DIMMB 0 MB width x8 or x32 single rank memcfg channel[1] config (00600000): ECC inactive enhanced interleave mode on rank interleave on DIMMA 0 MB width x8 or x32 single rank, selected DIMMB 0 MB width x8 or x32 single rank Timestamp - after ram initialization: 4551055366 ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Manufacturing Mode : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Initializing ME: Current Operation State : Bring up ME: Current Operation Mode : Normal ME: Error Code : Debug Failure ME: Progress Phase : BUP Phase ME: Power Management Event : Moff->Mx wake after an error ME: Progress Phase State : 0x7b CBMEM: IMD: root @ 7cfff000 254 entries. IMD: root @ 7cffec00 62 entries. External stage cache: IMD: root @ 7d3ff000 254 entries. IMD: root @ 7d3fec00 62 entries. Timestamp - start of bootblock: 337318917 Timestamp - end of bootblock: 1277798392 Timestamp - starting to load romstage: 1296605804 Timestamp - finished loading romstage: 1298896157 Timestamp - start of romstage: 1301475825 Timestamp - before ram initialization: 1319633523 Timestamp - after ram initialization: 4525370668 Unhiding PEG10. SMM Memory Map SMRAM : 0x7d000000 0x800000 Subregion 0: 0x7d000000 0x300000 Subregion 1: 0x7d300000 0x100000 Subregion 2: 0x7d400000 0x400000 MTRR Range: Start=7c800000 End=7d000000 (Size 800000) MTRR Range: Start=7d000000 End=7d800000 (Size 800000) MTRR Range: Start=ff800000 End=0 (Size 800000) FMAP: area COREBOOT found @ a10200 (2031104 bytes) CBFS @ a10200 size 1efe00 CBFS: 'COREBOOT Locator' located CBFS at [a10200:c00000) CBFS: Locating 'fallback/postcar' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 8884 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 8980 CBFS: File @ offset 8980 size 17000 CBFS: Unmatched 'cpu_microcode_blob.bin' at 8980 CBFS: Checking offset 1fa00 CBFS: File @ offset 1fa00 size 1db5d CBFS: Unmatched 'fallback/ramstage' at 1fa00 CBFS: Checking offset 3d5c0 CBFS: File @ offset 3d5c0 size 436 CBFS: Unmatched 'config' at 3d5c0 CBFS: Checking offset 3da40 CBFS: File @ offset 3da40 size 29d CBFS: Unmatched 'revision' at 3da40 CBFS: Checking offset 3dd40 CBFS: File @ offset 3dd40 size 100 CBFS: Unmatched 'cmos.default' at 3dd40 CBFS: Checking offset 3de80 CBFS: File @ offset 3de80 size 5a7 CBFS: Unmatched 'vbt.bin' at 3de80 CBFS: Checking offset 3e480 CBFS: File @ offset 3e480 size 524 CBFS: Unmatched 'cmos_layout.bin' at 3e480 CBFS: Checking offset 3ea00 CBFS: File @ offset 3ea00 size 5a64 CBFS: Found @ offset 3ea00 size 5a64 Decompressing stage fallback/postcar @ 0x7cfd0fc0 (39280 bytes) Loading module at 7cfd1000 with entry 7cfd1000. filesize: 0x55d0 memsize: 0x9930 Processing 270 relocs. Offset value of 0x7afd1000 Timestamp - end of romstage: 4696033836 usbdebug: postcar starting... FMAP: area COREBOOT found @ a10200 (2031104 bytes) CBFS: 'COREBOOT Locator' located CBFS at [a10200:c00000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 1fa00 size 1db5d Decompressing stage fallback/ramstage @ 0x7cf78fc0 (355640 bytes) Loading module at 7cf79000 with entry 7cf79000. filesize: 0x41ed8 memsize: 0x56cf8 Processing 4095 relocs. Offset value of 0x7c179000 usbdebug: ramstage starting... Normal boot. BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0 Enumerating buses... CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0d04] enabled PCI: 00:01.0 subordinate bus PCI Express PCI: 00:01.0 [8086/0d01] enabled PCI: 00:02.0 [8086/0d26] enabled PCI: 00:03.0 [8086/0d0c] enabled PCI: 00:04.0 [8086/0d03] enabled PCI: 00:14.0 [8086/8c31] enabled PCI: 00:16.0 [8086/8c3a] enabled PCI: 00:16.1: Disabling device PCI: 00:16.2: Disabling device PCI: 00:16.3: Disabling device PCI: 00:19.0 [8086/153a] enabled PCI: 00:1a.0 [8086/8c2d] enabled PCI: 00:1b.0 [8086/8c20] enabled PCIe Root Port 1 ASPM is disabled PCI: 00:1c.0 [8086/8c10] enabled PCIe Root Port 2 ASPM is disabled PCI: 00:1c.1 [8086/8c12] enabled PCI: 00:1c.2 [8086/8c14] disabled PCI: 00:1c.3 [8086/8c16] disabled PCI: 00:1c.4 [8086/8c18] disabled PCI: 00:1d.0 [8086/8c26] enabled PCI: 00:1f.0 [8086/8c4f] enabled PCI: 00:1f.2 [8086/8c03] enabled PCI: 00:1f.3 [8086/8c22] enabled PCI: 00:1f.5: Disabling device PCI: 00:1f.6: Disabling device PCI: Leftover static devices: PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:1c.5 PCI: 00:1c.6 PCI: 00:1c.7 PCI: 00:1f.5 PCI: 00:1f.6 PCI: Check your devicetree.cb. PCI: pci_scan_bus for bus 01 scan_bus: scanning of bus PCI: 00:01.0 took 266 usecs PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [10ec/5227] enabled Enabling Common Clock Configuration ASPM: Enabled L0s and L1 scan_bus: scanning of bus PCI: 00:1c.0 took 1246 usecs PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [8086/08b2] enabled Enabling Common Clock Configuration ASPM: Enabled L1 scan_bus: scanning of bus PCI: 00:1c.1 took 1190 usecs No CMOS option 'touchpad'. PMH7: ID 05 Revision 12 PNP: 00ff.1 enabled EC Firmware ID GLHT30WW-3.23, Version 3.01B No CMOS option 'bluetooth'. H8: WWAN detection not implemented. Assuming WWAN installed No CMOS option 'wwan'. PNP: 00ff.2 enabled PNP: 0c31.0 enabled scan_bus: scanning of bus PCI: 00:1f.0 took 6226 usecs scan_bus: scanning of bus PCI: 00:1f.3 took 1 usecs scan_bus: scanning of bus DOMAIN: 0000 took 21461 usecs scan_bus: scanning of bus Root Device took 22353 usecs done FMAP: area RW_MRC_CACHE found @ a00000 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. flash size 0x2800000 bytes SF: Detected Opaque HW-sequencing with sector size 0x1000, total 0x2800000 SF size 0x2800000 does not correspond to CONFIG_ROM_SIZE 0xc00000!! BS: BS_DEV_ENUMERATE times (ms): entry 0 run 23 exit 3 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... PCI: 00:1a.0 EHCI BAR hook registered More than one caller of pci_ehci_read_resources from PCI: 00:1d.0 PNP: 00ff.1 missing read_resources PNP: 00ff.2 missing read_resources Done reading resources. skipping PNP: 00ff.2@60 fixed resource, size=0! skipping PNP: 00ff.2@62 fixed resource, size=0! skipping PNP: 00ff.2@64 fixed resource, size=0! skipping PNP: 00ff.2@66 fixed resource, size=0! Setting resources... PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:02.0 10 <- [0x00f0000000 - 0x00f03fffff] size 0x00400000 gran 0x16 mem64 PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io PCI: 00:03.0 10 <- [0x00f0638000 - 0x00f063bfff] size 0x00004000 gran 0x0e mem64 PCI: 00:04.0 10 <- [0x00f0630000 - 0x00f0637fff] size 0x00008000 gran 0x0f mem64 PCI: 00:14.0 10 <- [0x00f0620000 - 0x00f062ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:16.0 10 <- [0x00f0645000 - 0x00f064500f] size 0x00000010 gran 0x04 mem64 PCI: 00:19.0 10 <- [0x00f0600000 - 0x00f061ffff] size 0x00020000 gran 0x11 mem PCI: 00:19.0 14 <- [0x00f0640000 - 0x00f0640fff] size 0x00001000 gran 0x0c mem PCI: 00:19.0 18 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io PCI: 00:1a.0 EHCI Debug Port hook triggered

3 2

X220 and coreboot?
by Eero Volotinen 12 Feb '20

12 Feb '20

Hi List, Does anyone have dump of this bios as I don't have spi programmer? :( Eero

4 4

Asrock e350m1: sata disks not recognized
by Valentin 12 Feb '20

12 Feb '20

Hello, I've built coreboot for a asrock e350m1 mainboard before the weekend and with the current version SATA disks were not detected. Neither by SeaBIOS nor in a current Linux system booted from USB. As previos versions worked just fine i narrowed it down to the commit 94c47c0 [https://review.coreboot.org/c/coreboot/+/37703], it's the first commit that shows this problem. It seems to me that the rrot cause is that since this commit sb_Poweron_Init() for the sb800 isn't called anywhere, but I'm not sure about the right way to include it. Could anyone help with that? Thanks, Valentin

3 3

thinkpad x250 support
by Eero Volotinen 11 Feb '20

11 Feb '20

Hi, is the thinkpad x250 .. x260 supported in coreboot?

2 1

Intel processors supported
by R Dalton 08 Feb '20

08 Feb '20

We're developing a security focused computer product and hoping to use coreboot. Is it possible to use with modern Intel laptop processors and if so which families or platforms? thanks R Dalton

2 1

Gerrit etiquette
by dhendrix＠coreboot.org 02 Feb '20

02 Feb '20

Dear coreboot community members, Recently there was some unpleasant activity on Gerrit which violated the guidelines [1] regarding respectful conduct. Unfortunately this has directly caused a valued member of the community to withdraw from maintainership and has damaged relations with others as well. After discussion and deliberation, the coreboot leadership has decided to revoke +2/-2 privileges for the provocateur and have asked him to fork the project to continue his work elsewhere, at least for the time being. This decision might be reconsidered at a later date if this person shows respectful behavior when working with community members in the future. This is not the first time such situations have occurred and similar actions taken. It’s never an easy decision to make, however it is necessary to maintain a healthy and productive community. Even when only two people are directly involved in a conflict there are often others who are impacted. The cost of alienating developers and damage to the project is too high to tolerate any individual’s bad behavior. We generally trust that developers acting in good faith and in a respectful manner can resolve conflicts on their own. However, we will continue to develop guidelines to help move things along when disagreements inevitably occur. In any case, it is always required that we treat others in a professional manner and communicate with respect, regardless of who is right or wrong on any issue. [1] https://doc.coreboot.org/getting_started/gerrit_guidelines.html (https://doc.coreboot.org/getting_started/gerrit_guidelines.html)

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coreboot February 2020