coreboot January 2019

coreboot@coreboot.org

39 participants
31 discussions

How do I install a patch for the w520 to use Displayport/VGA output?
by surfbro＠tuta.io 17 Jan '19

17 Jan '19

I've installed Coreboot to a number of my Thinkpad machines, but I have no experience installing patches post installation. I'm trying to get the Displayport/VGA output to function on my now corebooted w520. https://www.coreboot.org/Board:lenovo/w520#VGA_.2F_DisplayPort_output <https://www.coreboot.org/Board:lenovo/w520#VGA_.2F_DisplayPort_output> The official coreboot guide says there's a patch to install to get these to work. Is it possible to put it in layman's terms so that I can get these working, I really really want to use my projector, so this would be so much help! I installed coreboot on my w520 myself so if it's similar to that process I believe I can get it done. Thanks Coreboot team.

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Google Summer of Code 2019
by Patrick Georgi 17 Jan '19

17 Jan '19

Dear coreboot community, I'm preparing the application to have coreboot participate in this year's Google Summer of Code. There are two things we should think about until early February for this: 1. We'll need some project proposals, for which I started https://review.coreboot.org/c/coreboot/+/30972 2. I need to specify the number of mentors we expect to have at hands. This needn't be a guaranteed commitment, but a rough idea would be good. As a mentor-candidate, if we make it into GSoC, we'd try to match you to a student with a project matching your interest and knowledge. You'd discuss their plan, follow up at least weekly on their progress and support them in their process to join and grow in the community. The time frame would be early May to early September: https://developers.google.com/open-source/gsoc/timeline. So if you're interested in growing our community, please speak up :-) Thanks, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

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Manual microcode update for G505s still needed? e.a.
by Anac 16 Jan '19

16 Jan '19

Dear all, Now with Coreboot version 4.9, is it still recommended to manually update AMD microcodes for Lenovo G505s as described here? Or is Coreboot 4.9 up-to-date for using a G505s as a Qubes station? http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#AMD_microcode_upda… How do you handle the AMD GPU AtomBIOS blobs? https://github.com/g505s-opensource-researcher/g505s-atombios#corebootrom-o… may be very clear to experts, but I don't get it. It reads "use one of these commands:" 1) Adding VGABIOS to coreboot.rom 2) Removing VGABIOS from coreboot.rom 3) Printing coreboot.rom memory map Which one should I use? Probably No.1. But there are 2 files for my G505S with discrete HD-8570M (pci1002,990b.rom and pci1002,6663.rom). Which one should I add? Both, separated by space? Then the command would look like that? ./util/cbfstool/cbfstool ~/coreboot.rom add -f ~/pci1002,990b.rom pci1002,6663.rom -n pci****,****.rom -t optionrom That looks odd. Doesn't it? What about TPM? Qubes recommends TPM in their system requirements since it is required for 'Anti Evil Maid'. But Coreboot configuration (make nconfig) does not allow to activate TPM. Am I doing something wrong or is TPM just really not an option? Best regards and thank you! Anac

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To modify MCTRL.SPDDIS of Intel Denvertion in coreboot
by Hilbert Tu(杜睿哲_Pegatron) 15 Jan '19

15 Jan '19

Hi, Is there anyone can tell me how to change MCTRL.SPDDIS in Coreboot? The Intel Denverton blocks write permission to address A0~AE due to security concern of DIMM SPD, but this also restricts the write access to generic EEPROM access in our platform. So I need to modify the SPDDIS bit to bypass the protection. But I don’t know how to do that in Coreboot. Please help and thanks in advance. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

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Coreboot build process with gcc 8.1
by Salvatore Bellizzi 11 Jan '19

11 Jan '19

Hi, I have a question reguarding the build process. Since crossgcc has been updated and gcc is now at version 8.1 I always encounter an error when building coreboot: coreboot/src/console/vtxprintf.c:102: undefined reference to '__udivmoddi4' Since coreboot uses crossgcc and its own libgcc libraries, I figured that the __udivmoddi4 function has not yet been implemented. Anyway I have incurred in this failure several times and even with the latest 4.9 release. Shouldn't I be able to build at least this latest release using unmodified crossgcc or am I missing something else? thanks, salvatore

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Depreciating FSP1.1 on soc/intel/quark along with util/checklist
by Arthur Heymans 09 Jan '19

09 Jan '19

Dear community soc/intel/quark Has 2 FSP versions hooked up, both FSP1.1 and FSP2.0. Maintaining the code for both versions does increase the developers load. So my question is can we remove the older FSP1.1 implementation? Is someone using this board in a setup that cannot be obtained with FSP2.0? There is only one board that has both FSP versions hooked up which can be selected in menuconfig, so we wouldn't be dropping a board. FSP1.1 on the Intel Galileo (only board using soc/intel/quark) is also the only board that uses util/checklist. This utility allows to check if certain linker symbols are found. Supposedly it allows board porters to gradually work towards with a checklist of things to do while in reality its just an extra burden to maintain a list of symbols. So can we remove util/checklist? [1] does that. Kind regards Arthur Heymans [1] https://review.coreboot.org/c/coreboot/+/30691

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Re: [coreboot] AMD IMC open source firmware replacement
by Rudolf Marek 07 Jan '19

07 Jan '19

Dne 30.5.2018 v 16:06 Mike Banon napsal(a): > Hi Rudolf, > > Regarding this part: > " To check if IMC is active check if PCI 0:14.3 0x40 bit7 set. " > what command do I need to use to check this? Try: sudo setpci -s 14.3 40.b Despite command name, it will print the value. Thanks Rudolf

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Please help me adapt coreboot to HiFive-Unleashed
by 王翔 07 Jan '19

07 Jan '19

I tried to adapt coreboot to HiFive-Unleashed and boot bbl with coreboot and run linux. My changes are as follows: https://github.com/hardenedlinux/coreboot-HiFiveUnleashed/tree/HiFive-Unlea… My code can run bbl, but it doesn't respond when bbl exits m-mode and enters linux. I use freedom-u-sdk to compile bbl. In order not to conflict with the coreboot memory address, execute the following command. riscv64-elf-objcopy --change-addresses 0x200000 work/riscv-pk/bbl ../coreboot/payload.elf I don't know what I missed, what should I do, I hope to get your help. ------------------ 王翔安全研究员广州市腾御安信息科技有限公司广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 04 Jan '19

04 Jan '19

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1398603: (CONSTANT_EXPRESSION_RESULT) /src/soc/mediatek/mt8183/dramc_pi_basic_api.c: 124 in transfer_pll_to_spm_control() /src/soc/mediatek/mt8183/dramc_pi_basic_api.c: 125 in transfer_pll_to_spm_control() ________________________________________________________________________________________________________ *** CID 1398603: (CONSTANT_EXPRESSION_RESULT) /src/soc/mediatek/mt8183/dramc_pi_basic_api.c: 124 in transfer_pll_to_spm_control() 118 clrsetbits_le32(&mtk_spm->poweron_config_set, 119 (0xffff << 16) | (0x1 << 0), 120 (0xb16 << 16) | (0x1 << 0)); 121 122 /* Set SPM pinmux */ 123 clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); >>> CID 1398603: (CONSTANT_EXPRESSION_RESULT) >>> "((uint32_t)read32(&mtk_spm->dramc_dpy_clk_sw_con_sel) & 4294967295U /* ~((uint32_t)0) */) | 0xffffffffU" is always 0xffffffff regardless of the values of its operands. This occurs as an argument to a function call. 124 setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); 125 setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); 126 127 setbits_le32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12)); 128 setbits_le32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0); 129 /src/soc/mediatek/mt8183/dramc_pi_basic_api.c: 125 in transfer_pll_to_spm_control() 119 (0xffff << 16) | (0x1 << 0), 120 (0xb16 << 16) | (0x1 << 0)); 121 122 /* Set SPM pinmux */ 123 clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); 124 setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); >>> CID 1398603: (CONSTANT_EXPRESSION_RESULT) >>> "((uint32_t)read32(&mtk_spm->dramc_dpy_clk_sw_con_sel2) & 4294967295U /* ~((uint32_t)0) */) | 0xffffffffU" is always 0xffffffff regardless of the values of its operands. This occurs as an argument to a function call. 125 setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); 126 127 setbits_le32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12)); 128 setbits_le32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0); 129 130 shu_lev = (shu_lev == 1) ? 2 : 1; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Please suggest a AM3/AM3+ motherboard which is supported by Coreboot when32GB of RAM installed
by info＠aulix.com 03 Jan '19

03 Jan '19

Hello, I have found that following boards are indicated as supported: Version:1.0 StartHTML:0000000105 EndHTML:0000025498 StartFragment:0000020391 EndFragment:0000025458 ASUS M4A785-M WIP... AMD Fam10h AMD RS780/SB700 ITE™ IT8712F AMD Athlon™ 64 / FX / X2 Socket AM3/AM2(+) DIP8 SPI Y Y — ASUS M4A785T-M OK... AMD Fam10h AMD RS780/SB700 ITE™ IT8712F AMD Athlon™ 64 / FX / X2 Socket AM3 DIP8 SPI Y Y — ASUS M4A78-EM OK... AMD Fam10h AMD RS780/SB700 ITE™ IT8712F AMD Athlon™ 64 / FX / X2 Socket AM3/AM2(+) DIP8 SPI Y Y — ASUS M5A88-V OK... AMD Fam10h AMD 880G/850 ITE™ IT8721F AMD Athlon™Phenom™Sempron™ 64 / FX / X2 Socket AM3/AM3+ DIP8 SPI Y Y — GIGABYTE GA-MA785GMT-UD2H OK... AMD Fam10h AMD 785G / SB710 ITE IT8718F AMD Phenom™ II / Athlon™ II Socket AM3 ? ? ? ? — GIGABYTE GA-MA78GM-US2H OK AMD Fam10h AMD 780G / SB700 ITE IT8718F AMD Phenom™ / Athlon™ / Sempron™ Socket AM2+ ? ? ? ? — And actually most of them missing any info on the status page and somewhere is info like: The boards works only with less than 4GB of RAM, if installed more then it does not boot Linux. You can see that some AMD 16GB boards support 32GB two with 4x8GB modules: https://www.overclockers.com/forums/showthread.php/698565-Can-i-use-8GB-DDR… http://www.tomshardware.com/answers/id-1714859/asus-m5a88-evo-ram.html But these are 32GBs with their original BIOSes. What about 16GB or 32GB with a Coreboot flashed on these boards? Did anyone tested and used such config with 16GB or 32GB DDR3 RAM? Kind Regards, Alex

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coreboot January 2019