Dear coreboot community,
I'm preparing the application to have coreboot participate in this
year's Google Summer of Code.
There are two things we should think about until early February for this:
1. We'll need some project proposals, for which I started
2. I need to specify the number of mentors we expect to have at hands.
This needn't be a guaranteed commitment, but a rough idea would be
As a mentor-candidate, if we make it into GSoC, we'd try to match you
to a student with a project matching your interest and knowledge.
You'd discuss their plan, follow up at least weekly on their progress
and support them in their process to join and grow in the community.
The time frame would be early May to early September:
So if you're interested in growing our community, please speak up :-)
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
Geschäftsführer: Paul Manicle, Halimah DeLaine Prado
Now with Coreboot version 4.9, is it still recommended to manually
update AMD microcodes for Lenovo G505s as described here? Or is Coreboot
4.9 up-to-date for using a G505s as a Qubes station?
How do you handle the AMD GPU AtomBIOS blobs?
may be very clear to experts, but I don't get it. It reads "use one of
1) Adding VGABIOS to coreboot.rom
2) Removing VGABIOS from coreboot.rom
3) Printing coreboot.rom memory map
Which one should I use? Probably No.1. But there are 2 files for my
G505S with discrete HD-8570M (pci1002,990b.rom and pci1002,6663.rom).
Which one should I add? Both, separated by space? Then the command would
look like that?
./util/cbfstool/cbfstool ~/coreboot.rom add -f ~/pci1002,990b.rom
pci1002,6663.rom -n pci****,****.rom -t optionrom
That looks odd. Doesn't it?
What about TPM? Qubes recommends TPM in their system requirements since
it is required for 'Anti Evil Maid'. But Coreboot configuration (make
nconfig) does not allow to activate TPM. Am I doing something wrong or
is TPM just really not an option?
Best regards and thank you!
Is there anyone can tell me how to change MCTRL.SPDDIS in Coreboot?
The Intel Denverton blocks write permission to address A0~AE due to security concern of DIMM SPD, but this also restricts the write access to generic EEPROM access in our platform. So I need to modify the SPDDIS bit to bypass the protection. But I don’t know how to do that in Coreboot. Please help and thanks in advance.
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I have a question reguarding the build process.
Since crossgcc has been updated and gcc is now at version 8.1 I always
encounter an error when building coreboot:
coreboot/src/console/vtxprintf.c:102: undefined reference to
Since coreboot uses crossgcc and its own libgcc libraries, I figured
that the __udivmoddi4 function has not yet been implemented.
Anyway I have incurred in this failure several times and even with the
latest 4.9 release. Shouldn't I be able to build at least this latest
release using unmodified crossgcc or am I missing something else?
soc/intel/quark Has 2 FSP versions hooked up, both FSP1.1 and FSP2.0.
Maintaining the code for both versions does increase the developers
So my question is can we remove the older FSP1.1 implementation?
Is someone using this board in a setup that cannot be obtained with
There is only one board that has both FSP versions hooked up which can
be selected in menuconfig, so we wouldn't be dropping a board.
FSP1.1 on the Intel Galileo (only board using soc/intel/quark) is also
the only board that uses util/checklist. This utility allows to check
if certain linker symbols are found. Supposedly it allows board porters
to gradually work towards with a checklist of things to do while
in reality its just an extra burden to maintain a list of symbols.
So can we remove util/checklist?  does that.
Dne 30.5.2018 v 16:06 Mike Banon napsal(a):
> Hi Rudolf,
> Regarding this part:
> " To check if IMC is active check if PCI 0:14.3 0x40 bit7 set. "
> what command do I need to use to check this?
sudo setpci -s 14.3 40.b
Despite command name, it will print the value.
I tried to adapt coreboot to HiFive-Unleashed and boot bbl with coreboot and run linux.
My changes are as follows:
My code can run bbl, but it doesn't respond when bbl exits m-mode and enters linux.
I use freedom-u-sdk to compile bbl. In order not to conflict with the coreboot memory address, execute the following command.
riscv64-elf-objcopy --change-addresses 0x200000 work/riscv-pk/bbl ../coreboot/payload.elf
I don't know what I missed, what should I do, I hope to get your help.
I have found that following boards are indicated as supported:
Version:1.0 StartHTML:0000000105 EndHTML:0000025498 StartFragment:0000020391 EndFragment:0000025458
ASUS M4A785-M WIP... AMD Fam10h AMD RS780/SB700 ITE™ IT8712F AMD Athlon™ 64 / FX / X2 Socket AM3/AM2(+) DIP8 SPI Y Y —
ASUS M4A785T-M OK... AMD Fam10h AMD RS780/SB700 ITE™ IT8712F AMD Athlon™ 64 / FX / X2 Socket AM3 DIP8 SPI Y Y —
ASUS M4A78-EM OK... AMD Fam10h AMD RS780/SB700 ITE™ IT8712F AMD Athlon™ 64 / FX / X2 Socket AM3/AM2(+) DIP8 SPI Y Y —
ASUS M5A88-V OK... AMD Fam10h AMD 880G/850 ITE™ IT8721F AMD Athlon™Phenom™Sempron™ 64 / FX / X2 Socket AM3/AM3+ DIP8 SPI Y Y —
GIGABYTE GA-MA785GMT-UD2H OK... AMD Fam10h AMD 785G / SB710 ITE IT8718F AMD Phenom™ II / Athlon™ II Socket AM3 ? ? ? ? —
GIGABYTE GA-MA78GM-US2H OK AMD Fam10h AMD 780G / SB700 ITE IT8718F AMD Phenom™ / Athlon™ / Sempron™ Socket AM2+ ? ? ? ? —
And actually most of them missing any info on the status page and somewhere is info like:
The boards works only with less than 4GB of RAM, if installed more then it does not boot Linux.
You can see that some AMD 16GB boards support 32GB two with 4x8GB modules:
But these are 32GBs with their original BIOSes.
What about 16GB or 32GB with a Coreboot flashed on these boards?
Did anyone tested and used such config with 16GB or 32GB DDR3 RAM?
Video Mode in Coreboot
coreboot video frame buffer information
GOP UEFI driver (Tiano payload) is expected to report 4 modes
GOP should report MaxMode 4 *0:
1600x900 BGRReserved Pixels 1600 1:
640x480 BGRReserved Pixels 640 2:
800x600 BGRReserved Pixels 800 3:
1024x768 BGRReserved Pixels 1024
In BayTrail Platform i only see 1 single mode which is 400 * 300
what changes are expected from GOP/VBIOS to set one of the 4 graphics mode