set PcdSmbusSpdWriteDisable to disable?
On Mon, Jan 14, 2019 at 8:28 PM Hilbert Tu(杜睿哲_Pegatron) <
Is there anyone can tell me how to change MCTRL.SPDDIS in Coreboot?
The Intel Denverton blocks write permission to address A0~AE due to
security concern of DIMM SPD, but this also restricts the write access to
generic EEPROM access in our platform. So I need to modify the SPDDIS bit
to bypass the protection. But I don’t know how to do that in Coreboot.
Please help and thanks in advance.
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