coreboot January 2013

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Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco
by ron minnich 02 Jan '13

02 Jan '13

On Mon, Dec 31, 2012 at 11:23 AM, David Hubbard <david.c.hubbard+coreboot(a)gmail.com> wrote: > Andrew has good points. Technically there's nothing about Secure Boot that > can be proven to exclude alternative OS's such as Linux. While that is technically true, I am starting to see reports of systems that, at the very least, are making it hard to boot anything but Windows. Also. Microsoft has exercised its power to limit the types of binaries that will be signed, e.g. anything built with GPL V3 will not be signed. Now, while they may have valid reasons, this does demonstrate the extent of Microsoft's power over platforms with Secure Boot. I find it worrisome. Given what a mess the vendors have made of $PIR/_MP/ACPI over the years, I don't see the UEFI Secure Boot situation being much better. So, get ready for desktops/laptops that "should" boot non-Windows OSes, but don't. Garret's blog is well worth reading on this whole issue. ron

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Patch set updated for coreboot: 5b294a4 enable early serial console on exynos5250
by David Hendricks 31 Dec '12

31 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2085 -gerrit commit 5b294a4267eeb2fe9a45520ce2cad574511e4591 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 31 17:55:29 2012 -0800 enable early serial console on exynos5250 Change-Id: Ib16308c72b86860e80caec96202c42991a7b1d1a Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index 4a09ca3..abfc049 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -5,6 +5,7 @@ config CPU_SAMSUNG_EXYNOS config CPU_SAMSUNG_EXYNOS5 depends on ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS + select EARLY_SERIAL_CONSOLE bool default n

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Patch set updated for coreboot: 8362128 cleanup some exynos5250 uart code
by David Hendricks 31 Dec '12

31 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2084 -gerrit commit 836212854884b85115df1eb8b69ac62656720a81 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 31 17:56:22 2012 -0800 cleanup some exynos5250 uart code This just cleans out some unused headers and tidies up the early serial code. TODO: Clean-up or replace FDT code, make "base_port" easier to configure. Change-Id: Ie77ee6d4935346e0053c09252055662f1a45d5f5 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/uart.c | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 3d43976..9f4f7f3 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -21,14 +21,8 @@ * */ -//#include <common.h> -//#include <linux/compiler.h> #include <uart.h> #include <arch/io.h> -//#include <asm/arch-exynos/spl.h> -//#include <asm/global_data.h> -//#include <fdtdec.h> -//#include <serial.h> #include <console/console.h> /* for __console definition */ @@ -180,8 +174,6 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -/* FIXME: ordering of arguments for coreboot v. u-boot for tx_byte */ -//static void exynos5_tx_byte(const char c, const int dev_index) static void exynos5_uart_tx_byte(unsigned char data) { // struct s5p_uart *const uart = s5p_get_base_uart(dev_index); @@ -198,14 +190,6 @@ static void exynos5_uart_tx_byte(unsigned char data) #ifndef __PRE_RAM__ static const struct console_driver exynos5_uart_console __console = { -//static const struct console_driver exynos5_uart_console __console = { -#if 0 - void (*init)(void); - void (*tx_byte)(unsigned char byte); - void (*tx_flush)(void); - unsigned char (*rx_byte)(void); - int (*tst_byte)(void); -#endif .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, // .tx_flush = exynos5_uart_tx_flush, @@ -213,11 +197,6 @@ static const struct console_driver exynos5_uart_console __console = { // .tst_byte = exynos5_uart_tst_byte, }; #else -/* for romstage_console... */ -//void (*uart_init)(void) = exynos5_init_dev; -//unsigned char (*uart_rx_byte)(unsigned base_port) = exynos5_uart_rx_byte; -//void (*uart_tx_byte)(unsigned base_port, unsigned char data) = exynos5_uart_tx_byte; -/* FIXME: trivial wrappers */ void uart_init() { exynos5_init_dev();

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Patch set updated for coreboot: 50d7ef8 make early serial console support more generic
by David Hendricks 31 Dec '12

31 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2086 -gerrit commit 50d7ef8df779e9a4cd41d11bcc772518615918a9 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 31 17:28:43 2012 -0800 make early serial console support more generic This patch makes pre-RAM serial init more generic, particularly for platforms which do not necessarily need cache-as-RAM in order to use the serial console and do not have a standard 8250 serial port. This adds a Kconfig variable to set romstage-* for very early serial console init. The current method assumes that cache-as-RAM should enable this, so to maintain compatibility selecting CACHE_AS_RAM will also select EARLY_SERIAL_CONSOLE. Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/console/Kconfig | 7 +++++++ src/console/Makefile.inc | 2 +- src/console/console.c | 4 +++- src/cpu/Kconfig | 1 + src/include/uart.h | 4 ---- 5 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 117fdb8..a726c1f 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -5,6 +5,13 @@ config SERIAL_CONSOLE help Send coreboot debug output to a serial port +config EARLY_SERIAL_CONSOLE + bool + select SERIAL_CONSOLE + default n + help + Use serial console during early boot stages (e.g. cache-as-RAM) + config CONSOLE_SERIAL8250 bool "Serial port console output (I/O mapped, 8250-compatible)" depends on SERIAL_CONSOLE diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index a712486..3c4777f 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -10,7 +10,7 @@ smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-y += vtxprintf.c -romstage-$(CONFIG_CACHE_AS_RAM) += console.c +romstage-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c romstage-y += post.c romstage-y += die.c diff --git a/src/console/console.c b/src/console/console.c index d5f25a5..e92dbf6 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -99,13 +99,15 @@ int console_tst_byte(void) #else // __PRE_RAM__ ^^^ NOT defined vvv defined +#include <uart.h> + void console_init(void) { #if CONFIG_USBDEBUG enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_SERIAL_CONSOLE && !CONFIG_CONSOLE_SERIAL8250MEM uart_init(); #endif #if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 383ba79..ddc46cf 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,6 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool + select EARLY_SERIAL_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/include/uart.h b/src/include/uart.h index 931d6dc..ea371c4 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -15,10 +15,6 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * FIXME(dhendrix): This file contains generic prototypes for UART functions. - * The existing headers are too specific to the 8250, so we need a better - * abstraction for use with non-8250 UARTs. */ #ifndef UART_H

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New patch to review for coreboot: 1aa888f make early serial console support more generic
by David Hendricks 31 Dec '12

31 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2086 -gerrit commit 1aa888fc93609f96cb19afd1a88085471489840b Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 31 17:28:43 2012 -0800 make early serial console support more generic This patch makes pre-RAM serial init more generic, particularly for platforms which do not necessarily need cache-as-RAM in order to use the serial console and do not have a standard 8250 serial port. This adds a Kconfig variable to set romstage-* for very early serial console init. The current method assumes that cache-as-RAM should enable this, so to maintain compatibility selecting CACHE_AS_RAM will also select EARLY_SERIAL_CONSOLE. Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/console/Kconfig | 7 +++++++ src/console/Makefile.inc | 2 +- src/console/console.c | 4 +++- src/cpu/Kconfig | 1 + src/include/uart.h | 4 ---- 5 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 117fdb8..a726c1f 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -5,6 +5,13 @@ config SERIAL_CONSOLE help Send coreboot debug output to a serial port +config EARLY_SERIAL_CONSOLE + bool + select SERIAL_CONSOLE + default n + help + Use serial console during early boot stages (e.g. cache-as-RAM) + config CONSOLE_SERIAL8250 bool "Serial port console output (I/O mapped, 8250-compatible)" depends on SERIAL_CONSOLE diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index a712486..3c4777f 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -10,7 +10,7 @@ smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-y += vtxprintf.c -romstage-$(CONFIG_CACHE_AS_RAM) += console.c +romstage-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c romstage-y += post.c romstage-y += die.c diff --git a/src/console/console.c b/src/console/console.c index d5f25a5..e92dbf6 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -99,13 +99,15 @@ int console_tst_byte(void) #else // __PRE_RAM__ ^^^ NOT defined vvv defined +#include <uart.h> + void console_init(void) { #if CONFIG_USBDEBUG enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_SERIAL_CONSOLE && !CONFIG_CONSOLE_SERIAL8250MEM uart_init(); #endif #if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 383ba79..ddc46cf 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,6 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool + select EARLY_SERIAL_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/include/uart.h b/src/include/uart.h index 931d6dc..ea371c4 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -15,10 +15,6 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * FIXME(dhendrix): This file contains generic prototypes for UART functions. - * The existing headers are too specific to the 8250, so we need a better - * abstraction for use with non-8250 UARTs. */ #ifndef UART_H

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New patch to review for coreboot: 668a858 enable early serial console on exynos5250
by David Hendricks 31 Dec '12

31 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2085 -gerrit commit 668a85883fdbebfdde633604cc91c1c6da6287e4 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 31 17:55:29 2012 -0800 enable early serial console on exynos5250 Change-Id: Ib16308c72b86860e80caec96202c42991a7b1d1a Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index 4a09ca3..abfc049 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -5,6 +5,7 @@ config CPU_SAMSUNG_EXYNOS config CPU_SAMSUNG_EXYNOS5 depends on ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS + select EARLY_SERIAL_CONSOLE bool default n

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New patch to review for coreboot: dcaec83 cleanup some exynos5250 uart code
by David Hendricks 31 Dec '12

31 Dec '12

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2084 -gerrit commit dcaec8388e9f4a4f0bcedfd34a19e4f91fc1ecda Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 31 17:56:22 2012 -0800 cleanup some exynos5250 uart code This just cleans out some unused headers and tidies up the early serial code. TODO: Clean-up or replace FDT code, make "base_port" easier to configure. Change-Id: Ie77ee6d4935346e0053c09252055662f1a45d5f5 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/uart.c | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 3d43976..9f4f7f3 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -21,14 +21,8 @@ * */ -//#include <common.h> -//#include <linux/compiler.h> #include <uart.h> #include <arch/io.h> -//#include <asm/arch-exynos/spl.h> -//#include <asm/global_data.h> -//#include <fdtdec.h> -//#include <serial.h> #include <console/console.h> /* for __console definition */ @@ -180,8 +174,6 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -/* FIXME: ordering of arguments for coreboot v. u-boot for tx_byte */ -//static void exynos5_tx_byte(const char c, const int dev_index) static void exynos5_uart_tx_byte(unsigned char data) { // struct s5p_uart *const uart = s5p_get_base_uart(dev_index); @@ -198,14 +190,6 @@ static void exynos5_uart_tx_byte(unsigned char data) #ifndef __PRE_RAM__ static const struct console_driver exynos5_uart_console __console = { -//static const struct console_driver exynos5_uart_console __console = { -#if 0 - void (*init)(void); - void (*tx_byte)(unsigned char byte); - void (*tx_flush)(void); - unsigned char (*rx_byte)(void); - int (*tst_byte)(void); -#endif .init = exynos5_init_dev, .tx_byte = exynos5_uart_tx_byte, // .tx_flush = exynos5_uart_tx_flush, @@ -213,11 +197,6 @@ static const struct console_driver exynos5_uart_console __console = { // .tst_byte = exynos5_uart_tst_byte, }; #else -/* for romstage_console... */ -//void (*uart_init)(void) = exynos5_init_dev; -//unsigned char (*uart_rx_byte)(unsigned base_port) = exynos5_uart_rx_byte; -//void (*uart_tx_byte)(unsigned base_port, unsigned char data) = exynos5_uart_tx_byte; -/* FIXME: trivial wrappers */ void uart_init() { exynos5_init_dev();

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coreboot January 2013