coreboot January 2013

coreboot@coreboot.org

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New patch to review for coreboot: 23c7a57 armv7: invoke intermediate build rules
by David Hendricks 02 Jan '13

02 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2095 -gerrit commit 23c7a570333e67bd204eb13e6eb95cfc5f52a74a Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 2 17:48:49 2013 -0800 armv7: invoke intermediate build rules This adds $$(INTERMEDIATE) as a pre-requisite for coreboot.rom on armv7. It is modeled after the $(obj)/coreboot.rom rule for x86. Change-Id: I483a88035fa2288829b6e042e51ef932c8c4f23c Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index f911591..8a728a6 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -58,7 +58,7 @@ $(obj)/coreboot.pre1: $(CBFSTOOL) mv $(obj)/coreboot.rom $@ endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp if [ -f $(objcbfs)/coreboot_ap.elf ]; \

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New patch to review for coreboot: cd89cd3 armv7: pass bootblock offset from Kconfig into cbfstool
by David Hendricks 02 Jan '13

02 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2094 -gerrit commit cd89cd38fad64dc3c27cdab91d9df2568d203e8f Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 2 17:47:11 2013 -0800 armv7: pass bootblock offset from Kconfig into cbfstool This replaces a somewhat useless calculation used earlier (which always evaluated to 0) with an offset to specify the location of the Coreboot bootblock. Change-Id: Ib85aaccf138cebeb6bf8aedf82308861206dff48 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index b413d3e..f911591 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -49,7 +49,7 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ -B $(objcbfs)/bootblock.bin -a 64 \ - -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) + -o $(CONFIG_BOOTBLOCK_OFFSET) $(prebuild-files) true mv $@.tmp $@ else

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New patch to review for coreboot: 535a8af snow: Stuff to support building image with BL1
by David Hendricks 02 Jan '13

02 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2093 -gerrit commit 535a8af278eb17bbfe1770d067912c0adca67d4d Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 2 17:41:51 2013 -0800 snow: Stuff to support building image with BL1 This patch does two things which will take effect in follow-up patches: 1. Add an intermediate Makefile rule for dd'ing BL1 into the coreboot.rom pre-image. This is modeled after a similar hack for the bd82x6x southbridge. 2. Add a Kconfig variable, BOOTBLOCK_OFFSET, which will be used to pass the bootblock offset into cbfstool. Change-Id: I89da255dc903c387b754b06a11bb3439035ead87 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5250/Kconfig | 7 +++++++ src/cpu/samsung/exynos5250/Makefile.inc | 10 ++++++++++ 2 files changed, 17 insertions(+) diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index c2d9b9f..360c57f 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,3 +1,10 @@ +config BOOTBLOCK_OFFSET + hex "Bootblock offset" + default 0x3400 + help + This is where the Coreboot bootblock resides. For Exynos5250, + this value is pre-determined by the vendor-provided BL1. + config EXYNOS_ACE_SHA bool default n diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 556631a..1ff2327 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -1,3 +1,8 @@ +# Run an intermediate step when producing coreboot.rom +# that adds additional components to the final firmware +# image outside of CBFS +INTERMEDIATE += exynos5250_add_bl1 + romstage-y += clock.c romstage-y += clock_init.c romstage-y += exynos_cache.c @@ -30,3 +35,8 @@ ramstage-y += uart.c ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c ramstage-$(CONFIG_SPL_BUILD) += dmc_common.c ramstage-$(CONFIG_SPL_BUILD) += dmc_init_ddr3.c + +exynos5250_add_bl1: $(obj)/coreboot.pre + printf " DD Adding Samsung Exynos5250 BL1\n" + dd if=3rdparty/cpu/samsung/exynos5250/E5250.nbl1.bin \ + of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1

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New patch to review for coreboot: 96221a7 add user-specified offset when creating armv7 cbfs image
by David Hendricks 02 Jan '13

02 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2092 -gerrit commit 96221a764767bd54a1b2e508cc18cbc4dcef6df9 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 2 17:29:00 2013 -0800 add user-specified offset when creating armv7 cbfs image The "offs" provided on the command-line was not taken into account when creating an image for armv7... Change-Id: I1781bd636f60c00581f3bd1d54506f0f50bb8ad0 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- util/cbfstool/common.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c index 7e33c97..befdc3f 100644 --- a/util/cbfstool/common.c +++ b/util/cbfstool/common.c @@ -567,10 +567,10 @@ int create_cbfs_image(const char *romfile, uint32_t _romsize, // should be aligned to align but then we need to dynamically // create the jump to the bootblock - loadfile(bootblock, &bootblocksize, romarea + 0x20 + + loadfile(bootblock, &bootblocksize, romarea + offs + 0x20 + sizeof(struct cbfs_header), SEEK_SET); - master_header = (struct cbfs_header *)(romarea + 0x20); - uint32_t *arm_vec = (uint32_t *)romarea; + master_header = (struct cbfs_header *)(romarea + offs + 0x20); + uint32_t *arm_vec = (uint32_t *)(romarea + offs); /* * Encoding for this branch instruction is: * 31:28 - condition (0xe for always/unconditional) @@ -591,16 +591,15 @@ int create_cbfs_image(const char *romfile, uint32_t _romsize, ALIGN((0x40 + bootblocksize), align)); master_header->architecture = htonl(CBFS_ARCHITECTURE_ARMV7); - ((uint32_t *) phys_to_virt(0x4))[0] = + ((uint32_t *) phys_to_virt(0x4 + offs))[0] = virt_to_phys(master_header); recalculate_rom_geometry(romarea); cbfs_create_empty_file( - ALIGN((0x40 + bootblocksize), align), - romsize - ALIGN((bootblocksize + 0x40), align) - //- sizeof(struct cbfs_header) - - sizeof(struct cbfs_file) ); + offs + ALIGN((0x40 + bootblocksize), align), + romsize - offs - sizeof(struct cbfs_file) - + ALIGN((bootblocksize + 0x40), align)); break; case CBFS_ARCHITECTURE_X86:

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Patch merged into coreboot/master: 1e0e556 cbmem utility: support command line options
by gerrit＠coreboot.org 02 Jan '13

02 Jan '13

the following patch was just integrated into master: commit 1e0e55615f86bb9237fa8f4d81158cbf25c65565 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jan 2 15:43:56 2013 -0800 cbmem utility: support command line options The tool could print much more useful information than just time stamps, for example the cbmem console on systems that don't have a kernel patched to support /sys/firmware/log. Hence, add command line option parsing to make adding such features easier in the future. Change-Id: Ib2b2584970f8a4e4187da803fcc5a95469f23a6a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2091 Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Thu Jan 3 01:03:40 2013, giving +1 See http://review.coreboot.org/2091 for details. -gerrit

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Patch merged into coreboot/master: 2c3f260 Fix strcpy()
by gerrit＠coreboot.org 02 Jan '13

02 Jan '13

the following patch was just integrated into master: commit 2c3f2609ca30f6303cec9639bacf1eb40aeee213 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Dec 19 11:22:07 2012 -0800 Fix strcpy() 'nough said. It was broken since 2006. Change-Id: I312ac07eee65d6bb8567851dd38064c7f51b3bd2 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2062 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Build-Tested: build bot (Jenkins) at Thu Jan 3 00:52:42 2013, giving +1 See http://review.coreboot.org/2062 for details. -gerrit

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New patch to review for coreboot: a65ef0f cbmem utility: support command line options
by Stefan Reinauer 02 Jan '13

02 Jan '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2091 -gerrit commit a65ef0f5c38a65049f1d460c3d25b6beeeff0324 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jan 2 15:43:56 2013 -0800 cbmem utility: support command line options The tool could print much more useful information than just time stamps, for example the cbmem console on systems that don't have a kernel patched to support /sys/firmware/log. Hence, add command line option parsing to make adding such features easier in the future. Change-Id: Ib2b2584970f8a4e4187da803fcc5a95469f23a6a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbmem/cbmem.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 31950e2..1cb7b8d 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -21,6 +21,8 @@ #include <stdio.h> #include <stdlib.h> #include <string.h> +#include <unistd.h> +#include <getopt.h> #include "stdlib.h" #include "boot/coreboot_tables.h" @@ -32,6 +34,8 @@ typedef uint64_t u64; #include "cbmem.h" #include "timestamp.h" +#define CBMEM_VERSION "1.0" + /* File descriptor used to access /dev/mem */ static FILE* fd; @@ -246,11 +250,58 @@ static void dump_timestamps(const struct timestamp_table *tst_p) } } +void print_version(void) +{ + printf("cbmem v%s -- ", CBMEM_VERSION); + printf("Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.\n\n"); + printf( + "This program is free software: you can redistribute it and/or modify\n" + "it under the terms of the GNU General Public License as published by\n" + "the Free Software Foundation, version 2 of the License.\n\n" + "This program is distributed in the hope that it will be useful,\n" + "but WITHOUT ANY WARRANTY; without even the implied warranty of\n" + "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n" + "GNU General Public License for more details.\n\n" + "You should have received a copy of the GNU General Public License\n" + "along with this program. If not, see <http://www.gnu.org/licenses/>.\n\n"); +} + +void print_usage(const char *name) +{ + printf("usage: %s [-vh?]\n", name); + printf("\n" + " -v | --version: print the version\n" + " -h | --help: print this help\n" + "\n"); + exit(1); +} int main(int argc, char** argv) { int j; - static const int possible_base_addresses[] = {0, 0xf0000}; + static const int possible_base_addresses[] = { 0, 0xf0000 }; + + int opt, option_index = 0; + static struct option long_options[] = { + {"version", 0, 0, 'v'}, + {"help", 0, 0, 'h'}, + {0, 0, 0, 0} + }; + while ((opt = getopt_long(argc, argv, "vh?", + long_options, &option_index)) != EOF) { + switch (opt) { + case 'v': + print_version(); + exit(0); + break; + case 'h': + case '?': + default: + print_usage(argv[0]); + exit(0); + break; + } + } fd = fopen("/dev/mem", "r"); if (!fd) {

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Patch set updated for coreboot: 1fc6137 Fix strcpy()
by Stefan Reinauer 02 Jan '13

02 Jan '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2062 -gerrit commit 1fc61372dc598b11754e2cecb24ba4a118297bcd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Dec 19 11:22:07 2012 -0800 Fix strcpy() 'nough said. It was broken since 2006. Change-Id: I312ac07eee65d6bb8567851dd38064c7f51b3bd2 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/string.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/include/string.h b/src/include/string.h index 708961b..44f244c 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -69,10 +69,15 @@ static inline char *strncpy(char *to, const char *from, int count) return ret; } -static inline void strcpy(char *dst, const char *src) +static inline char *strcpy(char *dst, const char *src) { + char *ptr = dst; + while (*src) *dst++ = *src++; + *dst = '\0'; + + return ptr; } static inline int strcmp(const char *s1, const char *s2)

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Patch set updated for coreboot: 16a5ddb Add (hacked-up) s3c24x0_i2c files
by David Hendricks 02 Jan '13

02 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2078 -gerrit commit 16a5ddbc14e03d87561712136d13341fdd33c357 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 27 14:06:05 2012 -0800 Add (hacked-up) s3c24x0_i2c files These are needed for communicating with the PMIC on Snow. We'll tidy them up as we go along... Change-Id: I197f59927eae0ad66191862d052de2a8873fb22f Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/s5p-common/Makefile.inc | 2 + src/cpu/samsung/s5p-common/s3c24x0_i2c.c | 640 +++++++++++++++++++++++++++++++ src/cpu/samsung/s5p-common/s3c24x0_i2c.h | 43 +++ 3 files changed, 685 insertions(+) diff --git a/src/cpu/samsung/s5p-common/Makefile.inc b/src/cpu/samsung/s5p-common/Makefile.inc index 9747f0d..7de3c28 100644 --- a/src/cpu/samsung/s5p-common/Makefile.inc +++ b/src/cpu/samsung/s5p-common/Makefile.inc @@ -2,6 +2,7 @@ romstage-y += cpu_info.c romstage-y += pwm.c # needed by timer.c romstage-y += s5p_gpio.c romstage-y += timer.c +romstage-y += s3c24x0_i2c.c #romstage-y += sromc.c #romstage-y += wdt.c @@ -10,3 +11,4 @@ ramstage-y += cpu_info.c ramstage-y += pwm.c # needed by timer.c ramstage-y += timer.c ramstage-y += s5p_gpio.c +ramstage-y += s3c24x0_i2c.c diff --git a/src/cpu/samsung/s5p-common/s3c24x0_i2c.c b/src/cpu/samsung/s5p-common/s3c24x0_i2c.c new file mode 100644 index 0000000..0b6f768 --- /dev/null +++ b/src/cpu/samsung/s5p-common/s3c24x0_i2c.c @@ -0,0 +1,640 @@ +/* + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.mueller(a)elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This code should work for both the S3C2400 and the S3C2410 + * as they seem to have the same I2C controller inside. + * The different address mapping is handled by the s3c24xx.h files below. + */ + +#include <common.h> +#include <arch/io.h> +#include "clk.h" +#include "cpu/samsung/exynos5-common/clk.h" +#include "cpu/samsung/exynos5250/cpu.h" +#include "gpio.h" +#include "cpu/samsung/exynos5250/gpio.h" +#include "cpu/samsung/exynos5250/pinmux.h" + +//#include <fdtdec.h> +#include "device/i2c.h" +#include "s3c24x0_i2c.h" + +/* for board_i2c_* */ +#include "cpu/samsung/exynos5-common/spl.h" + +#define I2C_WRITE 0 +#define I2C_READ 1 + +#define I2C_OK 0 +#define I2C_NOK 1 +#define I2C_NACK 2 +#define I2C_NOK_LA 3 /* Lost arbitration */ +#define I2C_NOK_TOUT 4 /* time out */ + +#define I2CSTAT_BSY 0x20 /* Busy bit */ +#define I2CSTAT_NACK 0x01 /* Nack bit */ +#define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ +#define I2CCON_IRPND 0x10 /* Interrupt pending bit */ +#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ +#define I2C_MODE_MR 0x80 /* Master Receive Mode */ +#define I2C_START_STOP 0x20 /* START / STOP */ +#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ + +/* The timeouts we live by */ +enum { + I2C_XFER_TIMEOUT_MS = 35, /* xfer to complete */ + I2C_INIT_TIMEOUT_MS = 1000, /* bus free on init */ + I2C_IDLE_TIMEOUT_MS = 100, /* waiting for bus idle */ + I2C_STOP_TIMEOUT_US = 200, /* waiting for stop events */ +}; + +/* We should not rely on any particular ordering of these IDs */ +#if 0 +#ifndef CONFIG_OF_CONTROL +static enum periph_id periph_for_dev[EXYNOS_I2C_MAX_CONTROLLERS] = { + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, +}; +#endif +#endif + +static unsigned int g_current_bus __attribute__((section(".data"))); +static struct s3c24x0_i2c *g_early_i2c_config __attribute__((section(".data"))); + +static struct s3c24x0_i2c_bus i2c_bus[EXYNOS_I2C_MAX_CONTROLLERS] + __attribute__((section(".data"))); +static int i2c_busses __attribute__((section(".data"))); + +void i2c_set_early_reg(unsigned int base) +{ + g_early_i2c_config = (struct s3c24x0_i2c *)base; +} + +static struct s3c24x0_i2c_bus *get_bus(int bus_idx) +{ + /* If an early i2c config exists we just use that */ + if (g_early_i2c_config) { + /* FIXME: value not retained from i2c_set_early_reg()? (but then, how + * did if (!i2c) check pass earlier on? Corrupt value? */ + i2c_bus[0].regs = g_early_i2c_config; + return &i2c_bus[0]; + } + + if (bus_idx < i2c_busses) + return &i2c_bus[bus_idx]; + debug("Undefined bus: %d\n", bus_idx); + return NULL; +} + +static inline struct exynos5_gpio_part1 *exynos_get_base_gpio1(void) +{ + return (struct exynos5_gpio_part1 *)(EXYNOS5_GPIO_PART1_BASE); +} + +static int WaitForXfer(struct s3c24x0_i2c *i2c) +{ + int i; + + i = I2C_XFER_TIMEOUT_MS * 20; + while (!(readl(&i2c->iiccon) & I2CCON_IRPND)) { + if (i == 0) { + debug("%s: i2c xfer timeout\n", __func__); + return I2C_NOK_TOUT; + } + udelay(50); + i--; + } + + return I2C_OK; +} + +static int IsACK(struct s3c24x0_i2c *i2c) +{ + return !(readl(&i2c->iicstat) & I2CSTAT_NACK); +} + +static void ReadWriteByte(struct s3c24x0_i2c *i2c) +{ + uint32_t x; + + x = readl(&i2c->iiccon); + writel(x & ~I2CCON_IRPND, &i2c->iiccon); + /* FIXME(dhendrix): cannot use nested macro (compilation failure) */ +// writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); +} + +static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) +{ + ulong freq, pres = 16, div; + + freq = clock_get_periph_rate(PERIPH_ID_I2C0); + /* calculate prescaler and divisor values */ + if ((freq / pres / (16 + 1)) > speed) + /* set prescaler to 512 */ + pres = 512; + + div = 0; + + while ((freq / pres / (div + 1)) > speed) + div++; + + /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */ + writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); + + /* init to SLAVE REVEIVE and set slaveaddr */ + writel(0, &i2c->iicstat); + writel(slaveadd, &i2c->iicadd); + /* program Master Transmit (and implicit STOP) */ + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); +} + +/* TODO: determine if this is necessary to init board using FDT-provided info */ +#if 0 +void board_i2c_init(const void *blob) +{ + /* + * Turn off the early i2c configuration and init the i2c properly, + * this is done here to enable the use of i2c configs from FDT. + */ + i2c_set_early_reg(0); + +#ifdef CONFIG_OF_CONTROL + int node_list[EXYNOS_I2C_MAX_CONTROLLERS]; + int i, count; + + count = fdtdec_find_aliases_for_id(blob, "i2c", + COMPAT_SAMSUNG_S3C2440_I2C, node_list, + EXYNOS_I2C_MAX_CONTROLLERS); + + for (i = 0; i < count; i++) { + struct s3c24x0_i2c_bus *bus; + int node = node_list[i]; + + if (node < 0) + continue; + bus = &i2c_bus[i2c_busses]; + bus->regs = (struct s3c24x0_i2c *) + fdtdec_get_addr(blob, node, "reg"); + bus->id = (enum periph_id) + fdtdec_get_int(blob, node, "samsung,periph-id", -1); + bus->node = node; + bus->bus_num = i2c_busses++; + } +#else + int i; + + for (i = 0; i < EXYNOS_I2C_MAX_CONTROLLERS; i++) { + uintptr_t reg_addr = samsung_get_base_i2c() + + EXYNOS_I2C_SPACING * i; + + i2c_bus[i].regs = (struct s3c24x0_i2c_bus *)reg_addr; + i2c_bus[i].id = periph_for_dev[i]; + } + i2c_busses = EXYNOS_I2C_MAX_CONTROLLERS; +#endif +} +#endif + +/* + * MULTI BUS I2C support + */ +/* + * FIXME(dhendrix): not sure why this had to be guarded, but the code + * should probably go into an exynos5-specific .c file if it really is + * not generic. + */ +//#ifdef CONFIG_EXYNOS5 +static void i2c_bus_init(struct s3c24x0_i2c_bus *i2c, unsigned int bus) +{ + exynos_pinmux_config(i2c->id, 0); + + i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +} +//#else +//#error "should not be here" +//static void i2c_bus_init(struct s3c24x0_i2c_bus *i2c, unsigned int bus) {} +//#endif + +#ifdef CONFIG_I2C_MULTI_BUS +int i2c_set_bus_num(unsigned int bus) +{ + struct s3c24x0_i2c_bus *i2c; + + i2c = get_bus(bus); + if (!i2c) + return -1; + g_current_bus = bus; + i2c_bus_init(i2c, g_current_bus); + + return 0; +} + +unsigned int i2c_get_bus_num(void) +{ + return g_current_bus; +} +#endif + +#ifdef CONFIG_OF_CONTROL +int i2c_get_bus_num_fdt(const void *blob, int node) +{ + enum fdt_compat_id compat; + fdt_addr_t reg; + int i; + + compat = fdtdec_lookup(blob, node); + if (compat != COMPAT_SAMSUNG_S3C2440_I2C) { + debug("%s: Not a supported I2C node\n", __func__); + return -1; + } + + reg = fdtdec_get_addr(blob, node, "reg"); + for (i = 0; i < i2c_busses; i++) + if (reg == (fdt_addr_t)(uintptr_t)i2c_bus[i].regs) + return i; + + debug("%s: Can't find any matched I2C bus\n", __func__); + return -1; +} + +int i2c_reset_port_fdt(const void *blob, int node) +{ + struct s3c24x0_i2c_bus *i2c; + + int bus; + + bus = i2c_get_bus_num_fdt(blob, node); + if (bus < 0) { + printf("could not get bus for node %d\n", node); + return -1; + } + i2c = get_bus(bus); + if (!i2c) { + printf("get_bus() failed for node node %d\n", node); + return -1; + } + + i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + return 0; +} +#endif + +/* + * Verify the whether I2C ACK was received or not + * + * @param i2c pointer to I2C register base + * @param buf array of data + * @param len length of data + * return I2C_OK when transmission done + * I2C_NACK otherwise + */ +static int i2c_send_verify(struct s3c24x0_i2c *i2c, unsigned char buf[], + unsigned char len) +{ + int i, result = I2C_OK; + + if (IsACK(i2c)) { + for (i = 0; (i < len) && (result == I2C_OK); i++) { + writel(buf[i], &i2c->iicds); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); + if (result == I2C_OK && !IsACK(i2c)) + result = I2C_NACK; + } + } else { + result = I2C_NACK; + } + + return result; +} + +void i2c_init(int speed, int slaveadd) +{ + struct s3c24x0_i2c_bus *i2c; + struct exynos5_gpio_part1 *gpio; + int i; + uint32_t x; + + /* By default i2c channel 0 is the current bus */ + g_current_bus = 0; + + i2c = get_bus(g_current_bus); + if (!i2c) + return; + + i2c_bus_init(i2c, g_current_bus); + + /* wait for some time to give previous transfer a chance to finish */ + i = I2C_INIT_TIMEOUT_MS * 20; + while ((readl(&i2c->regs->iicstat) & I2CSTAT_BSY) && (i > 0)) { + udelay(50); + i--; + } + + gpio = exynos_get_base_gpio1(); + /* FIXME(dhendrix): cannot use nested macro (compilation failure) */ +// writel((readl(&gpio->b3.con) & ~0x00FF) | 0x0022, &gpio->b3.con); + x = readl(&gpio->b3.con); + writel((x & ~0x00FF) | 0x0022, &gpio->b3.con); + + i2c_ch_init(i2c->regs, speed, slaveadd); +} + +/* + * Send a STOP event and wait for it to have completed + * + * @param mode If it is a master transmitter or receiver + * @return I2C_OK if the line became idle before timeout I2C_NOK_TOUT otherwise + */ +static int i2c_send_stop(struct s3c24x0_i2c *i2c, int mode) +{ + int timeout; + + /* Setting the STOP event to fire */ + writel(mode | I2C_TXRX_ENA, &i2c->iicstat); + ReadWriteByte(i2c); + + /* Wait for the STOP to send and the bus to go idle */ + for (timeout = I2C_STOP_TIMEOUT_US; timeout > 0; timeout -= 5) { + if (!(readl(&i2c->iicstat) & I2CSTAT_BSY)) + return I2C_OK; + udelay(5); + } + + return I2C_NOK_TOUT; +} + +/* + * cmd_type is 0 for write, 1 for read. + * + * addr_len can take any value from 0-255, it is only limited + * by the char, we could make it larger if needed. If it is + * 0 we skip the address write cycle. + */ +static int i2c_transfer(struct s3c24x0_i2c *i2c, + unsigned char cmd_type, + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], + unsigned short data_len) +{ + int i, result, stop_bit_result; + uint32_t x; + + if (data == 0 || data_len == 0) { + /* Don't support data transfer of no length or to address 0 */ + debug("i2c_transfer: bad call\n"); + return I2C_NOK; + } + + /* Check I2C bus idle */ + i = I2C_IDLE_TIMEOUT_MS * 20; + while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { + udelay(50); + i--; + } + + if (readl(&i2c->iicstat) & I2CSTAT_BSY) { + debug("%s: bus busy\n", __func__); + return I2C_NOK_TOUT; + } + + /* FIXME(dhendrix): cannot use nested macro (compilation failure) */ + //writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); + x = readl(&i2c->iiccon); + writel(x | I2CCON_ACKGEN, &i2c->iiccon); + + if (addr && addr_len) { + writel(chip, &i2c->iicds); + /* send START */ + writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, + &i2c->iicstat); + if (WaitForXfer(i2c) == I2C_OK) + result = i2c_send_verify(i2c, addr, addr_len); + else + result = I2C_NACK; + } else + result = I2C_NACK; + + switch (cmd_type) { + case I2C_WRITE: + if (result == I2C_OK) + result = i2c_send_verify(i2c, data, data_len); + else { + writel(chip, &i2c->iicds); + /* send START */ + writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, + &i2c->iicstat); + if (WaitForXfer(i2c) == I2C_OK) + result = i2c_send_verify(i2c, data, data_len); + } + + if (result == I2C_OK) + result = WaitForXfer(i2c); + + stop_bit_result = i2c_send_stop(i2c, I2C_MODE_MT); + break; + + case I2C_READ: + { + int was_ok = (result == I2C_OK); + + writel(chip, &i2c->iicds); + /* resend START */ + writel(I2C_MODE_MR | I2C_TXRX_ENA | + I2C_START_STOP, &i2c->iicstat); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); + + if (was_ok || IsACK(i2c)) { + i = 0; + while ((i < data_len) && (result == I2C_OK)) { + /* disable ACK for final READ */ + if (i == data_len - 1) { + /* FIXME(dhendrix): nested macro */ +#if 0 + writel(readl(&i2c->iiccon) & + ~I2CCON_ACKGEN, + &i2c->iiccon); +#endif + x = readl(&i2c->iiccon) & ~I2CCON_ACKGEN; + writel(x, &i2c->iiccon); + } + ReadWriteByte(i2c); + result = WaitForXfer(i2c); + data[i] = readl(&i2c->iicds); + i++; + } + } else { + result = I2C_NACK; + } + + stop_bit_result = i2c_send_stop(i2c, I2C_MODE_MR); + break; + } + + default: + debug("i2c_transfer: bad call\n"); + result = stop_bit_result = I2C_NOK; + break; + } + + /* + * If the transmission went fine, then only the stop bit was left to + * fail. Otherwise, the real failure we're interested in came before + * that, during the actual transmission. + */ + return (result == I2C_OK) ? stop_bit_result : result; +} + +int i2c_probe(uchar chip) +{ + struct s3c24x0_i2c_bus *i2c; + uchar buf[1]; + int ret; + + i2c = get_bus(g_current_bus); + if (!i2c) + return -1; + buf[0] = 0; + + /* + * What is needed is to send the chip address and verify that the + * address was <ACK>ed (i.e. there was a chip at that address which + * drove the data line low). + */ + if (board_i2c_claim_bus(i2c->node)) { + debug("I2C cannot claim bus %d\n", i2c->bus_num); + return -1; + } + ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, 0, 0, buf, 1); + board_i2c_release_bus(i2c->node); + + return ret != I2C_OK; +} + +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + struct s3c24x0_i2c_bus *i2c; + uchar xaddr[4]; + int ret; + + if (alen > 4) { + debug("I2C read: addr len %d not supported\n", alen); + return 1; + } + + if (alen > 0) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } + +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); +#endif + i2c = get_bus(g_current_bus); + if (!i2c) + return -1; + if (board_i2c_claim_bus(i2c->node)) { + debug("I2C cannot claim bus %d\n", i2c->bus_num); + return -1; + } + ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen], + alen, buffer, len); + board_i2c_release_bus(i2c->node); + if (ret) { + debug("I2c read: failed %d\n", ret); + return 1; + } + return 0; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + struct s3c24x0_i2c_bus *i2c; + uchar xaddr[4]; + int ret; + + if (alen > 4) { + debug("I2C write: addr len %d not supported\n", alen); + return 1; + } + + if (alen > 0) { + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + } +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW + /* + * EEPROM chips that implement "address overflow" are ones + * like Catalyst 24WC04/08/16 which has 9/10/11 bits of + * address and the extra bits end up in the "chip address" + * bit slots. This makes a 24WC08 (1Kbyte) chip look like + * four 256 byte chips. + * + * Note that we consider the length of the address field to + * still be one byte because the extra address bits are + * hidden in the chip address. + */ + if (alen > 0) + chip |= ((addr >> (alen * 8)) & + CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); +#endif + i2c = get_bus(g_current_bus); + if (!i2c) + return -1; + if (board_i2c_claim_bus(i2c->node)) { + debug("I2C cannot claim bus %d\n", i2c->bus_num); + return -1; + } + ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen], + alen, buffer, len); + board_i2c_release_bus(i2c->node); + + return ret != 0; +} diff --git a/src/cpu/samsung/s5p-common/s3c24x0_i2c.h b/src/cpu/samsung/s5p-common/s3c24x0_i2c.h new file mode 100644 index 0000000..eb68af7 --- /dev/null +++ b/src/cpu/samsung/s5p-common/s3c24x0_i2c.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _S3C24X0_I2C_H +#define _S3C24X0_I2C_H + +/* FIXME: gross hack */ +#include "cpu/samsung/exynos5250/periph.h" + +struct s3c24x0_i2c { + u32 iiccon; + u32 iicstat; + u32 iicadd; + u32 iicds; + u32 iiclc; +}; + +struct s3c24x0_i2c_bus { + int node; /* device tree node */ + int bus_num; /* i2c bus number */ + struct s3c24x0_i2c *regs; + enum periph_id id; +}; +#endif /* _S3C24X0_I2C_H */

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Patch set updated for coreboot: 51e3674 enable early serial console on exynos5250
by David Hendricks 02 Jan '13

02 Jan '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2085 -gerrit commit 51e3674e977117da41e97c601ddc51dd528812aa Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 31 17:55:29 2012 -0800 enable early serial console on exynos5250 Change-Id: Ib16308c72b86860e80caec96202c42991a7b1d1a Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index 4a09ca3..abfc049 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -5,6 +5,7 @@ config CPU_SAMSUNG_EXYNOS config CPU_SAMSUNG_EXYNOS5 depends on ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS + select EARLY_SERIAL_CONSOLE bool default n

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coreboot January 2013