coreboot January 2013

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Patch set updated for coreboot: c792fe5 make early serial console support more generic
by Ronald G. Minnich 03 Jan '13

03 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2086 -gerrit commit c792fe553bce0a0ad06d47f4da777a9e2911a3d0 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 31 17:28:43 2012 -0800 make early serial console support more generic This patch makes pre-RAM serial init more generic, particularly for platforms which do not necessarily need cache-as-RAM in order to use the serial console and do not have a standard 8250 serial port. This adds a Kconfig variable to set romstage-* for very early serial console init. The current method assumes that cache-as-RAM should enable this, so to maintain compatibility selecting CACHE_AS_RAM will also select EARLY_SERIAL_CONSOLE. Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/console/Kconfig | 7 +++++++ src/console/Makefile.inc | 2 +- src/console/console.c | 4 +++- src/cpu/Kconfig | 1 + src/include/uart.h | 4 ---- src/include/uart8250.h | 1 - 6 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 117fdb8..a726c1f 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -5,6 +5,13 @@ config SERIAL_CONSOLE help Send coreboot debug output to a serial port +config EARLY_SERIAL_CONSOLE + bool + select SERIAL_CONSOLE + default n + help + Use serial console during early boot stages (e.g. cache-as-RAM) + config CONSOLE_SERIAL8250 bool "Serial port console output (I/O mapped, 8250-compatible)" depends on SERIAL_CONSOLE diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index a712486..3c4777f 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -10,7 +10,7 @@ smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-y += vtxprintf.c -romstage-$(CONFIG_CACHE_AS_RAM) += console.c +romstage-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c romstage-y += post.c romstage-y += die.c diff --git a/src/console/console.c b/src/console/console.c index d5f25a5..e92dbf6 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -99,13 +99,15 @@ int console_tst_byte(void) #else // __PRE_RAM__ ^^^ NOT defined vvv defined +#include <uart.h> + void console_init(void) { #if CONFIG_USBDEBUG enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_SERIAL_CONSOLE && !CONFIG_CONSOLE_SERIAL8250MEM uart_init(); #endif #if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 383ba79..ddc46cf 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,6 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool + select EARLY_SERIAL_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/include/uart.h b/src/include/uart.h index 931d6dc..ea371c4 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -15,10 +15,6 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * FIXME(dhendrix): This file contains generic prototypes for UART functions. - * The existing headers are too specific to the 8250, so we need a better - * abstraction for use with non-8250 UARTs. */ #ifndef UART_H diff --git a/src/include/uart8250.h b/src/include/uart8250.h index b00ff48..3366975 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -125,7 +125,6 @@ void uart8250_tx_flush(unsigned base_port); * have three different sets of uart code, so it's an improvement. */ void uart8250_init(unsigned base_port, unsigned divisor); -void uart_init(void); #endif #if CONFIG_CONSOLE_SERIAL8250MEM void uartmem_init(void);

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Patch set updated for coreboot: 2f8e7ac make early serial console support more generic
by Ronald G. Minnich 03 Jan '13

03 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2086 -gerrit commit 2f8e7ace9b4a6d0373c32cdbec24f61fba12c13f Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Dec 31 17:28:43 2012 -0800 make early serial console support more generic This patch makes pre-RAM serial init more generic, particularly for platforms which do not necessarily need cache-as-RAM in order to use the serial console and do not have a standard 8250 serial port. This adds a Kconfig variable to set romstage-* for very early serial console init. The current method assumes that cache-as-RAM should enable this, so to maintain compatibility selecting CACHE_AS_RAM will also select EARLY_SERIAL_CONSOLE. Change-Id: I089e7af633c227baf3c06c685f005e9d0e4b38ce Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/console/Kconfig | 7 +++++++ src/console/Makefile.inc | 2 +- src/console/console.c | 4 +++- src/cpu/Kconfig | 1 + src/include/uart.h | 4 ---- 5 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 117fdb8..a726c1f 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -5,6 +5,13 @@ config SERIAL_CONSOLE help Send coreboot debug output to a serial port +config EARLY_SERIAL_CONSOLE + bool + select SERIAL_CONSOLE + default n + help + Use serial console during early boot stages (e.g. cache-as-RAM) + config CONSOLE_SERIAL8250 bool "Serial port console output (I/O mapped, 8250-compatible)" depends on SERIAL_CONSOLE diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index a712486..3c4777f 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -10,7 +10,7 @@ smm-y += vtxprintf.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-y += vtxprintf.c -romstage-$(CONFIG_CACHE_AS_RAM) += console.c +romstage-$(CONFIG_EARLY_SERIAL_CONSOLE) += console.c romstage-y += post.c romstage-y += die.c diff --git a/src/console/console.c b/src/console/console.c index d5f25a5..e92dbf6 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -99,13 +99,15 @@ int console_tst_byte(void) #else // __PRE_RAM__ ^^^ NOT defined vvv defined +#include <uart.h> + void console_init(void) { #if CONFIG_USBDEBUG enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_SERIAL_CONSOLE && !CONFIG_CONSOLE_SERIAL8250MEM uart_init(); #endif #if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 383ba79..ddc46cf 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,6 +16,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool + select EARLY_SERIAL_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/include/uart.h b/src/include/uart.h index 931d6dc..ea371c4 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -15,10 +15,6 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * FIXME(dhendrix): This file contains generic prototypes for UART functions. - * The existing headers are too specific to the 8250, so we need a better - * abstraction for use with non-8250 UARTs. */ #ifndef UART_H

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New patch to review for coreboot: bcfe3a6 Add the push default to 'make gitconfig'
by Ronald G. Minnich 03 Jan '13

03 Jan '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2096 -gerrit commit bcfe3a64fbfa64e09178f2a4bb7555ccbe2da538 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Jan 3 08:26:09 2013 -0800 Add the push default to 'make gitconfig' It's too easy to forget this and it's kind of important, so Just Add It. Change-Id: Ic7ab7658425a98d5d435bfef46f89cc6a56c7284 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile.inc b/Makefile.inc index b0a5341..a066e25 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -340,6 +340,7 @@ gitconfig: chmod +x .git/hooks/$$hook; \ fi; \ done + git config remote.origin.push HEAD:refs/for/master (git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1) crossgcc: clean-for-update

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Patch merged into coreboot/master: ec8d35f armv7: pass bootblock offset from Kconfig into cbfstool
by gerrit＠coreboot.org 02 Jan '13

02 Jan '13

the following patch was just integrated into master: commit ec8d35fe911ab35a5f40fd5b452f5463857b244a Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 2 17:47:11 2013 -0800 armv7: pass bootblock offset from Kconfig into cbfstool This replaces a somewhat useless calculation used earlier (which always evaluated to 0) with an offset to specify the location of the Coreboot bootblock. Change-Id: Ib85aaccf138cebeb6bf8aedf82308861206dff48 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2094 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Jan 3 03:37:38 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jan 3 06:46:35 2013, giving +2 See http://review.coreboot.org/2094 for details. -gerrit

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Patch merged into coreboot/master: 4c2245e snow: Stuff to support building image with BL1
by gerrit＠coreboot.org 02 Jan '13

02 Jan '13

the following patch was just integrated into master: commit 4c2245eb67b0eabf18fc9b6788bc05d962ef5e0e Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 2 17:41:51 2013 -0800 snow: Stuff to support building image with BL1 This patch does two things which will take effect in follow-up patches: 1. Add an intermediate Makefile rule for dd'ing BL1 into the coreboot.rom pre-image. This is modeled after a similar hack for the bd82x6x southbridge. 2. Add a Kconfig variable, BOOTBLOCK_OFFSET, which will be used to pass the bootblock offset into cbfstool. Change-Id: I89da255dc903c387b754b06a11bb3439035ead87 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2093 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Jan 3 03:30:35 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jan 3 06:46:08 2013, giving +2 See http://review.coreboot.org/2093 for details. -gerrit

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Patch merged into coreboot/master: 454856b add user-specified offset when creating armv7 cbfs image
by gerrit＠coreboot.org 02 Jan '13

02 Jan '13

the following patch was just integrated into master: commit 454856b274ed81babdcea4b4ed5fb922fe0caf89 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed Jan 2 17:29:00 2013 -0800 add user-specified offset when creating armv7 cbfs image The "offs" provided on the command-line was not taken into account when creating an image for armv7... Change-Id: I1781bd636f60c00581f3bd1d54506f0f50bb8ad0 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2092 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Jan 3 03:22:44 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jan 3 06:45:24 2013, giving +2 See http://review.coreboot.org/2092 for details. -gerrit

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Patch merged into coreboot/master: 45256b3 Add (hacked-up) s3c24x0_i2c files
by gerrit＠coreboot.org 02 Jan '13

02 Jan '13

the following patch was just integrated into master: commit 45256b3bfc18c2b1183238738d3f97474583b949 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 27 14:06:05 2012 -0800 Add (hacked-up) s3c24x0_i2c files These are needed for communicating with the PMIC on Snow. We'll tidy them up as we go along... Change-Id: I197f59927eae0ad66191862d052de2a8873fb22f Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2078 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Jan 2 23:52:09 2013, giving +1 See http://review.coreboot.org/2078 for details. -gerrit

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Patch merged into coreboot/master: d3c7530 import SPL files for board_i2c_{claim, release}_bus()
by gerrit＠coreboot.org 02 Jan '13

02 Jan '13

the following patch was just integrated into master: commit d3c7530908463537c38d84d47d0c29a3bc5dac63 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 27 15:11:27 2012 -0800 import SPL files for board_i2c_{claim,release}_bus() This imports SPL (second phase loader) files from U-Boot. Most of the content of these files will eventually go away since they're fairly U-Boot specific. For now they are here to make Jenkins happy. Change-Id: Ib3a365ecb9dc304b20f7c1c06665aad2c0c53e69 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2081 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Jan 2 23:30:44 2013, giving +1 See http://review.coreboot.org/2081 for details. -gerrit

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Patch merged into coreboot/master: 8583ac3 armv7: create init.S for early ARMv7 init
by gerrit＠coreboot.org 02 Jan '13

02 Jan '13

the following patch was just integrated into master: commit 8583ac390a23a09c4bf75b3b9a9f2294d0523d87 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Dec 27 15:23:57 2012 -0800 armv7: create init.S for early ARMv7 init The old start.S file did a lot of work and had AP-specific #ifndef's. The new init.S will eventually contain only bare minimum generic ARM code for use by the bootblock. Processor-specific stuff and things that take place later in the boot process should go elsewhere. Change-Id: I7db0a77ee4bbad1ddecb193ea125d8941a50532b Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/2083 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jan 2 23:23:00 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jan 3 06:41:36 2013, giving +2 See http://review.coreboot.org/2083 for details. -gerrit

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Re: [coreboot] Feedback On Coreboot: the Solution to the Secure Boot Fiasco
by ron minnich 02 Jan '13

02 Jan '13

My take on it is that people are optimistic about solving the problems (good) but I'm pretty sure it's going to be a long and unpleasant trip. I don't know why they don't take all the effort they're putting into this and put it into more open systems instead. ron On Wed, Jan 2, 2013 at 11:28 AM, David Hubbard <david.c.hubbard+coreboot(a)gmail.com> wrote: > On Wed, Jan 2, 2013 at 11:04 AM, ron minnich <rminnich(a)gmail.com> wrote: >> >> On Wed, Jan 2, 2013 at 9:58 AM, Andrew Goodbody <ajg4tadpole(a)gmail.com> >> wrote: >> >> > I am sure that it is the old story, most testing will be done against >> > Windows. Anything more will be the exception. This is where the pressure >> > needs to be put on the platform vendors as this is the part that they >> > are >> > responsible for. >> >> Sorry, vendors don't have a pattern of paying attention to end user >> sales issues such as "won't boot Linux". They are selling into a >> market in which Linux is about 1% at best of sales. That's been the >> common experience anyway, even at very large companies: BIOS issues >> just don't get fixed. >> > > Andrew, Ron, what's your take on http://mjg59.dreamwidth.org/20916.html ? > > Specifically: > "This is part of Windows 8's fast boot support - the keyboard may not be > initialised until after the OS has started." > > So the logic goes: > 1. Secure Boot enabled and Win8 installed by the OEM > > 2. To access the BIOS, press F2/F8/DEL/whatever > > 3. "Fast boot" (hey! coreboot delivered on that first!) skips keyboard init > > 4. User is thus *forced* to use Win8's "hold down shift and restart" feature > -- adding another barrier before a user can boot her own OS. > > I think the biggest problem here is that the entire BIOS is made > inaccessible, and only if Windows gives permission can you change that. > > Regards, > David

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coreboot January 2013