coreboot January 2013

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607 discussions

Coreboot Seabios's Makefile.inc build issue.
by Denis 'GNUtoo' Carikli 02 Feb '13

02 Feb '13

Hi, When building SeaBIOS from 1.7.1 coreboot builds correctly. But when I try master it fails this way: make[2]: *** No rule to make target `out/misc.o', needed by `/home/gnutoo/x86/coreboot/build/seabios/out/ccode32flat.o'. Stop. I've tried a lot of combinaisons in the Makefile.inc that is in payloads/external/SeaBIOS but I didn't succeed at fixing it. I also lack the time to fix it right now, and that issue has been there for a long time... However running the following command in coreboot's topdir make it succeed: make -C build/seabios Then a normal make finishes to compiles coreboot. Denis.

2 2

Re: [coreboot] Guide lines: Prepend commit summary with component (was: New patch to review for coreboot: 0b41858 Clean up the mmu setup a bit)
by Peter Stuge 01 Feb '13

01 Feb '13

David Hendricks wrote: > If you wish to focus only on a particular part of the codebase It's more about getting an overview of what has changed. It is impossible to discern whether "Fix MMU setup" is at all relevant for my ThinkPad from the message alone. Maybe some setup was wrong - what do I know. "armv7: Fix MMU setup" however makes it clear what the change is. > specify the directories/files you wish to look at when running git log. It's the other way around, for creating an overview. The commit message represents the commit. The commit contains a root tree. Commits only affecting subsets of the code isn't really an accurate representation of how the repository works. > Actually, I think it would look kind of ugly to do "git log src/arch/x86" > and see every commit cluttered with some cookie-cutter prefix. Maybe - or maybe it is simply expected. Within x86 it's possible that there will be several different and distinct parts. //Peter

3 2

Re: [coreboot] Different Google copyright notices: »The Chromium OS Authors.« or Google, Inc.
by Peter Stuge 01 Feb '13

01 Feb '13

ron minnich wrote: > > In the community we can of course not know what is correct when, > > ah yes well I do kind of wonder if *I* know what I'm doing half the > time :-) I guess the concern was that perhaps there was a single correct notice to be used, and that some of you guys made a mistake somewhere. I don't expect that you make such mistakes, but I guess that's what Paul meant. //Peter

3 2

Patch merged into coreboot/master: 79e36d9 Improve how our printk calls do_div by using constants.
by gerrit＠coreboot.org 31 Jan '13

31 Jan '13

the following patch was just integrated into master: commit 79e36d90608a929c33b655c6fb6376f33f332e6f Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Jan 30 14:29:34 2013 -0800 Improve how our printk calls do_div by using constants. The do_div code has a nice optimization in it when it is called with constants. The current highly generalized use of it defeats those optimizations and causes trouble on ARM, resulting in a complex and buggy code path. Since we only need to print in bases 8, 10, and 16, do a minor restructuring of the code so that we call do_div with constants. If you need base 2, print in base 16 and do it in your head. :-) This fixes an ongoing problem with ARM, will not harm X86, and will help PPC should we ever want to support it again. Plus, I don't have to ever try to understand the div64 assembly and where it's going wrong :-) Change-Id: I6a480011916eb0834e05c5bb10909d83330fe797 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2235 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Wed Jan 30 23:38:01 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Jan 31 01:23:18 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Thu Jan 31 01:04:27 2013, giving +2 See http://review.coreboot.org/2235 for details. -gerrit

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Patch set updated for coreboot: 278a96f Fam15tn: Move SPD read from mainboards into wrapper
by Martin Roth 31 Jan '13

31 Jan '13

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2190 -gerrit commit 278a96f565b68ac96969a1c2ce43150f682de9dc Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Jan 20 10:38:58 2013 -0700 Fam15tn: Move SPD read from mainboards into wrapper Continuing with the mainboard cleanup for F15tn, move the functions to read the SPD from the mainboards for Thatcher and Parmer into the wrapper for the northbridge/amd/agesa/family15tn. Move the SPD address customization for the mainboard into the devicetree.cb file. Unrelated side note - Porting.h has an un-closed #pragma pack(1) that can cause confusing side-effects. AGESA's structures all use this, but coreboot's don't. Be sure to include the coreboot .h files BEFORE Porting.h is included, not after. This fix has been tested. Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 15 +- src/mainboard/amd/parmer/BiosCallOuts.h | 3 - src/mainboard/amd/parmer/Makefile.inc | 2 - src/mainboard/amd/parmer/devicetree.cb | 16 +- src/mainboard/amd/parmer/dimmSpd.c | 164 -------------------- src/mainboard/amd/parmer/dimmSpd.h | 59 -------- src/mainboard/amd/thatcher/BiosCallOuts.c | 15 +- src/mainboard/amd/thatcher/BiosCallOuts.h | 3 - src/mainboard/amd/thatcher/Makefile.inc | 2 - src/mainboard/amd/thatcher/devicetree.cb | 16 +- src/mainboard/amd/thatcher/dimmSpd.c | 166 --------------------- src/mainboard/amd/thatcher/dimmSpd.h | 59 -------- src/northbridge/amd/agesa/family15tn/Makefile.inc | 3 +- src/northbridge/amd/agesa/family15tn/chip.h | 28 ++++ src/northbridge/amd/agesa/family15tn/dimmSpd.c | 160 ++++++++++++++++++++ src/northbridge/amd/agesa/family15tn/dimmSpd.h | 56 +++++++ .../amd/agesa/family15tn/fam15tn_callouts.c | 8 + .../amd/agesa/family15tn/fam15tn_callouts.h | 1 + 18 files changed, 277 insertions(+), 499 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 8bfde14..c3e57c8 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -19,7 +19,6 @@ #include "agesawrapper.h" #include "amdlib.h" -#include "dimmSpd.h" #include "BiosCallOuts.h" #include "Ids.h" #include "OptionsIds.h" @@ -33,10 +32,10 @@ STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, {AGESA_DO_RESET, fam15tn_Reset }, {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, - {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD, fam15tn_ReadSpd }, {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, - {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, + {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, fam15tn_HookBeforeDQSTraining }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, fam15tn_HookBeforeExitSelfRefresh }, {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, @@ -63,14 +62,6 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return CalloutStatus; } -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); - - return Status; -} - /** * AMD Parmer Platform ALC272 Verb Table */ diff --git a/src/mainboard/amd/parmer/BiosCallOuts.h b/src/mainboard/amd/parmer/BiosCallOuts.h index 66db8cd..d42683e 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.h +++ b/src/mainboard/amd/parmer/BiosCallOuts.h @@ -25,9 +25,6 @@ /* CALLOUT Initialization */ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* AGESA ADVANCED CALLOUTS - MEMORY */ -AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); - /* FCH OEM Config*/ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc index de3163d..a83297a 100644 --- a/src/mainboard/amd/parmer/Makefile.inc +++ b/src/mainboard/amd/parmer/Makefile.inc @@ -19,12 +19,10 @@ romstage-y += buildOpts.c romstage-y += agesawrapper.c -romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c -ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index 3e3e371..9dbdc98 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -51,16 +51,10 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 13.2 on end # USB device pci 14.0 on # SMBUS chip drivers/generic/generic #dimm 0 - device i2c 50 on end + device i2c 50 on end # 7-bit SPD address end chip drivers/generic/generic #dimm 1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device i2c 51 on end # 7-bit SPD address end end # SM device pci 14.1 on end # IDE 0x439c @@ -85,6 +79,12 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 18.4 on end device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #pci_domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/parmer/dimmSpd.c b/src/mainboard/amd/parmer/dimmSpd.c deleted file mode 100644 index 576de7e..0000000 --- a/src/mainboard/amd/parmer/dimmSpd.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "dimmSpd.h" - -#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) - -/*#pragma optimize ("", off) // for source level debug - *--------------------------------------------------------------------------- - * - * SPD address table - porting required - */ - -static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm -{ - // socket 0 - { - {0xA0, 0x00}, // channel 0 dimms - {0xA2, 0x00}, // channel 1 dimms - }, - // socket 1 - { - {0x00, 0x00}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, -}; - -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) -{ - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*----------------------------------------------------------------------------- - * - * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - */ - -static int readSmbusByte (int iobase, int address, char *buffer) -{ - unsigned int status; - UINT64 limit; - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*--------------------------------------------------------------------------- - * - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) -{ - int index, error; - - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) return error; - - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); - if (error) return error; - } - - return 0; -} - -static void writePmReg (int reg, int data) -{ - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); -} - -static void setupFch (int ioBase) -{ - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz -} - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) -{ - int spdAddress, ioBase; - - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) return AGESA_ERROR; - ioBase = 0xB00; - setupFch (ioBase); - return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); -} diff --git a/src/mainboard/amd/parmer/dimmSpd.h b/src/mainboard/amd/parmer/dimmSpd.h deleted file mode 100644 index c19cecc..0000000 --- a/src/mainboard/amd/parmer/dimmSpd.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#ifndef _DIMMSPD_H_ -#define _DIMMSPD_H_ - -#include "Porting.h" -#include "AGESA.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData); - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -#endif diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index b82c56b..359ae78 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -19,7 +19,6 @@ #include "agesawrapper.h" #include "amdlib.h" -#include "dimmSpd.h" #include "BiosCallOuts.h" #include "Ids.h" #include "OptionsIds.h" @@ -33,10 +32,10 @@ STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DEALLOCATE_BUFFER, fam15tn_DeallocateBuffer }, {AGESA_DO_RESET, fam15tn_Reset }, {AGESA_LOCATE_BUFFER, fam15tn_LocateBuffer }, - {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD, fam15tn_ReadSpd }, {AGESA_READ_SPD_RECOVERY, fam15tn_DefaultRet }, - {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, - {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, + {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, fam15tn_GetIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, fam15tn_HookBeforeDQSTraining }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, fam15tn_HookBeforeExitSelfRefresh }, {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, @@ -63,14 +62,6 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return CalloutStatus; } -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); - - return Status; -} - /** * AMD Thatcher Platform ALC272 Verb Table */ diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.h b/src/mainboard/amd/thatcher/BiosCallOuts.h index 66db8cd..d42683e 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.h +++ b/src/mainboard/amd/thatcher/BiosCallOuts.h @@ -25,9 +25,6 @@ /* CALLOUT Initialization */ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* AGESA ADVANCED CALLOUTS - MEMORY */ -AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); - /* FCH OEM Config*/ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc index de3163d..a83297a 100644 --- a/src/mainboard/amd/thatcher/Makefile.inc +++ b/src/mainboard/amd/thatcher/Makefile.inc @@ -19,12 +19,10 @@ romstage-y += buildOpts.c romstage-y += agesawrapper.c -romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c -ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index f6459c1..ccb8b58 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -51,16 +51,10 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 13.2 on end # USB device pci 14.0 on # SMBUS chip drivers/generic/generic #dimm 0 - device i2c 50 on end + device i2c 50 on end # 7-bit SPD address end chip drivers/generic/generic #dimm 1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device i2c 51 on end # 7-bit SPD address end end # SM device pci 14.1 on end # IDE 0x439c @@ -100,6 +94,12 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 18.4 on end device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #pci_domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/thatcher/dimmSpd.c b/src/mainboard/amd/thatcher/dimmSpd.c deleted file mode 100644 index 29d6a29..0000000 --- a/src/mainboard/amd/thatcher/dimmSpd.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" -#include "dimmSpd.h" - -#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) - -/*#pragma optimize ("", off) // for source level debug - *--------------------------------------------------------------------------- - * - * SPD address table - porting required - */ - -static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm -{ - // socket 0 - { - {0xA0, 0x00}, // channel 0 dimms - {0xA2, 0x00}, // channel 1 dimms - }, - // socket 1 - { - {0x00, 0x00}, // channel 0 dimms - {0x00, 0x00}, // channel 1 dimms - }, -}; - -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData (int iobase, int address, char *buffer, int offset) -{ - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 1, 0x1F); // clear error status - __outbyte (iobase + 3, offset); // offset in eeprom - __outbyte (iobase + 4, address); // slave address and read bit - __outbyte (iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*----------------------------------------------------------------------------- - * - * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - */ - -static int readSmbusByte (int iobase, int address, char *buffer) -{ - unsigned int status; - UINT64 limit; - - __outbyte (iobase + 0, 0xFF); // clear error status - __outbyte (iobase + 2, 0x44); // read command - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc () + 2000000000 / 10; - for (;;) - { - status = __inbyte (iobase); - if (__rdtsc () > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte (iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*--------------------------------------------------------------------------- - * - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ - -static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) -{ - int index, error; - - /* read the first byte using offset zero */ - error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); - if (error) return error; - - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { - error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); - if (error) return error; - } - - return 0; -} - -static void writePmReg (int reg, int data) -{ - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); -} - -static void setupFch (int ioBase) -{ - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - //writePmReg (0x29, 0x80); - //writePmReg (0x28, 0x61); - __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz -} - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) -{ - int spdAddress, ioBase; - - if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; - if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; - - spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) return AGESA_ERROR; - ioBase = 0xB00; - setupFch (ioBase); - return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); -} diff --git a/src/mainboard/amd/thatcher/dimmSpd.h b/src/mainboard/amd/thatcher/dimmSpd.h deleted file mode 100644 index c19cecc..0000000 --- a/src/mainboard/amd/thatcher/dimmSpd.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#ifndef _DIMMSPD_H_ -#define _DIMMSPD_H_ - -#include "Porting.h" -#include "AGESA.h" - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -AGESA_STATUS -AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData); - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ - -#endif diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index b0cf7ff..5bc7f6c 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -18,7 +18,8 @@ # romstage-y += fam15tn_callouts.c +romstage-y += dimmSpd.c ramstage-y += northbridge.c ramstage-y += fam15tn_callouts.c - +ramstage-y += dimmSpd.c diff --git a/src/northbridge/amd/agesa/family15tn/chip.h b/src/northbridge/amd/agesa/family15tn/chip.h new file mode 100644 index 0000000..013d648 --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/chip.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AGESA_FAM15TN_CHIP_H_ +#define _AGESA_FAM15TN_CHIP_H_ + +struct northbridge_amd_agesa_family15tn_config +{ + u8 spdAddrLookup[2][2][4]; +}; + +#endif diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c new file mode 100644 index 0000000..8b62a39 --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_def.h> +#include <device/device.h> + +/* warning: Porting.h includes an open #pragma pack(1) */ +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include "dimmSpd.h" +#include "chip.h" + + +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/*----------------------------------------------------------------------------- + * + * readSmbusByteData - read a single SPD byte from any offset + */ + +static int readSmbusByteData (int iobase, int address, char *buffer, int offset) +{ + unsigned int status; + UINT64 limit; + + address |= 1; // set read bit + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 1, 0x1F); // clear error status + __outbyte (iobase + 3, offset); // offset in eeprom + __outbyte (iobase + 4, address); // slave address and read bit + __outbyte (iobase + 2, 0x48); // read byte command + + // time limit to avoid hanging for unexpected error status (should never happen) + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} + +/*----------------------------------------------------------------------------- + * + * readSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + */ + +static int readSmbusByte (int iobase, int address, char *buffer) +{ + unsigned int status; + UINT64 limit; + + __outbyte (iobase + 0, 0xFF); // clear error status + __outbyte (iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = __inbyte (iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = __inbyte (iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} + +/*--------------------------------------------------------------------------- + * + * readspd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ + +static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) +{ + int index, error; + + /* read the first byte using offset zero */ + error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + if (error) return error; + + /* read the remaining bytes using auto-increment for speed */ + for (index = 1; index < count; index++) + { + error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]); + if (error) return error; + } + + return 0; +} + +static void writePmReg (int reg, int data) +{ + __outbyte (0xCD6, reg); + __outbyte (0xCD7, data); +} + +static void setupFch (int ioBase) +{ + writePmReg (0x2D, ioBase >> 8); + writePmReg (0x2C, ioBase | 1); + __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz +} + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) +{ + int spdAddress, ioBase; + ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + ROMSTAGE_CONST struct northbridge_amd_agesa_family15tn_config *config = dev->chip_info; + + if ((dev == 0) || (config == 0)) + return AGESA_ERROR; + + if (info->SocketId >= DIMENSION(config->spdAddrLookup )) + return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) + return AGESA_ERROR; + if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) + return AGESA_ERROR; + + spdAddress = config->spdAddrLookup + [info->SocketId] [info->MemChannelId] [info->DimmId]; + + if (spdAddress == 0) return AGESA_ERROR; + ioBase = 0xB00; + setupFch (ioBase); + return readspd (ioBase, spdAddress, (void *) info->Buffer, 128); +} diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.h b/src/northbridge/amd/agesa/family15tn/dimmSpd.h new file mode 100644 index 0000000..116eeb0 --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#ifndef _DIMMSPD_H_ +#define _DIMMSPD_H_ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData); + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c index 7c3b0ac..35aae91 100644 --- a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c @@ -24,6 +24,7 @@ #include "heapManager.h" #include "FchPlatform.h" #include "cbfs.h" +#include "dimmSpd.h" #include "fam15tn_callouts.h" AGESA_STATUS fam15tn_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) @@ -403,3 +404,10 @@ AGESA_STATUS fam15tn_HookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *Con return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } +AGESA_STATUS fam15tn_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); + + return Status; +} diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h index 74c7bf3..eb80a63 100644 --- a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.h @@ -49,5 +49,6 @@ AGESA_STATUS fam15tn_HookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *Conf AGESA_STATUS fam15tn_HookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS fam15tn_DefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS fam15tn_HookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); +AGESA_STATUS fam15tn_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr); #endif /* CALLOUTS_AMD_AGESA_FAM15TN_H */

1 0

Patch set updated for coreboot: d9fbf8c Family 15tn: Update for string portability
by Mike Loptien 31 Jan '13

31 Jan '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2251 -gerrit commit d9fbf8c55e8f3688e44679da03027ca60cbb2293 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Wed Jan 30 16:00:43 2013 -0700 Family 15tn: Update for string portability Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: Ib8ab97666340a9481f3ab71f0f347382e964994f Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/northbridge/amd/agesa/family15tn/northbridge.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index eb63ead..b05a11c 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -544,7 +544,7 @@ static void domain_enable_resources(device_t dev) #endif /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam15 - domain_enable_resources: AmdInitMid.\n"); + printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); #if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type != 3) { printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); @@ -563,7 +563,7 @@ static void domain_enable_resources(device_t dev) printk(BIOS_DEBUG, "passed.\n"); #endif - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); + printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } #if CONFIG_HW_MEM_HOLE_SIZEK != 0

1 0

New patch to review for coreboot: 1fc7956 Family 15tn: Update for string protability
by Mike Loptien 31 Jan '13

31 Jan '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2251 -gerrit commit 1fc795678160a048ce724a7b9eb6745c3d3d26c7 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Wed Jan 30 16:00:43 2013 -0700 Family 15tn: Update for string protability Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: Ib8ab97666340a9481f3ab71f0f347382e964994f Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/northbridge/amd/agesa/family15tn/northbridge.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index eb63ead..b05a11c 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -544,7 +544,7 @@ static void domain_enable_resources(device_t dev) #endif /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam15 - domain_enable_resources: AmdInitMid.\n"); + printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); #if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type != 3) { printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); @@ -563,7 +563,7 @@ static void domain_enable_resources(device_t dev) printk(BIOS_DEBUG, "passed.\n"); #endif - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); + printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } #if CONFIG_HW_MEM_HOLE_SIZEK != 0

1 0

New patch to review for coreboot: 228fe81 Family 12: Update for string portability
by Mike Loptien 31 Jan '13

31 Jan '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2250 -gerrit commit 228fe811dfd8f5bc8c8ffe822392b44b6540e474 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Thu Jan 31 10:17:02 2013 -0700 Family 12: Update for string portability Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: I3368a831770df1b8449eb0c97ae4bb24f6678efd Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/northbridge/amd/agesa/family12/northbridge.c | 74 ++++++++++++------------ 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index c4b43c5..9c598e8 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -99,7 +99,7 @@ static void f1_write_config32(unsigned reg, u32 value) static u32 amdfam12_nodeid(device_t dev) { - printk(BIOS_DEBUG, "Fam12h - northbridge.c - amdfam12_nodeid\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } @@ -117,13 +117,13 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) { u32 val; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - set_vga_enable_reg - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); val = 1 | (nodeid<<4) | (linkn<<12); /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, 0x3c0:0x3df */ f1_write_config32(0xf4, val); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - set_vga_enable_reg - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -133,7 +133,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, struct resource *res; unsigned nodeid, link = 0; int result; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - reg_useable - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { device_t dev; @@ -153,7 +153,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, result = 1; } } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - reg_useable - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); return result; } @@ -221,7 +221,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) { struct resource *resource; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - amdfam12_link_read_bases - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); /* Initialize the io space constraints on the current bus */ resource = amdfam12_find_iopair(dev, nodeid, link); if (resource) { @@ -275,7 +275,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) } #endif } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - amdfam12_link_read_bases - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) @@ -347,7 +347,7 @@ static void read_resources(device_t dev) u32 nodeid; struct bus *link; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - read_resources - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); nodeid = amdfam12_nodeid(dev); for(link = dev->link_list; link; link = link->next) { @@ -355,7 +355,7 @@ static void read_resources(device_t dev) amdfam12_link_read_bases(dev, nodeid, link->link_num); } } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - read_resources - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -366,7 +366,7 @@ static void set_resource(device_t dev, struct resource *resource, unsigned reg, link_num; char buf[50]; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - set_resource - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); /* Make certain the resource has actually been set */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { @@ -406,7 +406,7 @@ static void set_resource(device_t dev, struct resource *resource, sprintf(buf, " <node %x link %x>", nodeid, link_num); report_resource_stored(dev, resource, buf); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - set_resource - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -418,7 +418,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) { struct bus *link; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - create_vga_resource - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); /* find out which link the VGA card is connected, * we only deal with the 'first' vga card */ @@ -442,7 +442,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); set_vga_enable_reg(nodeid, link->link_num); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - create_vga_resource - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -452,7 +452,7 @@ static void set_resources(device_t dev) struct bus *bus; struct resource *res; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - set_resources - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); /* Find the nodeid */ nodeid = amdfam12_nodeid(dev); @@ -469,7 +469,7 @@ static void set_resources(device_t dev) assign_resources(bus); } } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - set_resources - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static void setup_uma_memory(void) @@ -506,7 +506,7 @@ static void domain_read_resources(device_t dev) { unsigned reg; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_read_resources - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); /* Find the already assigned resource pairs */ get_fx_devs(); @@ -576,14 +576,14 @@ static void domain_read_resources(device_t dev) resource->flags = IORESOURCE_MEM; } #endif - printk(BIOS_DEBUG, "Fam12h - northbridge.c - domain_read_resources - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static void domain_set_resources(device_t dev) { u32 val; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_set_resources - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08lx\n",dev); @@ -781,7 +781,7 @@ printk(BIOS_DEBUG, " adsr - high_tables_size = %x.\n",high_tables_size); } } printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - domain_set_resources - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -789,14 +789,14 @@ static void domain_enable_resources(device_t dev) { // u32 val; /* Must be called after PCI enumeration and resource allocation */ -// printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - agesawrapper_amdinitmid - Start.\n"); - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - domain_enable_resources - Start.\n"); +// printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - agesawrapper_amdinitmid - Start.\n",__func__); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); // val = agesawrapper_amdinitmid (); // if(val) { // printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); // } -// printk(BIOS_DEBUG, "Fam12h - northbridge.c - domain_enable_resources - agesawrapper_amdinitmid - End.\n"); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - domain_enable_resources - End.\n"); +// printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - agesawrapper_amdinitmid - End.\n",__func__); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -805,7 +805,7 @@ static void domain_enable_resources(device_t dev) static void cpu_bus_read_resources(device_t dev) { - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_read_resources - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -814,50 +814,50 @@ static void cpu_bus_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; #endif - printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_read_resources - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static void cpu_bus_set_resources(device_t dev) { struct resource *resource = find_resource(dev, 0xc0010058); - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_set_resources - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); if (resource) { report_resource_stored(dev, resource, " <mmconfig>"); } pci_dev_set_resources(dev); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_set_resources - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static void cpu_bus_init(device_t dev) { u32 val; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); initialize_cpus(dev->link_list); #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - sb_After_Pci_Init - Start.\n",__func__); sb_After_Pci_Init (); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_After_Pci_Init - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - sb_After_Pci_Init - End.\n",__func__); #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - sb_Mid_Post_Init - Start.\n",__func__); sb_Mid_Post_Init (); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - sb_Mid_Post_Init - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - sb_Mid_Post_Init - End.\n",__func__); #endif // #if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - cpu_bus_init - agesawrapper_amdinitmid - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - agesawrapper_amdinitmid - Start.\n",__func__); val = agesawrapper_amdinitmid (); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - agesawrapper_amdinitmid - End.\n"); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - cpu_bus_init - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - agesawrapper_amdinitmid - End.\n",__func__); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -909,7 +909,7 @@ static struct device_operations cpu_bus_ops = { static void root_complex_enable_dev(struct device *dev) { - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - root_complex_enable_dev - Start.\n"); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); static int done = 0; /* Do not delay UMA setup, as a device on the PCI bus may evaluate @@ -927,7 +927,7 @@ static void root_complex_enable_dev(struct device *dev) else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { dev->ops = &cpu_bus_ops; } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - root_complex_enable_dev - End.\n"); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); }

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New patch to review for coreboot: ef4cbd5 Family 10: Update for string portability
by Mike Loptien 31 Jan '13

31 Jan '13

Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2249 -gerrit commit ef4cbd50d51306153aeeea9d067c8e929828d94e Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Thu Jan 31 10:19:31 2013 -0700 Family 10: Update for string portability Update function messages to be more portable by using the __func__ compiler command instead of hard coded function names. Change-Id: Idf479980e427bbf0399bdbc15045d80f402f6dbe Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 4bdc7b4..c5d570a 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -833,12 +833,12 @@ static void amdfam10_domain_enable_resources(device_t dev) { u32 val; /* Must be called after PCI enumeration and resource allocation */ - printk(BIOS_DEBUG, "\nFam10 - domain_enable_resources: AmdInitMid.\n"); + printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); val = agesawrapper_amdinitmid(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); } - printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); + printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); }

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New patch to review for coreboot: 2e85cbc Add MMCONF resource to AMD fam15 PCI_DOMAIN
by Steven Sherk 31 Jan '13

31 Jan '13

Steven Sherk (steven.sherk(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2248 -gerrit commit 2e85cbc1e844b627840466f916db30cdb32532a3 Author: Steven Sherk <steven.sherk(a)se-eng.com> Date: Wed Jan 30 16:02:14 2013 -0700 Add MMCONF resource to AMD fam15 PCI_DOMAIN This is a port of the following: commit d5c998be99709c92f200b3b08aed2ca3fee2d519 The coreboot resource allocator doesn't respect resources claimed in the APIC_CLUSTER. Move the MMCONF resource to the PCI_DOMAIN to prevent overlap with PCI devices. original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I6e585d5cf0d46bd58337a6801fb0690ab2dd000c Signed-off-by: Steven Sherk <steven.sherk(a)se-eng.com> --- src/northbridge/amd/agesa/family15/northbridge.c | 32 +++++++++++++++--------- 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 2ab0e3e..6fb3105 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -341,6 +341,20 @@ static void nb_read_resources(device_t dev) amdfam15_link_read_bases(dev, nodeid, link->link_num); } } + + /* + * This MMCONF resource must be reserved in the PCI_DOMAIN. + * It is not honored by the coreboot resource allocator if it is in + * the APIC_CLUSTER. + */ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif + } @@ -448,6 +462,12 @@ static void nb_set_resources(device_t dev) assign_resources(bus); } } + + /* Print the MMCONF region if it has been reserved. */ + res = find_resource(dev, 0xc0010058); + if (res) { + report_resource_stored(dev, res, " <mmconfig>"); + } } static void northbridge_init(struct device *dev) @@ -1095,22 +1115,10 @@ static void cpu_bus_noop(device_t dev) static void cpu_bus_read_resources(device_t dev) { -#if CONFIG_MMCONF_SUPPORT - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif } static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } - pci_dev_set_resources(dev); } static struct device_operations cpu_bus_ops = {

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coreboot January 2013