coreboot December 2003

coreboot@coreboot.org

39 participants
66 discussions

Re: Tyan S2885
by YhLu 05 Dec '03

05 Dec '03

Eric, I change amdk8_scan_root_bus to: unsigned int amdk8_scan_root_bus(device_t root, unsigned int max) { unsigned reg; uint32_t value; /* Unmap all of the other pci busses */ printk_debug("\nbefore pci_scan_bus\n"); for(reg = 0xe0; reg <= 0xec; reg += 4) { value = f1_read_config32(reg); printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", reg,value,max); if((value>>24)… [View More]>max) f1_write_config32(reg, 0); } for(reg = 0xe0; reg <= 0xec; reg += 4) { value = f1_read_config32(reg); printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", reg,value,max); } max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max); printk_debug("after pci_scan_bus\n"); for(reg = 0xe0; reg <= 0xec; reg += 4) { value = f1_read_config32(reg); printk_debug("amdk8_scan_root_bus %0x = %0x max = %0x\n", reg,value,max); } return max; } I think as least you only need to clear the regs that contain bigger bus number than the next bus for scanning. The result will be in the end. The problems: 1. It can not access 8151 on CPU link0 and so can not scan it 2. The HT scan seems can not figure out and set the link and read/write enable bit in e0. It set the e0 to 0x05050000 Regards Yinghai Lu Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.52.0_Fallback Fri Dec 5 14:29:03 EST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating buses... before pci_scan_bus amdk8_scan_root_bus e0 = 4000203 max = 0 amdk8_scan_root_bus e4 = 6050003 max = 0 amdk8_scan_root_bus e8 = 0 max = 0 amdk8_scan_root_bus ec = 0 max = 0 amdk8_scan_root_bus e0 = 0 max = 0 amdk8_scan_root_bus e4 = 0 max = 0 amdk8_scan_root_bus e8 = 0 max = 0 amdk8_scan_root_bus ec = 0 max = 0 PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled amd8111_enable dev: PCI: 01:04.6 lpc_dev: PCI: 01:04.0 index: 6 reg: ffff -> ffbf done PCI: 01:04.6 [ffff/ffff] disabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled amd8111_enable dev: PCI: 04:01.0 lpc_dev: PCI: 01:04.0 index: 9 reg: ffbf -> fdbf done PCI: 04:01.0 [ffff/ffff] disabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 4 Hypertransport scan link done Hyper transport scan link: 0 max: 5 Missing static device: PCI: 05:00.0 HyperT reset not needed PCI: pci_scan_bus for bus 5 PCI: 05:00.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:00.0 No device operations PCI: 05:01.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 05:01.0 No device operations PCI: pci_scan_bus returning with max=05 Hyper transport scan link: 0 new max: 5 Hypertransport scan link done amdk8_scan_chains max: 5 done amdk8_scan_chains max: 5 starting... amdk8_scan_chains max: 5 done PCI: pci_scan_bus returning with max=05 after pci_scan_bus amdk8_scan_root_bus e0 = 5050000 max = 5 amdk8_scan_root_bus e4 = 0 max = 5 amdk8_scan_root_bus e8 = 0 max = 5 amdk8_scan_root_bus ec = 0 max = 5 done Allocating resources... PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 01:04.6 missing read_resources PCI: 01:04.6 missing read_resources ASSIGN RESOURCES, bus 0 PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 00:18.0 c8 <- [0x00003000 - 0x00002fff] node 0 link 0 io PCI: 05:00.0 missing read_resources PCI: 05:01.0 missing read_resources PCI: 00:18.0 80 <- [0xfec00000 - 0xfebfffff] node 0 link 0 mem PCI: 01:04.6 missing read_resources PCI: 00:18.0 c0 <- [0x00001000 - 0x00002fff] node 0 link 2 io PCI: 01:04.6 missing read_resources PCI: 00:18.0 b8 <- [0xfe900000 - 0xfebfffff] node 0 link 2 mem ASSIGN RESOURCES, bus 5 PCI: 05:00.0 missing set_resources PCI: 05:01.0 missing set_resources ASSIGNED RESOURCES, bus 5 ASSIGN RESOURCES, bus 1 PCI: 01:01.0 1c <- [0x00002000 - 0x00001fff] bus 2 io PCI: 01:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 2 prefmem PCI: 01:01.0 20 <- [0xfe900000 - 0xfe9fffff] bus 2 mem ASSIGN RESOURCES, bus 2 PCI: 02:09.0 10 <- [0xfe900000 - 0xfe90ffff] mem ASSIGNED RESOURCES, bus 2 PCI: 01:01.1 10 <- [0xfeb00000 - 0xfeb00fff] mem PCI: 01:02.0 1c <- [0x00002000 - 0x00001fff] bus 3 io PCI: 01:02.0 24 <- [0xfeb00000 - 0xfeafffff] bus 3 prefmem PCI: 01:02.0 20 <- [0xfeb00000 - 0xfeafffff] bus 3 mem PCI: 01:02.1 10 <- [0xfeb01000 - 0xfeb01fff] mem PCI: 04:01.0 missing read_resources PCI: 01:03.0 1c <- [0x00001000 - 0x00001fff] bus 4 io PCI: 04:01.0 missing read_resources PCI: 01:03.0 24 <- [0xfeb00000 - 0xfeafffff] bus 4 prefmem PCI: 04:01.0 missing read_resources PCI: 01:03.0 20 <- [0xfea00000 - 0xfeafffff] bus 4 mem ASSIGN RESOURCES, bus 4 PCI: 04:00.0 10 <- [0xfea04000 - 0xfea04fff] mem PCI: 04:00.1 10 <- [0xfea05000 - 0xfea05fff] mem PCI: 04:00.2 10 <- [0xfea08000 - 0xfea080ff] mem PCI: 04:00.2 14 <- [0xfea09000 - 0xfea0901f] mem PCI: 04:01.0 missing set_resources PCI: 04:0b.0 10 <- [0x00001010 - 0x00001017] io PCI: 04:0b.0 14 <- [0x00001030 - 0x00001033] io PCI: 04:0b.0 18 <- [0x00001020 - 0x00001027] io PCI: 04:0b.0 1c <- [0x00001040 - 0x00001043] io PCI: 04:0b.0 20 <- [0x00001000 - 0x0000100f] io PCI: 04:0b.0 24 <- [0xfea07000 - 0xfea073ff] mem PCI: 04:0c.0 10 <- [0xfea06000 - 0xfea067ff] mem PCI: 04:0c.0 14 <- [0xfea00000 - 0xfea03fff] mem ASSIGNED RESOURCES, bus 4 PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] io PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] mem PCI: 01:04.1 20 <- [0x00002460 - 0x0000246f] io PCI: 01:04.2 10 <- [0x00002440 - 0x0000245f] io PCI: 01:04.5 10 <- [0x00002000 - 0x000020ff] io PCI: 01:04.5 14 <- [0x00002400 - 0x0000243f] io PCI: 01:04.6 missing set_resources ASSIGNED RESOURCES, bus 1 ASSIGNED RESOURCES, bus 0 done. Enabling resourcess... PCI: 00:18.0 cmd <- 00 PCI: 05:00.0 missing enable_resources PCI: 05:01.0 missing enable_resources PCI: 01:01.0 bridge ctrl <- 0000 PCI: 01:01.0 cmd <- 07 PCI: 02:09.0 cmd <- 02 PCI: 01:01.1 cmd <- 06 PCI: 01:02.0 bridge ctrl <- 0000 PCI: 01:02.0 cmd <- 07 PCI: 01:02.1 cmd <- 06 PCI: 01:03.0 bridge ctrl <- 0000 PCI: 01:03.0 cmd <- 07 PCI: 04:00.0 cmd <- 02 PCI: 04:00.1 cmd <- 02 PCI: 04:00.2 cmd <- 02 PCI: 04:01.0 missing enable_resources PCI: 04:0b.0 cmd <- 03 PCI: 04:0c.0 cmd <- 02 PCI: 01:04.0 cmd <- 0f PCI: 01:04.1 cmd <- 01 PCI: 01:04.2 cmd <- 01 PCI: 01:04.3 cmd <- 00 PCI: 01:04.5 cmd <- 01 PCI: 01:04.6 missing enable_resources PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 done. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.3 init NB: Function 3 Misc Control.. resetting cpu [View Less]

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Re: Tyan S2885
by YhLu 05 Dec '03

05 Dec '03

Eric, If don't clear the regs, the result will be: Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.52.0_Fallback Fri Dec 5 15:05:21 EST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating buses... before pci_scan_bus amdk8_scan_root_bus e0 = 4000203 max = 0 amdk8_scan_root_bus e4 = 6050003 max = 0 … [View More]amdk8_scan_root_bus e8 = 0 max = 0 amdk8_scan_root_bus ec = 0 max = 0 PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 2 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset needed PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] enabled amd8111_enable dev: PCI: 01:04.6 lpc_dev: PCI: 01:04.0 index: 6 reg: ffff -> ffbf done PCI: 01:04.6 [ffff/ffff] disabled PCI: pci_scan_bus for bus 2 PCI: 02:09.0 [14e4/16a7] ops PCI: 02:09.0 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled amd8111_enable dev: PCI: 04:01.0 lpc_dev: PCI: 01:04.0 index: 9 reg: ffbf -> fdbf done PCI: 04:01.0 [ffff/ffff] disabled PCI: 04:0b.0 [1095/3114] ops PCI: 04:0b.0 [1095/3114] enabled PCI: 04:0c.0 [104c/8023] ops PCI: 04:0c.0 [104c/8023] enabled PCI: pci_scan_bus returning with max=04 PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 2 new max: 4 Hypertransport scan link done Hyper transport scan link: 0 max: 5 PCI: 05:01.0 [1022/7454] enabled next_unitid: 0004 HyperT reset needed PCI: pci_scan_bus for bus 5 PCI: 05:01.0 [1022/7454] ops PCI: 05:01.0 [1022/7454] enabled PCI: 05:02.0 [1022/7455] bus ops PCI: 05:02.0 [1022/7455] enabled PCI: pci_scan_bus for bus 6 PCI: 06:00.0 [10de/0322] enabled PCI: pci_scan_bus returning with max=06 PCI: pci_scan_bus returning with max=06 Hyper transport scan link: 0 new max: 6 Hypertransport scan link done amdk8_scan_chains max: 6 done amdk8_scan_chains max: 6 starting... amdk8_scan_chains max: 6 done PCI: pci_scan_bus returning with max=06 after pci_scan_bus amdk8_scan_root_bus e0 = 4010203 max = 6 amdk8_scan_root_bus e4 = 6050003 max = 6 amdk8_scan_root_bus e8 = 0 max = 6 amdk8_scan_root_bus ec = 0 max = 6 done Allocating resources... PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 04:01.0 missing read_resources PCI: 01:04.6 missing read_resources PCI: 01:04.6 missing read_resources ASSIGN RESOURCES, bus 0 PCI: 00:18.0 c8 <- [0x00003000 - 0x00002fff] node 0 link 0 io PCI: 00:18.0 80 <- [0xe0000000 - 0xf8ffffff] node 0 link 0 mem PCI: 01:04.6 missing read_resources PCI: 00:18.0 c0 <- [0x00001000 - 0x00002fff] node 0 link 2 io PCI: 01:04.6 missing read_resources PCI: 00:18.0 b8 <- [0xf9000000 - 0xf92fffff] node 0 link 2 mem ASSIGN RESOURCES, bus 5 PCI: 05:01.0 10 <- [0xe0000000 - 0xefffffff] prefmem PCI: 05:02.0 1c <- [0x00003000 - 0x00002fff] bus 6 io PCI: 05:02.0 24 <- [0xf0000000 - 0xf7ffffff] bus 6 prefmem PCI: 05:02.0 20 <- [0xf8000000 - 0xf8ffffff] bus 6 mem ASSIGN RESOURCES, bus 6 PCI: 06:00.0 10 <- [0xf8000000 - 0xf8ffffff] mem PCI: 06:00.0 14 <- [0xf0000000 - 0xf7ffffff] prefmem ASSIGNED RESOURCES, bus 6 ASSIGNED RESOURCES, bus 5 ASSIGN RESOURCES, bus 1 PCI: 01:01.0 1c <- [0x00002000 - 0x00001fff] bus 2 io PCI: 01:01.0 24 <- [0xf9200000 - 0xf91fffff] bus 2 prefmem PCI: 01:01.0 20 <- [0xf9000000 - 0xf90fffff] bus 2 mem ASSIGN RESOURCES, bus 2 PCI: 02:09.0 10 <- [0xf9000000 - 0xf900ffff] mem ASSIGNED RESOURCES, bus 2 PCI: 01:01.1 10 <- [0xf9200000 - 0xf9200fff] mem PCI: 01:02.0 1c <- [0x00002000 - 0x00001fff] bus 3 io PCI: 01:02.0 24 <- [0xf9200000 - 0xf91fffff] bus 3 prefmem PCI: 01:02.0 20 <- [0xf9200000 - 0xf91fffff] bus 3 mem PCI: 01:02.1 10 <- [0xf9201000 - 0xf9201fff] mem PCI: 04:01.0 missing read_resources PCI: 01:03.0 1c <- [0x00001000 - 0x00001fff] bus 4 io PCI: 04:01.0 missing read_resources PCI: 01:03.0 24 <- [0xf9200000 - 0xf91fffff] bus 4 prefmem PCI: 04:01.0 missing read_resources PCI: 01:03.0 20 <- [0xf9100000 - 0xf91fffff] bus 4 mem ASSIGN RESOURCES, bus 4 PCI: 04:00.0 10 <- [0xf9104000 - 0xf9104fff] mem PCI: 04:00.1 10 <- [0xf9105000 - 0xf9105fff] mem PCI: 04:00.2 10 <- [0xf9108000 - 0xf91080ff] mem PCI: 04:00.2 14 <- [0xf9109000 - 0xf910901f] mem PCI: 04:01.0 missing set_resources PCI: 04:0b.0 10 <- [0x00001010 - 0x00001017] io PCI: 04:0b.0 14 <- [0x00001030 - 0x00001033] io PCI: 04:0b.0 18 <- [0x00001020 - 0x00001027] io PCI: 04:0b.0 1c <- [0x00001040 - 0x00001043] io PCI: 04:0b.0 20 <- [0x00001000 - 0x0000100f] io PCI: 04:0b.0 24 <- [0xf9107000 - 0xf91073ff] mem PCI: 04:0c.0 10 <- [0xf9106000 - 0xf91067ff] mem PCI: 04:0c.0 14 <- [0xf9100000 - 0xf9103fff] mem ASSIGNED RESOURCES, bus 4 PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] io PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] mem PCI: 01:04.1 20 <- [0x00002460 - 0x0000246f] io PCI: 01:04.2 10 <- [0x00002440 - 0x0000245f] io PCI: 01:04.5 10 <- [0x00002000 - 0x000020ff] io PCI: 01:04.5 14 <- [0x00002400 - 0x0000243f] io PCI: 01:04.6 missing set_resources ASSIGNED RESOURCES, bus 1 ASSIGNED RESOURCES, bus 0 Allocating VGA resource done. Enabling resourcess... PCI: 00:18.0 cmd <- 00 PCI: 05:01.0 cmd <- 06 PCI: 05:02.0 bridge ctrl <- 003e PCI: 05:02.0 cmd <- 07 PCI: 06:00.0 cmd <- 03 PCI: 01:01.0 bridge ctrl <- 0000 PCI: 01:01.0 cmd <- 07 PCI: 02:09.0 cmd <- 02 PCI: 01:01.1 cmd <- 06 PCI: 01:02.0 bridge ctrl <- 0000 PCI: 01:02.0 cmd <- 07 PCI: 01:02.1 cmd <- 06 PCI: 01:03.0 bridge ctrl <- 0000 PCI: 01:03.0 cmd <- 07 PCI: 04:00.0 cmd <- 02 PCI: 04:00.1 cmd <- 02 PCI: 04:00.2 cmd <- 02 PCI: 04:01.0 missing enable_resources PCI: 04:0b.0 cmd <- 03 PCI: 04:0c.0 cmd <- 02 PCI: 01:04.0 cmd <- 0f PCI: 01:04.1 cmd <- 01 PCI: 01:04.2 cmd <- 01 PCI: 01:04.3 cmd <- 00 PCI: 01:04.5 cmd <- 01 PCI: 01:04.6 missing enable_resources PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 done. Initializing devices... PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.3 init NB: Function 3 Misc Control.. resetting cpu [View Less]

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Update to pirq_routing
by Jordan Archer 05 Dec '03

05 Dec '03

The following is the diff for a change I made. I think the HAVE_PIRQ_TABLE is always defined and this allowed me to turn off the existence of a routing table. Jordan RCS file: /cvsroot/freebios/freebios2/src/arch/i386/include/arch/pirq_routing.h,v retrieving revision 1.1 diff -r1.1 pirq_routing.h 42c42,43 < #if defined(DEBUG) && defined(HAVE_PIRQ_TABLE) --- > //#if defined(DEBUG) && defined(HAVE_PIRQ_TABLE) > #if defined(DEBUG) && HAVE_PIRQ_TABLE … [View More]

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Re: Tyan S4880
by YhLu 05 Dec '03

05 Dec '03

Ron, Please check in the Tyan s2850/2880/2881/2882/4880 updates into the CVS Tree. 1. northbridge/amd/amdk8/raminit.h: change uint8_t to uint16_t 2. southbridge/amd/amd8111/amd8111_early_smbus.c: update smbus_write_byte 3. southbridge/amd/amd8131/amd8131_bridge.c: update ioapic_anable to enable PCI-X MASTER Mode. 4. other in /src/mainboard/tyan/ and /targets/tyan Stefan, With update 1 and 2, you can get ride of FAKE_SPD_ROM. You need to change some lines in auto.c for quartet. 1. I2C HUB … [View More]

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Re: Tyan S2885
by YhLu 05 Dec '03

05 Dec '03

I will try the code and use normal scan. YH. -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2003年12月4日 21:36 收件人: YhLu 抄送: ron minnich; Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: Tyan S2885 YhLu <YhLu(a)tyan.com> writes: > Eric, > > I found in amdk8_scan_root_bus in northbridge/amd/amdk8/northbridge.c > You put > /* Unmap all of the other pci busses */ > for(reg = 0xe0; reg <= 0xec; reg += 4) { > … [View More]

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arima hdama success
by Craig C Forney 05 Dec '03

05 Dec '03

On Wed, 3 Dec 2003, Ron Minnich wrote > as of this morning, with Yh Lu's changes, arima hdama builds work fine. > >ron I'm not having the same success. I got the latest snapshot this evening, built for the arima hdama, and it fails the same way it has failed (hangs after printing out stuff below) for the last couple of months. Have Yh Lu's changes that fix the arima hdama been committed? If not, could someone point me to the changes that fix whatever this problem is? Thanks, … [View More]Craig Forney Opus Innovations LLC LinuxBIOS-1.1.5.0Fallback Thu Dec 4 23:13:33 PST 2003 starting... setting up resource map.... AMD8111 southbridge is connected to HT link 00000000 setting up resource map.... done. Enabling routing table for node 00000000 done. Enabling SMP settings setup_remote_node setup_remote_done Renaming current temp node to 00000001 done. Enabling routing table for node 00000001 done. 00000002 nodes initialized. detect_mp_capabilities: 00000002 coherent_ht_finalize done SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram1.01 setting up CPU01 northbridge registers done. Ram2.00 166Mhz Interleaved RAM: 0x00100000 KB Ram2.01 Enabling dual channel memory disabling dimm00 disabling dimm01 disabling dimm00 disabling dimm01 200Mhz disabling dimm00 disabling dimm01 RAM: 0x00100000 KB Ram3 ECC enabled ECC enabled Initializing memory: done Clearing memory: addr 00000000-0000003f ----------------done Initializing memory: done Clearing memory: addr 00000040-0000003f done Ram4 PCI: 00:01.00 00: 22 10 50 74 00 00 30 02 12 00 04 06 00 00 81 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f1 01 20 02 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: ff ff 00 00 a0 00 00 00 00 00 00 00 ff 00 00 00 40: 07 00 1f 00 00 00 00 00 02 0c 00 00 00 2c 00 00 50: 00 00 02 00 00 00 04 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 03 00 08 00 03 00 0e 00 ff ff 02 00 ff ff b0: 00 00 00 00 00 00 00 00 08 c0 00 80 00 00 00 00 c0: 08 00 41 00 20 00 11 00 20 00 00 00 22 00 35 00 d0: 02 00 35 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 08 0c 00 08 08 0d 00 0f 0f 13 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:01.01 00: 22 10 51 74 00 00 00 02 01 10 00 08 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 ... PCI info deleted for brevity ... 80: 33 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 80 0a 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: a3 88 1e 5a 02 00 00 00 8c 5b b7 d6 72 9f e7 ef c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 04 67 05 44 e4 ae 6b 16 9e 4f 10 40 c5 1b cc 44 e0: d9 c6 0a 24 48 04 5c 10 38 6c 03 48 86 74 2e 26 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:18.03 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 40 00 be fc 07 77 73 80 7b 46 50: 08 a5 f7 0b 88 00 00 00 16 16 16 00 00 04 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 02 00 00 00 70 0f 00 00 00 83 06 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 01 00 00 e0 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 20 10 00 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.5.0Fallback Thu Dec 4 23:13:33 PST 2003 booting... Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating: NSC 87360 Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [ffff/ffff] enabled PCI: 00:19.1 [ffff/ffff/00ffff] has unknown header type ff, ignoring. PCI: 00:19.1 No device operations [View Less]

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Tyan S2885
by YhLu 05 Dec '03

05 Dec '03

Eric, I found in amdk8_scan_root_bus in northbridge/amd/amdk8/northbridge.c You put /* Unmap all of the other pci busses */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } Why you need to clear that? After you clear that, I can not see the 8151 and AGP in s2885. PS: I have reversed the scan sequence to make sure HT scan 8111 at first and then 8151. Regards Yinghai Lu

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Level 2 cache activation code?
by Svante Signell 04 Dec '03

04 Dec '03

Hello, I have recently upgraded my dual MSI-6120 from 2xCeleron (Mendocino) 300@450MHz with 2xMSI-6905 slot 370 to slot 1 adapters to one Celeron2 1.3GHz (Tualatin) using a Slot-T adapter card. The plan is to equip the mobo with 2xPIII or preferably 2xVIA C3 Nehemiah (when SMP capable). The problem is that the latest MSI BIOS (v2.0) for the mobo does not support Coppermine/Tualatin processors. The single GNU/Linux kernels boot without problems but _extremely_ slowly, at least with a speed … [View More]

6 27

Doubt with Diskonchip millennium?
by Devi Priya 04 Dec '03

04 Dec '03

Hi, In the application note (AP044) from Msystems diskonchip it is given as: "The DiskOnChip Millennium is mapped into an 8KB memory window in the host platforms memory map. This 8KB window consists of four 2KB windows." Why is this mapping done? Is this done for all the DiskOnChip Millennium? The steps for BIOS is summarised as 1. After DiskOnChip Millennium BUSY# signal is negated, the CPU fetches the Reset Vector from the Boot-Block area, fetches the Boot Code stored there, and … [View More]

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Re: Diskonchip ipl code for sc1200?
by Devi Priya 03 Dec '03

03 Dec '03

Hi, Thanks for ur suggestion. Should I write both ipl code for the chipset and the DOCM? Should I also write the SPL code for chipset and DOCM? Can I use the ipl and spl code given with the xpressloader BootLoader Development Kit? >From: ron minnich <rminnich(a)lanl.gov> >To: Devi Priya <ijpriya(a)hotmail.com> >CC: linuxbios(a)clustermatic.org >Subject: Re: Diskonchip ipl code for sc1200? >Date: Wed, 3 Dec 2003 07:34:03 -0700 (MST) > >On Wed, 3 Dec … [View More]

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coreboot December 2003