The following is the diff for a change I made. I think the HAVE_PIRQ_TABLE
is always defined and this allowed me to turn off the existence of a
routing table.
Jordan
RCS file:
/cvsroot/freebios/freebios2/src/arch/i386/include/arch/pirq_routing.h,v
retrieving revision 1.1
diff -r1.1 pirq_routing.h
42c42,43
< #if defined(DEBUG) && defined(HAVE_PIRQ_TABLE)
---
> //#if defined(DEBUG) && defined(HAVE_PIRQ_TABLE)
> #if defined(DEBUG) && HAVE_PIRQ_TABLE // JORDAN: This needs to
be dependent on value, not existence.
48c49,50
< #if defined(HAVE_PIRQ_TABLE)
---
> //#if defined(HAVE_PIRQ_TABLE)
> #if HAVE_PIRQ_TABLE // JORDAN: This needs to be dependent on
value, not
Index: romcc_io.h
===================================================================
Ron,
Please check in the Tyan s2850/2880/2881/2882/4880 updates into the CVS
Tree.
1. northbridge/amd/amdk8/raminit.h: change uint8_t to uint16_t
2. southbridge/amd/amd8111/amd8111_early_smbus.c: update smbus_write_byte
3. southbridge/amd/amd8131/amd8131_bridge.c: update ioapic_anable to enable
PCI-X MASTER Mode.
4. other in /src/mainboard/tyan/ and /targets/tyan
Stefan,
With update 1 and 2, you can get ride of FAKE_SPD_ROM. You need to change
some lines in auto.c for quartet. 1. I2C HUB address: 0x30 --> 0x18, 2.
RC0-> (1<<1)<<8, RC1-> (1<<2)<<8, RC2-> (1<<3)<<8, RC3-> (1<<4)<<8.
Regards
YH.
I will try the code and use normal scan.
YH.
-----邮件原件-----
发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com]
发送时间: 2003年12月4日 21:36
收件人: YhLu
抄送: ron minnich; Stefan Reinauer; linuxbios(a)clustermatic.org
主题: Re: Tyan S2885
YhLu <YhLu(a)tyan.com> writes:
> Eric,
>
> I found in amdk8_scan_root_bus in northbridge/amd/amdk8/northbridge.c
> You put
> /* Unmap all of the other pci busses */
> for(reg = 0xe0; reg <= 0xec; reg += 4) {
> f1_write_config32(reg, 0);
> }
>
> Why you need to clear that? After you clear that, I can not see the 8151
and
> AGP in s2885.
Hmm. This looks like a thinko.
So right now the code says:
unsigned int amdk8_scan_root_bus(device_t root, unsigned int max)
{
unsigned reg;
max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
/* Unmap all of the other pci busses */
for(reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
return max;
}
And I think what I meant was:
unsigned int amdk8_scan_root_bus(device_t root, unsigned int max)
{
unsigned reg;
/* Unmap all of the other pci busses */
for(reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
max = pci_scan_bus(&root->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
return max;
}
I don't have a clue why it works at all with clearing those registers after
the pci bus scan.
I wonder if that is the reason scan order matters because I don't
clear those registers out first and things are dual mapped.
Anyway my intention was to be very careful and to clear the HT chain
mapping registers before we scanned them so we didn't have any old
configurations getting in the way.
Eric
Eric,
I found in amdk8_scan_root_bus in northbridge/amd/amdk8/northbridge.c
You put
/* Unmap all of the other pci busses */
for(reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
Why you need to clear that? After you clear that, I can not see the 8151 and
AGP in s2885.
PS:
I have reversed the scan sequence to make sure HT scan 8111 at first and
then 8151.
Regards
Yinghai Lu
Hello,
I have recently upgraded my dual MSI-6120 from 2xCeleron (Mendocino)
300@450MHz with 2xMSI-6905 slot 370 to slot 1 adapters to one Celeron2
1.3GHz (Tualatin) using a Slot-T adapter card. The plan is to equip the
mobo with 2xPIII or preferably 2xVIA C3 Nehemiah (when SMP capable).
The problem is that the latest MSI BIOS (v2.0) for the mobo does not
support Coppermine/Tualatin processors. The single GNU/Linux kernels
boot without problems but _extremely_ slowly, at least with a speed
reduction by a factor 10. hdparm -tT gives around 20/2 compared with
250/25 with the Mendocino CPU(s). For example uncompressing the kernel
takes minute(s) compared to seconds. After some trials and web searching
I suspect that the problem is with the level 2 cache not activated by
the BIOS.
I see the you have code in the linuxbios for activating caches.
i) Does this code work for 440BX motherboards?
ii) Is it possible to extract this code and try out after the kernel has
booted (slowly), to verify my assumption?
iii) Is there some other tool available for cache activation?
iv) One interesting continuation would be to try to replace the MSI
(AMI) BIOS with linuxbios, but as a first step I think this would be a
little risky.
Any ideas?
Thanks,
Svante
Hi,
In the application note (AP044) from Msystems diskonchip it is given
as:
"The DiskOnChip Millennium is mapped into an 8KB memory window in the host
platforms
memory map. This 8KB window consists of four 2KB windows." Why is this
mapping done?
Is this done for all the DiskOnChip Millennium?
The steps for BIOS is summarised as
1. After DiskOnChip Millennium BUSY# signal is negated, the CPU fetches the
Reset Vector from
the Boot-Block area, fetches the Boot Code stored there, and starts to
execute the code.
2. Boot Code runs the first part of BIOS, initializing the basic hardware
functionality.
3. Boot Codes loads the rest of the BIOS from the flash memory to the DRAM,
and transfer control
(jumps) there.
4. Chip Select of DiskOnChip Millennium is remapped from Reset Vector to
BIOS expansion area.
5. CPU executes the rest of the BIOS code, including ROM expansion devices
(among them, the
DiskOnChip Millennium itself).
6. CPU calls OS bootstrap loader (INT19).
7. OS is loaded, and recognizes the DiskOnChip Millennium as the boot
device.
8. OS loads the application code from the DiskOnChip Millennium and executes
it.
9. Application software uses DiskOnChip Millennium exactly as if it were
using a regular hard disk.
In step 4 why is this remapping done
_________________________________________________________________
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MSN Shopping. No waiting for a clerk to help you! http://shopping.msn.com
Hi,
Thanks for ur suggestion. Should I write both ipl code for the chipset
and the DOCM? Should I also write the SPL code for chipset and DOCM? Can I
use the ipl and spl code given with the xpressloader BootLoader Development
Kit?
>From: ron minnich <rminnich(a)lanl.gov>
>To: Devi Priya <ijpriya(a)hotmail.com>
>CC: linuxbios(a)clustermatic.org
>Subject: Re: Diskonchip ipl code for sc1200?
>Date: Wed, 3 Dec 2003 07:34:03 -0700 (MST)
>
>On Wed, 3 Dec 2003, Devi Priya wrote:
>
> > I could not find any ipl code for sc1200 (nano mainboard). Which
>should I
> > mention in the config file for docipl? Please give me suggestion.
>
>you'll have to write it.
>
>ron
>
>_______________________________________________
>Linuxbios mailing list
>Linuxbios(a)clustermatic.org
>http://www.clustermatic.org/mailman/listinfo/linuxbios
_________________________________________________________________
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