coreboot May 2012

coreboot@coreboot.org

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287 discussions

Patch set updated for coreboot: 3a99e2c Provide functions to access arbitrary GPIO pins and vectors
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1049 -gerrit commit 3a99e2cd0443e017d6978930db98ad579af5a93f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 15 14:18:59 2012 -0700 Provide functions to access arbitrary GPIO pins and vectors This change adds utility functions which allow to read any GPIO pin, as well as a vector of GPIO pin values. As presented, these functions will be available to Sandy Bridge and Ivy Bridge systems only. There is no error checking: trying to read GPIO pin number which exceeds actual number of pins will return zero, trying to read GPIO which is not actually configured as such will return unpredictable value. When reading a GPIO pin vector, the pin numbers are passed in an array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass pointer to array of {4, 2, 15, -1}. Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/southbridge/intel/bd82x6x/gpio.c | 37 ++++++++++++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/gpio.h | 8 +++++++ 2 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c index 598726a..2ba34ea 100644 --- a/src/southbridge/intel/bd82x6x/gpio.c +++ b/src/southbridge/intel/bd82x6x/gpio.c @@ -25,6 +25,8 @@ #include "pch.h" #include "gpio.h" +#define MAX_GPIO_NUMBER 75 /* zero based */ + void setup_pch_gpios(const struct pch_gpio_map *gpio) { u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; @@ -63,3 +65,38 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) if (gpio->set3.reset) outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3); } + +int get_gpio(int gpio_num) +{ + static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48}; + u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + int index, bit; + + if (gpio_num > MAX_GPIO_NUMBER) + return 0; /* Just ignore wrong gpio numbers. */ + + index = gpio_num / 32; + bit = gpio_num % 32; + + return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1; +} + +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array) +{ + int gpio; + unsigned bitmask = 1; + unsigned vector = 0; + + while (bitmask && + ((gpio = *gpio_num_array++) != -1)) { + vector <<= 1; + if (get_gpio(gpio)) + vector |= bitmask; + bitmask <<= 1; + } + return vector; +} diff --git a/src/southbridge/intel/bd82x6x/gpio.h b/src/southbridge/intel/bd82x6x/gpio.h index 214947f..44e808a 100644 --- a/src/southbridge/intel/bd82x6x/gpio.h +++ b/src/southbridge/intel/bd82x6x/gpio.h @@ -150,4 +150,12 @@ struct pch_gpio_map { /* Configure GPIOs with mainboard provided settings */ void setup_pch_gpios(const struct pch_gpio_map *gpio); +/* get GPIO pin value */ +int get_gpio(int gpio_num); +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array); + #endif

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Patch set updated for coreboot: a9f436f Drop config variable CPU_MODEL_INDEX
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1047 -gerrit commit a9f436fa6f13d46f9d4a2b9f4f849a3f828ab5cd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 11 16:30:54 2012 -0700 Drop config variable CPU_MODEL_INDEX It's only used in the ACPI generator for Sandybridge/Ivybridge CPUs and the code can easily be changed to not rely on any Kconfig magic. Change-Id: Ie2f92edfe8908f7eb2fda3088f77ad22f491ddcf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/model_206ax/Kconfig | 8 -------- src/cpu/intel/model_206ax/acpi.c | 11 ++--------- 2 files changed, 2 insertions(+), 17 deletions(-) diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index c11f21a..d2d4c73 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -36,18 +36,10 @@ if CPU_INTEL_MODEL_206AX config CPU_MODEL_NAME string default "Intel SandyBridge CPU" - - config CPU_MODEL_INDEX - hex - default 0x2a endif if CPU_INTEL_MODEL_306AX config CPU_MODEL_NAME string default "Intel IvyBridge CPU" - - config CPU_MODEL_INDEX - hex - default 0x3a endif diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 1a8ceb7..6153174 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -44,15 +44,8 @@ static int get_cores_per_package(void) if (c.x86 != 6) return 1; - switch (c.x86_model) { - case CONFIG_CPU_MODEL_INDEX: - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - break; - default: - cores = (cpuid_ebx(1) >> 16) & 0xff; - break; - } + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; return cores; }

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Patch set updated for coreboot: 1560649 Sandybridge: Fix MRC cache calculation
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1046 -gerrit commit 15606496889239bcfa231ed416b7a1f34033ccb7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 11:21:10 2012 -0700 Sandybridge: Fix MRC cache calculation The MRC region is described by Kconfig variables, no further math or parsing is required at this point. Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/mrccache.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 5c4c382..aad2b91 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -65,8 +65,8 @@ u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { u8 *mrc_region; u32 region_size; - u32 *data; #ifdef USE_FDT_FMAP_FOR_MRC_CACHE + u32 *data; const struct fdt_header *fdt_header; const struct fdt_property *fdtp; int offset, len; @@ -114,10 +114,8 @@ u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) region_size = fdt32_to_cpu(data[1]); mrc_region = (u8*)((unsigned long)flashrom_base + fdt32_to_cpu(data[0])); #else - data = (u32 *)((void *)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION + 12)); - region_size = CONFIG_MRC_CACHE_SIZE; - mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + be32_to_cpu(data[0])); + mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); #endif *mrc_region_ptr = (struct mrc_data_container *)mrc_region;

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Patch set updated for coreboot: 63acdad Sandybridge: Remove remnants of FDT support from MRC cache code
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1051 -gerrit commit 63acdad535f94580b137661a97a99264c5d00541 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 14:16:47 2012 -0700 Sandybridge: Remove remnants of FDT support from MRC cache code Originally, ChromeBooks would get the offset of the MRC cache from an entry in the u-boot device tree. Not everyone wants to use u-boot on Sandybridge systems, however. Since the new code (based on Kconfig) is now fully working, we can drop the u-boot device tree remnants. Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/mrccache.c | 80 ++++---------------------- 1 files changed, 11 insertions(+), 69 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index aad2b91..d774ff0 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -28,19 +28,6 @@ #include "sandybridge.h" #include <spi.h> #include <spi_flash.h> -/* Using the FDT FMAP for finding the MRC cache area requires including FDT - * support in coreboot, which we would like to avoid. There are a number of - * options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - For ChromeOS devices: implement native FMAP - * - For non-ChromeOS devices: use CBFS - * For now let's leave this code in here until the issue is sorted out in - * a way that works for everyone. - */ -#undef USE_FDT_FMAP_FOR_MRC_CACHE -#ifdef USE_FDT_FMAP_FOR_MRC_CACHE -#include <fdt/libfdt.h> -#endif struct mrc_data_container *next_mrc_block(struct mrc_data_container *mrc_cache) { @@ -61,64 +48,19 @@ int is_mrc_cache(struct mrc_data_container *mrc_cache) return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); } +/* Right now, the offsets for the MRC cache area are hard-coded in the + * northbridge Kconfig. In order to make this more flexible, there are + * a number of options: + * - Have each mainboard Kconfig supply a hard-coded offset + * - For ChromeOS devices: implement native FMAP + * - For non-ChromeOS devices: use CBFS + */ u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { - u8 *mrc_region; - u32 region_size; -#ifdef USE_FDT_FMAP_FOR_MRC_CACHE - u32 *data; - const struct fdt_header *fdt_header; - const struct fdt_property *fdtp; - int offset, len; - const char *compatible = "chromeos,flashmap"; - const char *subnode = "rw-mrc-cache"; - const char *property = "reg"; - u64 flashrom_base = 0; - - fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT); - - if (!fdt_header) { - printk(BIOS_ERR, "%s: no FDT found!\n", __func__); - return 0; - } - - offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible); - if (offset < 0) { - printk(BIOS_ERR, "%s: no %s node found!\n", - __func__, compatible); - return 0; - } - - if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) { - printk(BIOS_ERR, "%s: no base address in node name!\n", - __func__); - return 0; - } - - offset = fdt_subnode_offset(fdt_header, offset, subnode); - if (offset < 0) { - printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode); - return 0; - } - - fdtp = fdt_get_property(fdt_header, offset, property, &len); - if (!fdtp || (len != 8)) { - printk(BIOS_ERR, "%s: property %s at %p, len %d!\n", - __func__, property, fdtp, len); - return 0; - } - - data = (u32 *)fdtp->data; - - // Calculate actual address of the MRC cache in memory - region_size = fdt32_to_cpu(data[1]); - mrc_region = (u8*)((unsigned long)flashrom_base + fdt32_to_cpu(data[0])); -#else - region_size = CONFIG_MRC_CACHE_SIZE; - mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); -#endif - *mrc_region_ptr = (struct mrc_data_container *)mrc_region; + u32 region_size = CONFIG_MRC_CACHE_SIZE; + *mrc_region_ptr = (struct mrc_data_container *) + (CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); return region_size; } @@ -182,7 +124,7 @@ struct mrc_data_container *find_current_mrc_cache(void) entry_id++; mrc_cache = mrc_next; mrc_next = next_mrc_block(mrc_cache); - /* Stay in the mrcdata region defined in fdt */ + /* Stay in the mrc data region */ if ((void*)mrc_next >= (void*)(mrc_region + region_size)) break; }

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Patch set updated for coreboot: 3255dae Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1044 -gerrit commit 3255dae09981daa753118fd3f9cd46dbd071001a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 22 15:24:51 2012 -0700 Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled Right now coreboot compilation fails when SPI flash debugging is enabled. Fix it by using the right set of memory functions. Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/spi/spi_flash.c | 1 - src/southbridge/intel/bd82x6x/spi.c | 12 ++++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 2c0f702..0b859f3 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -264,7 +264,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, #if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: Got idcodes\n"); - print_buffer(0, idcode, 1, sizeof(idcode), 0); #endif /* count the number of continuation bytes */ diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 2508a96..95fbfb9 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -162,7 +162,7 @@ enum { static u8 readb_(const void *addr) { - u8 v = readb(addr); + u8 v = read8((unsigned long)addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -170,7 +170,7 @@ static u8 readb_(const void *addr) static u16 readw_(const void *addr) { - u16 v = readw(addr); + u16 v = read16((unsigned long)addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -178,7 +178,7 @@ static u16 readw_(const void *addr) static u32 readl_(const void *addr) { - u32 v = readl(addr); + u32 v = read32((unsigned long)addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -186,21 +186,21 @@ static u32 readl_(const void *addr) static void writeb_(u8 b, const void *addr) { - writeb(b, addr); + write8((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } static void writew_(u16 b, const void *addr) { - writew(b, addr); + write16((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } static void writel_(u32 b, const void *addr) { - writel(b, addr); + write32((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); }

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Patch set updated for coreboot: a770d5e Add support for Panther Point to SPI driver
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1048 -gerrit commit a770d5e34857f2641e973806f64aad6364ed6fbb Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 11:18:35 2012 -0700 Add support for Panther Point to SPI driver Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/device/pci_ids.h | 2 ++ src/southbridge/intel/bd82x6x/spi.c | 29 ++++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 1765293..4ebd572 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2504,6 +2504,8 @@ #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5d #define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc /* Intel 82801E (C-ICH) */ diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 95fbfb9..ccc530d 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -286,11 +286,24 @@ void spi_free_slave(struct spi_slave *_slave) free(slave); } -static inline int spi_is_cougarpoint_lpc(uint16_t device_id) +/* + * Check if this device ID matches one of supported Intel PCH devices. + * + * Return the ICH version if there is a match, or zero otherwise. + */ +static inline int get_ich_version(uint16_t device_id) { - return device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX; -}; + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) + return 7; + + if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || + (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) + return 9; + + return 0; +} void spi_init(void) { @@ -313,11 +326,9 @@ void spi_init(void) return; } - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) { - ich_version = 7; - } else if (spi_is_cougarpoint_lpc(device_id)) { - ich_version = 9; - } else { + ich_version = get_ich_version(device_id); + + if (!ich_version) { printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n"); return; }

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Patch set updated for coreboot: 1d0ab4d Move subsystem IDs to devicetree.cb
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1042 -gerrit commit 1d0ab4d60b763fe740e4ae94d0dd4ca692286494 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 15 12:36:57 2012 -0700 Move subsystem IDs to devicetree.cb A while back coreboot was changed to read the subsystem IDs from devicetree.cb to allow each onboard PCI device to have its own subsystem id. When we originally branched, this was not the case, and the sandybridge/ivybridge mainboards have not been updated yet. Also, drop the subsystem ID from Emerald Lake 2, since it's not a Google device. Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/intel/emeraldlake2/Kconfig | 8 -------- src/mainboard/samsung/lumpy/Kconfig | 8 -------- src/mainboard/samsung/lumpy/devicetree.cb | 1 + src/mainboard/samsung/stumpy/Kconfig | 8 -------- src/mainboard/samsung/stumpy/devicetree.cb | 1 + 5 files changed, 2 insertions(+), 24 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 9e4f347..873d273 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -43,12 +43,4 @@ config VGA_BIOS_FILE string default "pci8086,0166.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 - endif # BOARD_INTEL_EMERALDLAKE2 diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 200edac..0835012 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -44,14 +44,6 @@ config VGA_BIOS_FILE string default "pci8086,0106.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 - config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool default n diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 36af1ca..3e93df4 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -33,6 +33,7 @@ chip northbridge/intel/sandybridge end device pci_domain 0 on + subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index dda3002..18094cf 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -43,14 +43,6 @@ config VGA_BIOS_FILE string default "pci8086,0106.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 - config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool default n diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index f10b283..b59dcb2 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -28,6 +28,7 @@ chip northbridge/intel/sandybridge end device pci_domain 0 on + subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller

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Patch set updated for coreboot: ae114e9 Implement %zu / %zd in printk
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1043 -gerrit commit ae114e94989a273015a758ffcd4260d88be8050f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 15 13:28:07 2012 -0700 Implement %zu / %zd in printk The SPI drivers from u-boot make heavy use of %zu/%zd (size_t/ssize_t). Implement this in our printk implementation so we get useful output. Change-Id: I91798ff4f28b9c3cd4db204c7ec503596d247dcd Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/console/vtxprintf.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index a370e5f..28c5a60 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -170,7 +170,7 @@ repeat: /* get the conversion qualifier */ qualifier = -1; - if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') { + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt == 'z') { qualifier = *fmt; ++fmt; if (*fmt == 'l') { @@ -218,7 +218,6 @@ repeat: field_width, precision, flags); continue; - case 'n': if (qualifier == 'L') { long long *ip = va_arg(args, long long *); @@ -265,6 +264,8 @@ repeat: num = va_arg(args, unsigned long long); } else if (qualifier == 'l') { num = va_arg(args, unsigned long); + } else if (qualifier == 'z') { + num = va_arg(args, size_t); } else if (qualifier == 'h') { num = (unsigned short) va_arg(args, int); if (flags & SIGN)

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Patch set updated for coreboot: f394b77 Reduce default verbosity of SPI flash drivers
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1045 -gerrit commit f394b77b035c83008bdc67a6ff532ae587267dd2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 11:03:29 2012 -0700 Reduce default verbosity of SPI flash drivers Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled. Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/spi/eon.c | 2 ++ src/drivers/spi/macronix.c | 2 ++ src/drivers/spi/spansion.c | 2 ++ src/drivers/spi/stmicro.c | 2 ++ src/drivers/spi/winbond.c | 2 ++ 5 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index b7c0630..7d9bc44 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -85,9 +85,11 @@ static int eon_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index abf59c9..148527d 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -141,9 +141,11 @@ static int macronix_write(struct spi_flash *flash, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 5479cae..511091b 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -162,9 +162,11 @@ static int spansion_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 9322c06..ccdfa00 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -163,9 +163,11 @@ static int stmicro_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index a2feb7a..0e50843 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -130,9 +130,11 @@ static int winbond_write(struct spi_flash *flash, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); if (ret < 0) {

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Patch set updated for coreboot: 1ef774a Fix printk types in SPI flash drivers
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1041 -gerrit commit 1ef774ab8232f66de72fb2dcd796ee819476b213 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 14 13:52:32 2012 -0700 Fix printk types in SPI flash drivers - use %zu instead of %zd for size_t (%zd is for ssize_t) - use %x instead of %lx for u32 - break some long lines to avoid commit hook trouble Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/spi/eon.c | 2 +- src/drivers/spi/macronix.c | 7 ++++--- src/drivers/spi/spansion.c | 3 ++- src/drivers/spi/sst.c | 2 +- src/drivers/spi/stmicro.c | 3 ++- src/drivers/spi/winbond.c | 8 ++++---- 6 files changed, 14 insertions(+), 11 deletions(-) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 4056953..b7c0630 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -86,7 +86,7 @@ static int eon_write(struct spi_flash *flash, cmd[3] = byte_addr; printk(BIOS_SPEW, - "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 130e746..abf59c9 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -141,7 +141,8 @@ static int macronix_write(struct spi_flash *flash, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); @@ -165,8 +166,8 @@ static int macronix_write(struct spi_flash *flash, byte_addr = 0; } - printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes @ 0x%lx\n", - len, offset - len); + printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes @" + " 0x%lx\n", len, (unsigned long)(offset - len)); spi_release_bus(flash->spi); return ret; diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index a4f370a..5479cae 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -162,7 +162,8 @@ static int spansion_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index c5bec12..8245f72 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -195,7 +195,7 @@ sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) done: printk(BIOS_INFO, "SF: SST: program %s %zu bytes @ 0x%lx\n", - ret ? "failure" : "success", len, offset - actual); + ret ? "failure" : "success", len, (unsigned long)offset - actual); spi_release_bus(flash->spi); return ret; diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 8cbdad5..9322c06 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -163,7 +163,8 @@ static int stmicro_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 65818d5..a2feb7a 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -130,8 +130,8 @@ static int winbond_write(struct spi_flash *flash, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %ld\n", - buf + actual, + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); @@ -155,8 +155,8 @@ static int winbond_write(struct spi_flash *flash, byte_addr = 0; } - printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes @ 0x%lx\n", - len, offset - len); + printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes @" + " 0x%lx\n", len, (unsigned long)(offset - len)); ret = 0; out:

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coreboot May 2012