coreboot May 2012

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Patch merged into coreboot/master: 68ae60f Move VSA support from x86 to Geode
by gerrit＠coreboot.org 01 May '12

01 May '12

the following patch was just integrated into master: commit 68ae60f6d9bcef7e365a3a00fbe78111e7da7ee6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 23:56:58 2012 +0200 Move VSA support from x86 to Geode Instead of the special case in the generic Makefile.inc, use cbfs-files in the CPU directories. Change-Id: I71d9c8dff906c9a516ac0dd09a315f8956075592 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/962 for details. -gerrit

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Patch merged into coreboot/master: 2558f47 Support adding stages with cbfs-files
by gerrit＠coreboot.org 01 May '12

01 May '12

the following patch was just integrated into master: commit 2558f479d59042d9748ba931fa2436cc07faa933 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 23:53:56 2012 +0200 Support adding stages with cbfs-files stages have special cbfstool syntax, which we need to support. Change-Id: I119255246af818f010acfc7ec2091a6184e74eb3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/961 for details. -gerrit

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Patch merged into coreboot/master: e6089c3 Add vsa processor to cbfs-files
by gerrit＠coreboot.org 01 May '12

01 May '12

the following patch was just integrated into master: commit e6089c31deb1712509edd11c15081a4a189b325a Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 23:15:17 2012 +0200 Add vsa processor to cbfs-files Change-Id: I548e86084acc51b0471160d37439385f524224cf Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/960 for details. -gerrit

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Patch merged into coreboot/master: 63385c6 Make geode_lx use the vsa from blobs repository
by gerrit＠coreboot.org 01 May '12

01 May '12

the following patch was just integrated into master: commit 63385c66126389fec8b6abc5923ec477442b360b Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Apr 30 22:56:30 2012 +0200 Make geode_lx use the vsa from blobs repository ... or fail if repository is not enabled. Change-Id: I0a1e6d6fed852ec7edf96ace8346ae6b23838a56 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/959 for details. -gerrit

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Patch merged into coreboot/master: 887793d Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.
by gerrit＠coreboot.org 01 May '12

01 May '12

the following patch was just integrated into master: commit 887793df39d78bcdab65cb965a98fcd31b88fca4 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Mar 29 17:58:52 2012 -0700 Set up the Emerald Lake 2 SMI and SCI sources based on the schematic. This sets up the SMI and SCI inputs on the PCH for Emerald Lake 2 based on my best interpretation of the schematic. It may not be correct, but it doesn't seem to cause any problems either. Change-Id: I21238b3853a92893ec7f08baa2a3ebd35c49dd97 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue May 1 07:24:16 2012, giving +2 See http://review.coreboot.org/964 for details. -gerrit

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New patch to review for coreboot: 9297200 Allow device ID arrays in the PCI driver structure
by Vadim Bendebury 01 May '12

01 May '12

Vadim Bendebury (vbendeb(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/982 -gerrit commit 929720020030761885433ef7027005480812424b Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Apr 24 12:53:19 2012 -0700 Allow device ID arrays in the PCI driver structure Many PCI devices share the very same driver despite having different PCI device IDs, which causes a lot of copy and paste of driver definitions. This change introduces a way to specify the array of acceptable device IDs in a single driver entry. As an example the Intel {Sandy|Ivy} Bridge SATA driver is being modified to use a single driver structure for all different SATA controller flavors, a few more Ivy Bridge IDs are being added as well. BUG=none TEST=manual . modified coreboot brought up an Ivy Bridge platform all the way to Linux login screen. Change-Id: I761c5611b93ef946053783f7a755e6c456dd6991 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/devices/pci_device.c | 24 +++++++++++++++++++++++- src/include/device/pci.h | 1 + src/southbridge/intel/bd82x6x/sata.c | 27 ++++----------------------- 3 files changed, 28 insertions(+), 24 deletions(-) diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index c055995..c9af7c4 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -796,6 +796,28 @@ static struct device_operations *get_pci_bridge_ops(device_t dev) } /** + * Check if a device id matches a PCI driver entry. + * + * The driver entry can either point at a zero terminated array of acceptable + * device IDs, or include a single device ID. + * + * @driver pointer to the PCI driver entry being checked + * @device_id PCI device ID of the device being matched + */ +static int device_id_match(struct pci_driver *driver, unsigned short device_id) +{ + if (driver->devices) { + unsigned short check_id; + const unsigned short *device_list = driver->devices; + while ((check_id = *device_list++) != 0) + if (check_id == device_id) + return 1; + } + + return (driver->device == device_id); +} + +/** * Set up PCI device operation. * * Check if it already has a driver. If not, use find_device_operations(), @@ -817,7 +839,7 @@ static void set_pci_ops(struct device *dev) */ for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) { if ((driver->vendor == dev->vendor) && - (driver->device == dev->device)) { + device_id_match(driver, dev->device)) { dev->ops = (struct device_operations *)driver->ops; printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n", dev_path(dev), driver->vendor, driver->device, diff --git a/src/include/device/pci.h b/src/include/device/pci.h index d4cfb85..e864d6d 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -42,6 +42,7 @@ struct pci_driver { const struct device_operations *ops; unsigned short vendor; unsigned short device; + const unsigned short *devices; }; #define __pci_driver __attribute__ ((used,__section__(".rodata.pci_driver"))) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 057b882..fef12cd 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -215,32 +215,13 @@ static struct device_operations sata_ops = { .ops_pci = &sata_pci_ops, }; +static const unsigned short all_dev_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, + 0x1e00, 0x1e01, 0x1e02, 0x1e03, + 0 }; /* Non-AHCI and Non-RAID Mode */ static const struct pci_driver pch_sata_normal_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c00, -}; -static const struct pci_driver pch_sata_mobile_normal_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c01, -}; - -/* AHCI Mode */ -static const struct pci_driver pch_sata_ahci_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c02, -}; -static const struct pci_driver pch_sata_mobile_ahci_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c03, -}; -static const struct pci_driver pch_sata_mobile_ahci_driver_a __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1e03, + .devices = all_dev_ids, };

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New patch to review for coreboot: f7738ff Add simple PMIO & PMIO2 read/write routines to CIMX wrapper
by Martin Roth 01 May '12

01 May '12

Martin Roth (martin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/981 -gerrit commit f7738ffdbf221cb4ae80ce3172e8dfa3a54e043d Author: Martin Roth <martin(a)se-eng.com> Date: Sat Apr 28 10:25:20 2012 -0600 Add simple PMIO & PMIO2 read/write routines to CIMX wrapper These are the PMIO & PMIO2 read & write routines from src/southbridge/amd/sb800/sb800.c & sb800.h for use in the cimx tree. Currently most platforms using CIMX are calling WritePMIO() directly from the src/vendorcode/amd/cimx/sbX00 directories instead of using a wrapper function. These functions only do byte reads & writes. Change-Id: I881a6e2d4ddbba3dbdf4dd33e06313fe88b3682a Signed-off-by: Martin L Roth <martin(a)se-eng.com> --- src/southbridge/amd/cimx/Makefile.inc | 4 ++ src/southbridge/amd/cimx/cimx_util.c | 52 +++++++++++++++++++++++++++++++++ src/southbridge/amd/cimx/cimx_util.h | 36 ++++++++++++++++++++++ 3 files changed, 92 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index 80c6378..a9ea8b9 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -19,3 +19,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 + +romstage-y += cimx_util.c + +ramstage-y += cimx_util.c diff --git a/src/southbridge/amd/cimx/cimx_util.c b/src/southbridge/amd/cimx/cimx_util.c new file mode 100755 index 0000000..ca4c86a --- /dev/null +++ b/src/southbridge/amd/cimx/cimx_util.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <arch/io.h> +#include "cimx_util.h" + +static void pmio_write_index(u16 port_base, u8 reg, u8 value) +{ + outb(reg, port_base); + outb(value, port_base + 1); +} + +static u8 pmio_read_index(u16 port_base, u8 reg) +{ + outb(reg, port_base); + return inb(port_base + 1); +} + +void pm_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM_INDEX, reg, value); +} + +u8 pm_ioread(u8 reg) +{ + return pmio_read_index(PM_INDEX, reg); +} + +void pm2_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM2_INDEX, reg, value); +} + +u8 pm2_ioread(u8 reg) +{ + return pmio_read_index(PM2_INDEX, reg); +} diff --git a/src/southbridge/amd/cimx/cimx_util.h b/src/southbridge/amd/cimx/cimx_util.h new file mode 100755 index 0000000..4ef534c --- /dev/null +++ b/src/southbridge/amd/cimx/cimx_util.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CIMX_UTIL_H +#define CIMX_UTIL_H + +#include <stdint.h> + +/* Power management index/data registers */ +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 +#define PM2_INDEX 0xcd0 +#define PM2_DATA 0xcd1 + +void pm_iowrite(u8 reg, u8 value); +u8 pm_ioread(u8 reg); +void pm2_iowrite(u8 reg, u8 value); +u8 pm2_ioread(u8 reg); + +#endif /* CIMX_UTIL_H */

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coreboot May 2012