May 2012 - coreboot - mail.coreboot.org

Re: [coreboot] bluetooth on Thinkpad X60s
by Patrick Georgi May 2, 2012

May 2, 2012

Am Di 01 Mai 2012 23:14:48 CEST schrieb Motiejus Jakštys: > Besides, why isn't it default yet? What are the blockers to enable > this option by default (in perfect world, it should be enabled?)? In a perfect world, yes. Problem is, not all boards define a useful CMOS layout (or use the values defined therein, if they simply copy&pasted the data). If they don't define any layout, the build (probably) breaks. If they define bogus values, that will confuse users. Maybe at some point we should just make it the default. Patrick

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New patch to review for coreboot: c22e7fe ChromeOS: drop unused debug header description No part of ChromeOS seems to use the debug header description, so drop it to make sure it does not get copied around wrongly.
by Stefan Reinauer May 2, 2012

May 2, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/989 -gerrit commit c22e7fe544fe5418e8671afc2c6b6e08a71f0915 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 1 17:04:51 2012 -0700 ChromeOS: drop unused debug header description No part of ChromeOS seems to use the debug header description, so drop it to make sure it does not get copied around wrongly. Change-Id: Icb0baedbf6112f11289b2ddd9618a955a424ddf7 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/intel/emeraldlake2/acpi/chromeos.asl | 8 -------- src/mainboard/samsung/stumpy/acpi/chromeos.asl | 8 -------- 2 files changed, 0 insertions(+), 16 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl index 81ead2e..6a61b0d 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl @@ -68,14 +68,6 @@ Device (CRHW) Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect - Package() { 0x100, 0, 9, "CougarPoint" }, // debug header gpio - Package() { 0x101, 0, 10, "CougarPoint" }, // debug header gpio 1 - Package() { 0x102, 0, 12, "CougarPoint" }, // debug header gpio 2 - Package() { 0x103, 0, 13, "CougarPoint" }, // debug header gpio 3 - Package() { 0x104, 0, 14, "CougarPoint" }, // debug header gpio 4 - Package() { 0x105, 0, 15, "CougarPoint" }, // debug header gpio 5 - Package() { 0x106, 0, 24, "CougarPoint" }, // debug header gpio 6 - Package() { 0x107, 0, 26, "CougarPoint" }, // debug header gpio 7 }) Return (OIPG) diff --git a/src/mainboard/samsung/stumpy/acpi/chromeos.asl b/src/mainboard/samsung/stumpy/acpi/chromeos.asl index 65202cb..f517b16 100644 --- a/src/mainboard/samsung/stumpy/acpi/chromeos.asl +++ b/src/mainboard/samsung/stumpy/acpi/chromeos.asl @@ -68,14 +68,6 @@ Device (CRHW) Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect - Package() { 0x100, 0, 9, "CougarPoint" }, // debug header gpio - Package() { 0x101, 0, 10, "CougarPoint" }, // debug header gpio 1 - Package() { 0x102, 0, 12, "CougarPoint" }, // debug header gpio 2 - Package() { 0x103, 0, 13, "CougarPoint" }, // debug header gpio 3 - Package() { 0x104, 0, 14, "CougarPoint" }, // debug header gpio 4 - Package() { 0x105, 0, 15, "CougarPoint" }, // debug header gpio 5 - Package() { 0x106, 0, 24, "CougarPoint" }, // debug header gpio 6 - Package() { 0x107, 0, 26, "CougarPoint" }, // debug header gpio 7 }) Return (OIPG)

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New patch to review for coreboot: d4508c2 Don't include console.h in microcode.c when compiling with ROMCC
by Stefan Reinauer May 1, 2012

May 1, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/988 -gerrit commit d4508c295915bfad6b19daf4b39a5fa3de631d22 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 1 16:53:22 2012 -0700 Don't include console.h in microcode.c when compiling with ROMCC If microcode.c is built by romcc, this indicates that we are running microcode updates in the bootblock (e.g. before enabling cache as ram). In this case we did not enable any consoles yet, so we don't output anything. This patch removes inclusion of the unnecessary console/console.h for that case, which was breaking with certain configurations. Change-Id: Iebb57794d7b1e84cac253d249d47b88de4dd28a3 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/microcode/microcode.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 1511798..ae1c26a 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -20,7 +20,9 @@ /* Microcode update for Intel PIII and later CPUs */ #include <stdint.h> +#if !defined(__ROMCC__) #include <console/console.h> +#endif #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h>

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New patch to review for coreboot: b95dd5f Make Intel i5000 specific options only appear on i5000 systems
by Stefan Reinauer May 1, 2012

May 1, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/986 -gerrit commit b95dd5fb7ed289cea3bb2914077874560351c1fa Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 1 16:35:03 2012 -0700 Make Intel i5000 specific options only appear on i5000 systems Change-Id: If183611b0b62d9321a5a12311c4cb3b344b04b36 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/i5000/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig index 0595a57..b5bc3d6 100644 --- a/src/northbridge/intel/i5000/Kconfig +++ b/src/northbridge/intel/i5000/Kconfig @@ -24,3 +24,4 @@ config NORTHBRIDGE_INTEL_I5000 config NORTHBRIDGE_INTEL_I5000_RAM_CHECK bool prompt "Run ramcheck after RAM initialization" + depends on NORTHBRIDGE_INTEL_I5000

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New patch to review for coreboot: 4a2a115 Strip quotes from Sandybridge MRC blob
by Stefan Reinauer May 1, 2012

May 1, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/987 -gerrit commit 4a2a1152bdaea766df1de7645f2320d69fe10a57 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 1 16:37:18 2012 -0700 Strip quotes from Sandybridge MRC blob This fixes my build when specifying an absolute path to the binary. Change-Id: I95fb3960be70f78146c6afeb9cc777dccdca6b5b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/Makefile.inc | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index b72e9fa..3dcbe2b 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -32,7 +32,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c # We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin -mrc.bin-file := $(CONFIG_MRC_FILE) +mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) ifeq ($(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE),y) mrc.bin-position := 0xfffa0000 endif

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Re: [coreboot] bluetooth on Thinkpad X60s
by Patrick Georgi May 1, 2012

May 1, 2012

Am Di 01 Mai 2012 21:24:00 CEST schrieb Motiejus Jakštys: > 2) The only way to disable bluetooth device now is modifying coreboot > source code. There should be a better way. Compile-time configuration > (via make menuconfig) would be feasible and doable for me. However, > any better suggestions? It would be *perfect*, if it was possible to > toggle it at runtime. How could I figure out if it is possible? > > Pointers appreciated. The get_option function uses CMOS nvram, but that has to be compiled in (which isn't the default in the tree yet). The nvram can be configured with our nvramtool (see util/nvramtool). When booting a coreboot equipped system, nvramtool automatically determines the available fields and their legal values from a table kept in RAM by coreboot. Patrick

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New patch to review for coreboot: 241e572 Enable USE_OPTION_TABLE for ThinkPad X60
by Motiejus Jakštys May 1, 2012

May 1, 2012

Motiejus Jakštys (desired.mta(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/985 -gerrit commit 241e57244fe64f0a3b15f72972129ebaacd75d2f Author: Motiejus Jakštys <desired.mta(a)gmail.com> Date: Tue May 1 21:47:16 2012 +0100 Enable USE_OPTION_TABLE for ThinkPad X60 Without this option bluetooth configuration value in nvram is not consulted properly. It also enables built-in volume control (read-only). Tested on: ThinkPad X60s, 1702. Change-Id: I2fc6bb527c6e086a083e63922d1253eda7d4a36d Signed-off-by: Motiejus Jakštys <desired.mta(a)gmail.com> --- src/mainboard/lenovo/x60/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index d35ab03..e77fac6 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME + select USE_OPTION_TABLE config MAINBOARD_DIR string

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Patch merged into coreboot/master: aea1621 Fix issue with PCIe power management setup
by gerrit＠coreboot.org May 1, 2012

May 1, 2012

the following patch was just integrated into master: commit aea1621bd1489a910483d2858dc5810c8d48207e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Apr 27 10:58:22 2012 -0700 Fix issue with PCIe power management setup The current early PM setup that attempts to configure dynamic clock gating relies on PCIe functions to be enabled that may not be. Instead of reading port 0 or 4 directly to determine the link width use the register that refelects the soft strapping options as this will always be available. Also add a clear register assignment and break for port 0 in the switch statement instead of falling through to port 4 as that could end up setting the slot power limit based on port 4 values instead of based on port 0. register 0xE1=0x3f and all other root ports should have 0xE1=0x03. When port 0 and 4 are disabled they will have 0xE1=0x3C before being disabled by the pch enable handler. LUMPY default: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5) pci_read8 0 0x1c 0 0xe1 0x3f pci_read8 0 0x1c 3 0xe1 0x03 LUMPY with PCIe port coalesce enabled: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5) pci_read8 0 0x1c 0 0xe1 0x3f pci_read8 0 0x1c 1 0xe1 0x03 Change-Id: I33a37b0ec0c8e570cf5d9dda2c06e0225fee135c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue May 1 06:41:55 2012, giving +1 See http://review.coreboot.org/980 for details. -gerrit

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Re: [coreboot] bluetooth on Thinkpad X60s
by Patrick Georgi May 1, 2012

May 1, 2012

Am Di 01 Mai 2012 20:24:10 CEST schrieb Motiejus Jakštys: > On Tue, May 1, 2012 at 16:18, Patrick Georgi <patrick(a)georgi-clan.de> wrote: >> val = 1; >> get_option(&val, "bluetooth"); >> h8_bluetooth_enable(val); >> >> get_option only updates the value pointed to by the first argument if >> there's something to update to (CMOS use must be enabled _and_ CMOS must >> contain valid data). Otherwise it's kept as is. > Do I understand it correctly that you have just sent a valid patch > which could be included? Not a patch. But close. I have no way to test it. I also don't know if "bluetooth enabled by default" is the way to go on that system. With all that covered, a patch could be made and uploaded to review.coreboot.org. Patrick

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Patch merged into coreboot/master: 050c40f Add an option to enable PCIe root port coalescing
by gerrit＠coreboot.org May 1, 2012

May 1, 2012

the following patch was just integrated into master: commit 050c40f1dcee3945709146abf0c8cfd47b4abca3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Apr 27 10:30:51 2012 -0700 Add an option to enable PCIe root port coalescing Background: The PCI spec (3.0-3.2.2.3.4) requires that PCI devices implement function 0. The Linux Kernel therefore will not enumerate a PCI device if it does not present a valid config space at function 0. If a board does not have anything connected to root port 0 and it is desired to disable the unused ports in order to save power then this will cause the other downstream PCIe devices to go missing as they will not be enumerated. Intel chipsets provide a way to map root port numbers to different PCI function numbers, thereby avoiding this issue and allowing root port 0 to be turned off. This change adds a new chip config option 'pcie_port_coalesce' that will collapse the enabled root ports into a linear map starting at zero. This option defaults to disabled as it can have a confusing effect on the system as the declared static devicetree may not match what is seen at runtime. This option is also forced on if the static devicetree disables port 0. When each root port is processed in the early enable stage it looks for a lower numbered root port that has been disabled and then swaps the two assigned function numbers. However the mapping register is write-once so it has to keep track of the proposed mapping changes until all ports have been processed before writing out the final map value. At this point it also updates the function numbers in the static device tree so they are consistent with the new layout. There are a few other closely related fixes in this change: 1) There is a power savings opportunity if an entire bank of ports (0-3 or 4-7) are disabled. This was checking the chipset revision to look for CougarPoint B1+ stepping and that was not passing on PantherPoint where this should always be applied. To fix this I added a function to determine the chipset type based on comparing the upper byte of the device ID. 2) Apply the same chipset type check fix to the IOBP programming. 3) There is another power savings opportunity to enable dynamic clock gating on shared PCIe resources which only applies to ports 0 and 4. However if 0 or 4 is disabled then the later check to enable this would fail as that device is already hidden. LUMPY current: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5) 01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01) 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B LUMPY with PCIe port coalesce enabled: 00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5) 00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5) 01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01) 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B Change-Id: I828aa407fdc9c156c1c42eda8e2d893c0aa66eef Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue May 1 06:27:44 2012, giving +1 See http://review.coreboot.org/979 for details. -gerrit

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