Patch set updated for coreboot: 3a99e2c Provide functions to access arbitrary GPIO pins and vectors

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1049

-gerrit

commit 3a99e2cd0443e017d6978930db98ad579af5a93f
Author: Vadim Bendebury 
Date:   Tue May 15 14:18:59 2012 -0700

Provide functions to access arbitrary GPIO pins and vectors

This change adds utility functions which allow to read any GPIO pin,
    as well as a vector of GPIO pin values.

As presented, these functions will be available to Sandy Bridge and
    Ivy Bridge systems only.

There is no error checking: trying to read GPIO pin number which
    exceeds actual number of pins will return zero, trying to read GPIO
    which is not actually configured as such will return unpredictable
    value.

When reading a GPIO pin vector, the pin numbers are passed in an
    array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a
    three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass
    pointer to array of {4, 2, 15, -1}.

Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d
    Signed-off-by: Vadim Bendebury 
---
 src/southbridge/intel/bd82x6x/gpio.c |   37 ++++++++++++++++++++++++++++++++++
 src/southbridge/intel/bd82x6x/gpio.h |    8 +++++++
 2 files changed, 45 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c
index 598726a..2ba34ea 100644
--- a/src/southbridge/intel/bd82x6x/gpio.c
+++ b/src/southbridge/intel/bd82x6x/gpio.c
@@ -25,6 +25,8 @@
 #include "pch.h"
 #include "gpio.h"

+#define MAX_GPIO_NUMBER 75 /* zero based */
+
 void setup_pch_gpios(const struct pch_gpio_map *gpio)
 {
    u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
@@ -63,3 +65,38 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio)
    if (gpio->set3.reset)
    	outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3);
 }
+
+int get_gpio(int gpio_num)
+{
+	static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48};
+	u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+	int index, bit;
+
+	if (gpio_num > MAX_GPIO_NUMBER)
+		return 0; /* Just ignore wrong gpio numbers. */
+
+	index = gpio_num / 32;
+	bit = gpio_num % 32;
+
+	return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1;
+}
+
+/*
+ * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned get_gpios(const int *gpio_num_array)
+{
+	int gpio;
+	unsigned bitmask = 1;
+	unsigned vector = 0;
+
+	while (bitmask &&
+	       ((gpio = *gpio_num_array++) != -1)) {
+		vector <<= 1;
+		if (get_gpio(gpio))
+			vector |= bitmask;
+		bitmask <<= 1;
+	}
+	return vector;
+}
diff --git a/src/southbridge/intel/bd82x6x/gpio.h b/src/southbridge/intel/bd82x6x/gpio.h
index 214947f..44e808a 100644
--- a/src/southbridge/intel/bd82x6x/gpio.h
+++ b/src/southbridge/intel/bd82x6x/gpio.h
@@ -150,4 +150,12 @@ struct pch_gpio_map {
 /* Configure GPIOs with mainboard provided settings */
 void setup_pch_gpios(const struct pch_gpio_map *gpio);

+/* get GPIO pin value */
+int get_gpio(int gpio_num);
+/*
+ * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned get_gpios(const int *gpio_num_array);
+
 #endif