coreboot May 2012

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Patch merged into coreboot/master: 6c32304 Fix typo on Persimmon #if CONFIG_HAVE_ACPI_RESUME
by gerrit＠coreboot.org 25 May '12

25 May '12

the following patch was just integrated into master: commit 6c323041f289d4453f3d97413ca402276f76f089 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri May 25 12:20:10 2012 -0600 Fix typo on Persimmon #if CONFIG_HAVE_ACPI_RESUME Stupid typo: APCI instead of ACPI in Persimmon. Change-Id: I6fd7f091cf1f5c4c0e1b57c21553dab93b545eab Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Fri May 25 21:08:33 2012, giving +1 See http://review.coreboot.org/1054 for details. -gerrit

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Patch set updated for coreboot: 1a649e8 Update SB800 CIMX FADT
by Martin Roth 25 May '12

25 May '12

Martin Roth (martin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1055 -gerrit commit 1a649e859f956360dbb01b1e5e10fc6ab99f4dbd Author: Martin Roth <martin(a)se-eng.com> Date: Fri May 25 12:23:32 2012 -0600 Update SB800 CIMX FADT - Add #define to allow the FADT PM Profile to be overridden. - Change the location of the PMA_CNT_BLOCK_ADDRESS to match current documentation. - cst_cnt should be 0 if smi_cmd == 0 - add a couple of default access sizes. - Add a couple of #define values for unsupported C2 & C3 entries. - Add PM Profile override value into amd/persimmon platform. This does not use the #defines in acpi.h so that the files that include this don't all need to start including acpi.h. Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094 Signed-off-by: Martin L Roth <martin(a)se-eng.com> --- src/arch/x86/include/arch/acpi.h | 4 +++ src/mainboard/amd/persimmon/platform_cfg.h | 14 +++++++++++ src/southbridge/amd/cimx/sb800/fadt.c | 34 +++++++++++++++------------ 3 files changed, 37 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 9f790cc..8c8106d 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -310,6 +310,10 @@ typedef struct acpi_fadt { #define ACPI_FADT_REV_ACPI_4_0 4 #define ACPI_FADT_REV_ACPI_5_0 5 +/* Flags for p_lvl2_lat and p_lvl3_lat */ +#define ACPI_FADT_C2_NOT_SUPPORTED 101 +#define ACPI_FADT_C3_NOT_SUPPORTED 1001 + /* FADT Feature Flags */ #define ACPI_FADT_WBINVD (1 << 0) #define ACPI_FADT_WBINVD_FLUSH (1 << 1) diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index db3fc15..1065cda 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -256,4 +256,18 @@ const static CODECTBLLIST persimmon_codec_tablelist[] = */ #define AZALIA_OEM_VERB_TABLE (&persimmon_codec_tablelist[0]) +/* set up an ACPI prefered power management profile */ +/* from acpi.h + * PM_UNSPECIFIED = 0, + * PM_DESKTOP = 1, + * PM_MOBILE = 2, + * PM_WORKSTATION = 3, + * PM_ENTERPRISE_SERVER = 4, + * PM_SOHO_SERVER = 5, + * PM_APPLIANCE_PC = 6, + * PM_PERFORMANCE_SERVER = 7, + * PM_TABLET = 8 + */ +#define FADT_PM_PROFILE 1 + #endif diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 3a34519..38b4a27 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -38,6 +38,10 @@ #endif #endif +#ifndef FADT_PM_PROFILE + #define FADT_PM_PROFILE PM_UNSPECIFIED +#endif + /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. @@ -62,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ - fadt->preferred_pm_profile = PM_SOHO_SERVER; + fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */ fadt->smi_cmd = 0; /* disable system management mode */ fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ @@ -85,7 +89,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) val = 0; WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); val = ACPI_PMA_CNT_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val); + WritePMIO(SB_PMIOA_REG6E, AccWidthUint16, &val); /* AcpiDecodeEnable, When set, SB uses the contents of the * PM registers at index 60-6B to decode ACPI I/O address. @@ -104,21 +108,21 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->gpe0_blk = GPE0_BLK_ADDRESS; fadt->gpe1_blk = 0; /* No gpe1 block in hudson1 */ - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 16 bits */ + fadt->pm2_cnt_len = 1; /* 8 bits */ + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; + fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->duty_offset = 1; - fadt->duty_width = 3; + fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ + fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = 0; /* 0x7d these have to be */ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ fadt->century = 0; /* 0x7f to make rtc alrm work */ @@ -157,7 +161,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -195,13 +199,13 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;

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New patch to review for coreboot: 77659fd Update SB800 CIMX FADT
by Martin Roth 25 May '12

25 May '12

Martin Roth (martin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1055 -gerrit commit 77659fd429a1aa44c5089995ebb9566cfce034dc Author: Martin Roth <martin(a)se-eng.com> Date: Fri May 25 12:23:32 2012 -0600 Update SB800 CIMX FADT - Add #define to allow the FADT PM Profile to be overridden. - Change the location of the PMA_CNT_BLOCK_ADDRESS to match current documentation. - cst_cnt should be 0 if smi_cmd == 0 - add a couple of default access sizes. - Add a couple of #define values for unsupported C2 & C3 entries. - Add PM Profile override value into amd/persimmon platform. This does not use the #defines in acpi.h so that the files that include this don't all need to start including acpi.h. Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094 Signed-off-by: Martin L Roth <martin(a)se-eng.com> --- src/arch/x86/include/arch/acpi.h | 4 +++ src/mainboard/amd/persimmon/platform_cfg.h | 14 +++++++++++ src/southbridge/amd/cimx/sb800/fadt.c | 34 +++++++++++++++------------ 3 files changed, 37 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 9f790cc..8c8106d 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -310,6 +310,10 @@ typedef struct acpi_fadt { #define ACPI_FADT_REV_ACPI_4_0 4 #define ACPI_FADT_REV_ACPI_5_0 5 +/* Flags for p_lvl2_lat and p_lvl3_lat */ +#define ACPI_FADT_C2_NOT_SUPPORTED 101 +#define ACPI_FADT_C3_NOT_SUPPORTED 1001 + /* FADT Feature Flags */ #define ACPI_FADT_WBINVD (1 << 0) #define ACPI_FADT_WBINVD_FLUSH (1 << 1) diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index db3fc15..6062115 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -256,4 +256,18 @@ const static CODECTBLLIST persimmon_codec_tablelist[] = */ #define AZALIA_OEM_VERB_TABLE (&persimmon_codec_tablelist[0]) +/* set up an ACPI prefered power management profile */ +/* from acpi.h + * PM_UNSPECIFIED = 0, + * PM_DESKTOP = 1, + * PM_MOBILE = 2, + * PM_WORKSTATION = 3, + * PM_ENTERPRISE_SERVER = 4, + * PM_SOHO_SERVER = 5, + * PM_APPLIANCE_PC = 6, + * PM_PERFORMANCE_SERVER = 7, + * PM_TABLET = 8 + */ +#define FADT_PM_PROFILE 1 + #endif diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 3a34519..38b4a27 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -38,6 +38,10 @@ #endif #endif +#ifndef FADT_PM_PROFILE + #define FADT_PM_PROFILE PM_UNSPECIFIED +#endif + /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. @@ -62,7 +66,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ - fadt->preferred_pm_profile = PM_SOHO_SERVER; + fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */ fadt->smi_cmd = 0; /* disable system management mode */ fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ @@ -85,7 +89,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) val = 0; WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); val = ACPI_PMA_CNT_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val); + WritePMIO(SB_PMIOA_REG6E, AccWidthUint16, &val); /* AcpiDecodeEnable, When set, SB uses the contents of the * PM registers at index 60-6B to decode ACPI I/O address. @@ -104,21 +108,21 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->gpe0_blk = GPE0_BLK_ADDRESS; fadt->gpe1_blk = 0; /* No gpe1 block in hudson1 */ - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 8; + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 16 bits */ + fadt->pm2_cnt_len = 1; /* 8 bits */ + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; - fadt->cst_cnt = 0xe3; - fadt->p_lvl2_lat = 101; - fadt->p_lvl3_lat = 1001; + fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ - fadt->duty_offset = 1; - fadt->duty_width = 3; + fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ + fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = 0; /* 0x7d these have to be */ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ fadt->century = 0; /* 0x7f to make rtc alrm work */ @@ -157,7 +161,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; fadt->x_pm1a_evt_blk.addrh = 0x0; @@ -195,13 +199,13 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; fadt->x_pm_tmr_blk.addrh = 0x0; fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = 64; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;

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Patch set updated for coreboot: 6c32304 Fix typo on Persimmon #if CONFIG_HAVE_ACPI_RESUME
by Marc Jones 25 May '12

25 May '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1054 -gerrit commit 6c323041f289d4453f3d97413ca402276f76f089 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri May 25 12:20:10 2012 -0600 Fix typo on Persimmon #if CONFIG_HAVE_ACPI_RESUME Stupid typo: APCI instead of ACPI in Persimmon. Change-Id: I6fd7f091cf1f5c4c0e1b57c21553dab93b545eab Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/mainboard/amd/persimmon/agesawrapper.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 195ff54..779e198 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -253,7 +253,7 @@ UINT32 GetHeapBase( { UINT32 heap; -#if CONFIG_HAVE_APCI_RESUME +#if CONFIG_HAVE_ACPI_RESUME /* Both romstage and ramstage has this S3 detect. */ if (acpi_get_sleep_type() == 3) heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */

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New patch to review for coreboot: 4db6650 Fix typo on PennStation #if CONFIG_HAVE_ACPI_RESUME
by Marc Jones 25 May '12

25 May '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1054 -gerrit commit 4db66508c3410cce30f80af03cd82d5a4960a83b Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri May 25 12:20:10 2012 -0600 Fix typo on PennStation #if CONFIG_HAVE_ACPI_RESUME Stupid typo: APCI instead of ACPI in PennStation. Change-Id: I6fd7f091cf1f5c4c0e1b57c21553dab93b545eab Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/mainboard/amd/persimmon/agesawrapper.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 195ff54..779e198 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -253,7 +253,7 @@ UINT32 GetHeapBase( { UINT32 heap; -#if CONFIG_HAVE_APCI_RESUME +#if CONFIG_HAVE_ACPI_RESUME /* Both romstage and ramstage has this S3 detect. */ if (acpi_get_sleep_type() == 3) heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */

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Optimizations to GMP build/host tuning break toolchain portability
by Raymond Danks 25 May '12

25 May '12

I'm writing this as a bug for the GMP community and CCing coreboot, although, with the proper direction I can imagine this all ending in a change to the configure flags in the coreboot xgcc build. The coreboot project contains a build script for generating a cross toolchain (xgcc). The versions were recently bumped to: GMP_VERSION=5.0.5 MPFR_VERSION=3.1.0 MPC_VERSION=0.9 LIBELF_VERSION=0.8.13 GCC_VERSION=4.6.3 GCC_AUTOCONF_VERSION=2.64 BINUTILS_VERSION=2.22 For the purposes of this bug, the important change was the move from GMP 5.0.2 to GMP 5.0.5. The issue is that an xgcc toolchain built on one host cannot consistently be moved to a similar operating system on a different host with a different underlying architecture. This was seen with both 32bit and 64bit OS installs under the following configurations: 64bit Build Host Ubuntu 11.04 \n \l Linux ubuntubuilder03 2.6.38-14-server #58-Ubuntu SMP Tue Mar 27 20:21:58 UTC 2012 x86_64 x86_64 x86_64 GNU/Linux vendor_id : AuthenticAMD model name : AMD Athlon(tm) II X4 605e Processor 64bit Execution Host Ubuntu 10.04.3 LTS \n \l Linux beast 2.6.32-24-generic #43-Ubuntu SMP Thu Sep 16 14:58:24 UTC 2010 x86_64 GNU/Linux vendor_id : GenuineIntel model name : Intel(R) Core(TM) i7 CPU Q 720 @ 1.60GHz 32bit Build Host Ubuntu 11.04 \n \l Linux ubuntubuilder04 2.6.38-14-generic-pae #58-Ubuntu SMP Tue Mar 27 19:06:30 UTC 2012 i686 athlon i386 GNU/Linux vendor_id : AuthenticAMD model name : Embedded AMD Opteron(tm) Processor 41KX HE NOTE: The architecture is 64bit, but the operating system is 32bit 32bit Execution Host Ubuntu 11.10 \n \l Linux test2 3.0.0-17-generic #30-Ubuntu SMP Thu Mar 8 17:34:21 UTC 2012 i686 i686 i386 GNU/Linux vendor_id : GenuineIntel model name : Intel(R) Pentium(R) 4 CPU 2.80GHz The following issue symptom does not seem to be limited to Linux operating systems. Cygwin builds using Windows XP VMs and native Windows installs also exhibit the problem. On Linux systems, in the coreboot build on the execution host using a tar'd and copied binary toolchain from the build host resulted in messages like: libpci/libpci.c:221:1: internal compiler error: Illegal instruction make[1]: Entering directory `/home/tester/sage_edk/release_workspace/coreboot/payloads/libpayload' CC libpci/libpci.libpci.o Please submit a full bug report, with preprocessed source if appropriate. See<http://gcc.gnu.org/bugs.html> for instructions. make[1]: Leaving directory `/home/tester/sage_edk/release_workspace/coreboot/payloads/libpayload' make[1]: *** [build/libpci/libpci.libpci.o] Error 1 make: *** [libpayload] Error 2 or ./src/cpu/amd/agesa/cache_as_ram.inc: Assembler messages: ./src/cpu/amd/agesa/cache_as_ram.inc:67: Error: unbalanced parenthesis in operand 1. or romstage.c: Assembler messages: romstage.c:476: Error: value of 4294967296 too large for field of 4 bytes at 4448 romstage.c:477: Error: value of 4294967296 too large for field of 4 bytes at 4460 <snip> On Cygwin systems, the build resulted in messages like: cc1: out of memory allocating 67174399 bytes after a total of 336396288 bytes Makefile:238: recipe for target `build/console/vtxprintf.romstage.o' failed I performed a bisect of the GMP mercurial repository and identified an offending changeset: http://gmplib.org:8000/gmp-5.0/rev/2b7b8ada8a20 By this, I mean, that the xgcc toolchain, when built with any change prior to this GMP version, was able to compile coreboot when moved between build and execution host. I constructed a patch for GMP 5.0.5 reversing this change (attached). Similarly, with this patch, the xgcc toolchain using GMP 5.0.5 is portable. Are the tuning changes made in this change optimal? What are the GMP recommendations for constructing a toolchain that is portable between similar hosts? Thanks, Ray Raymond Danks Sage Electronic Engineering, LLC

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Patch merged into coreboot/master: 88a1ccf nvramtool: use C99 PRIx64 / PRId64 for uint64_t variables
by gerrit＠coreboot.org 25 May '12

25 May '12

the following patch was just integrated into master: commit 88a1ccfa55bad83429c09acdb3cb6e2aa84cb03e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu May 24 13:36:30 2012 -0700 nvramtool: use C99 PRIx64 / PRId64 for uint64_t variables In printf/printk, using %lld or %ld for uint64_t will warn on either 64bit or 32bit machines. However, C99 defines PRIx64 / PRId64 to provide the right modifiers for printing uint64_t variables. Use them instead. Change-Id: I68df5d069a1e99d1a75885173ddfd7815197afea Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri May 25 08:01:34 2012, giving +2 See http://review.coreboot.org/1053 for details. -gerrit

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Patch merged into coreboot/master: c960958 Fix size_t for certain versions of GCC
by gerrit＠coreboot.org 25 May '12

25 May '12

the following patch was just integrated into master: commit c960958a82b43dc4401d8f300e0d90daefc9341f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 14 13:21:08 2012 -0700 Fix size_t for certain versions of GCC When compiling coreboot with the latest ChromeOS toolchain, GCC complains that some printk calls use %zu in connection with size_t types since it resolves the typedefs to long unsigned int. The problem is solved by using the GCC built-in __SIZE_TYPE__ if it exists and define __SIZE_TYPE__ to long unsigned int otherwise. Change-Id: I449c3d385b5633a05e57204704e981de6e017b86 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri May 25 08:00:43 2012, giving +2 See http://review.coreboot.org/1040 for details. -gerrit

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Re: [coreboot] [AMD] Persimmon
by martin.meng＠mic.com.tw 25 May '12

25 May '12

Hello ldwer, >>Are you using a payload? If so, which one are you using? I use SeaBIOS stable version. >Have you checked if there is output on the target's EHCI/serial port, >and what the output is? >See http://www.coreboot.org/Developer_Manual/Tools#Null-modem_cable >and http://www.coreboot.org/EHCI_Debug_Port I have used serial port to dump message, but it always show "▒" char, then I change baud rate 115200 to 38400, but do not help anything. Thanks for your help. Martin -----Original Message----- From: Idwer Vollering [mailto:vidwer@gmail.com] Sent: Thursday, May 24, 2012 5:28 AM To: martin.meng (孟憲君 - MIC) Cc: coreboot(a)coreboot.org Subject: Re: [coreboot] [AMD] Persimmon 2012/5/23 <martin.meng(a)mic.com.tw>: > Hello all, > > > > I check out coreboot and build and run persimmon project via menuconfig, Are you using a payload? If so, which one are you using? > > Mainborad: AMD > > Mainboard Model: Persimon > > FlashSize: 4MB > > > > But it always show 0x00 on my PCI debug card. Have you checked if there is output on the target's EHCI/serial port, and what the output is? See http://www.coreboot.org/Developer_Manual/Tools#Null-modem_cable and http://www.coreboot.org/EHCI_Debug_Port > > I do not know its 80 port default path is LPC or PCI, so > > I have tried to route 80 port to PCI in entry32.inc (src/cpu/x86/32bit), > > But it seem not work. > > > > Can someone help me to solve this issue, > > > > Thanks. > > > > Here is my configuration: > > NorthBridge: AMD family 14 > > SouthBridge: SB800 > > SIO: FNTEK F81865

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Patch set updated for coreboot: b3d2676 Reduce default verbosity of SPI flash drivers
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1045 -gerrit commit b3d2676231863076a3a3965142aeda130ea3f423 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 11:03:29 2012 -0700 Reduce default verbosity of SPI flash drivers Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled. Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/spi/eon.c | 2 ++ src/drivers/spi/macronix.c | 2 ++ src/drivers/spi/spansion.c | 2 ++ src/drivers/spi/stmicro.c | 2 ++ src/drivers/spi/winbond.c | 2 ++ 5 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index b7c0630..7d9bc44 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -85,9 +85,11 @@ static int eon_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 84e79ef..f74eb4f 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -141,9 +141,11 @@ static int macronix_write(struct spi_flash *flash, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 5479cae..511091b 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -162,9 +162,11 @@ static int spansion_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 9322c06..ccdfa00 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -163,9 +163,11 @@ static int stmicro_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 7b6d105..01644b0 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -130,9 +130,11 @@ static int winbond_write(struct spi_flash *flash, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); if (ret < 0) {

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coreboot May 2012