coreboot May 2012

coreboot@coreboot.org

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Patch set updated for coreboot: e41c677 Provide functions to access arbitrary GPIO pins and vectors
by Patrick Georgi 24 May '12

24 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1049 -gerrit commit e41c6774598194a89f16c7e27dae56140dd5f9fc Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 15 14:18:59 2012 -0700 Provide functions to access arbitrary GPIO pins and vectors This change adds utility functions which allow to read any GPIO pin, as well as a vector of GPIO pin values. As presented, these functions will be available to Sandy Bridge and Ivy Bridge systems only. There is no error checking: trying to read GPIO pin number which exceeds actual number of pins will return zero, trying to read GPIO which is not actually configured as such will return unpredictable value. When reading a GPIO pin vector, the pin numbers are passed in an array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass pointer to array of {4, 2, 15, -1}. Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/southbridge/intel/bd82x6x/gpio.c | 37 ++++++++++++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/gpio.h | 8 +++++++ 2 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c index 598726a..2ba34ea 100644 --- a/src/southbridge/intel/bd82x6x/gpio.c +++ b/src/southbridge/intel/bd82x6x/gpio.c @@ -25,6 +25,8 @@ #include "pch.h" #include "gpio.h" +#define MAX_GPIO_NUMBER 75 /* zero based */ + void setup_pch_gpios(const struct pch_gpio_map *gpio) { u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; @@ -63,3 +65,38 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) if (gpio->set3.reset) outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3); } + +int get_gpio(int gpio_num) +{ + static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48}; + u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + int index, bit; + + if (gpio_num > MAX_GPIO_NUMBER) + return 0; /* Just ignore wrong gpio numbers. */ + + index = gpio_num / 32; + bit = gpio_num % 32; + + return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1; +} + +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array) +{ + int gpio; + unsigned bitmask = 1; + unsigned vector = 0; + + while (bitmask && + ((gpio = *gpio_num_array++) != -1)) { + vector <<= 1; + if (get_gpio(gpio)) + vector |= bitmask; + bitmask <<= 1; + } + return vector; +} diff --git a/src/southbridge/intel/bd82x6x/gpio.h b/src/southbridge/intel/bd82x6x/gpio.h index 214947f..44e808a 100644 --- a/src/southbridge/intel/bd82x6x/gpio.h +++ b/src/southbridge/intel/bd82x6x/gpio.h @@ -150,4 +150,12 @@ struct pch_gpio_map { /* Configure GPIOs with mainboard provided settings */ void setup_pch_gpios(const struct pch_gpio_map *gpio); +/* get GPIO pin value */ +int get_gpio(int gpio_num); +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array); + #endif

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Patch set updated for coreboot: b972fec Add EM100 mode to Intel Firmware Descriptor tool
by Patrick Georgi 24 May '12

24 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1039 -gerrit commit b972fecf8b37384fa75de7e5d1e33827fce8b675 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 11 15:53:43 2012 -0700 Add EM100 mode to Intel Firmware Descriptor tool To avoid having two copies for every firmware descriptor (one for EM100 use and one for real SPI flash use), add an EM100 mode to ifdtool that allows to "dumb down" a fast image to the settings required for the EM100 to work. Change-Id: I0ed989f0a49316bc63d8627cb5d4bd988ae7a103 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/ifdtool/ifdtool.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++- util/ifdtool/ifdtool.h | 9 +++++++ 2 files changed, 67 insertions(+), 2 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 8c1077c..e78ac60 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -152,16 +152,52 @@ static void decode_spi_frequency(unsigned int freq) } } +static void decode_component_density(unsigned int density) +{ + switch (density) { + case COMPONENT_DENSITY_512KB: + printf("512KB"); + break; + case COMPONENT_DENSITY_1MB: + printf("1MB"); + break; + case COMPONENT_DENSITY_2MB: + printf("2MB"); + break; + case COMPONENT_DENSITY_4MB: + printf("4MB"); + break; + case COMPONENT_DENSITY_8MB: + printf("8MB"); + break; + case COMPONENT_DENSITY_16MB: + printf("16MB"); + break; + default: + printf("unknown<%x>MB", density); + } +} + static void dump_fcba(fcba_t * fcba) { printf("\nFound Component Section\n"); printf("FLCOMP 0x%08x\n", fcba->flcomp); + printf(" Dual Output Fast Read Support: %ssupported\n", + (fcba->flcomp & (1 << 30))?"":"not "); printf(" Read ID/Read Status Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 27) & 7); printf("\n Write/Erase Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 24) & 7); printf("\n Fast Read Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 21) & 7); + printf("\n Fast Read Support: %ssupported", + (fcba->flcomp & (1 << 20))?"":"not "); + printf("\n Read Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 17) & 7); + printf("\n Component 2 Density: "); + decode_component_density((fcba->flcomp >> 3) & 7); + printf("\n Component 1 Density: "); + decode_component_density(fcba->flcomp & 7); printf("\n"); printf("FLILL 0x%08x\n", fcba->flill); printf("FLPB 0x%08x\n", fcba->flpb); @@ -303,6 +339,15 @@ static void set_spi_frequency(char *filename, char *image, int size, write_image(filename, image, size); } +static void set_em100_mode(char *filename, char *image, int size) +{ + fdbar_t *fdb = find_fd(image, size); + fcba_t *fcba = (fcba_t *) (image + (((fdb->flmap0) & 0xff) << 4)); + + fcba->flcomp &= ~(1 << 30); + set_spi_frequency(filename, image, size, SPI_FREQUENCY_20MHZ); +} + void inject_region(char *filename, char *image, int size, int region_type, char *region_fname) { @@ -389,6 +434,8 @@ static void print_usage(const char *name) " -x | --extract: extract intel fd modules\n" " -i | --inject <region>:<module> inject file <module> into region <region>\n" " -s | --spifreq <20|33|50> set the SPI frequency\n" + " -e | --em100 set SPI frequency to 20MHz and disable\n" + " Dual Output Fast Read Support\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n" @@ -399,6 +446,7 @@ int main(int argc, char *argv[]) { int opt, option_index = 0; int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0; + int mode_em100 = 0; char *region_type_string = NULL, *region_fname = NULL; int region_type = -1, inputfreq = 0; enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ; @@ -408,12 +456,13 @@ int main(int argc, char *argv[]) {"extract", 0, NULL, 'x'}, {"inject", 1, NULL, 'i'}, {"spifreq", 1, NULL, 's'}, + {"em100", 0, NULL, 'e'}, {"version", 0, NULL, 'v'}, {"help", 0, NULL, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "dxi:s:vh?", + while ((opt = getopt_long(argc, argv, "dxi:s:evh?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -473,6 +522,9 @@ int main(int argc, char *argv[]) } mode_spifreq = 1; break; + case 'e': + mode_em100 = 1; + break; case 'v': print_version(); exit(EXIT_SUCCESS); @@ -492,7 +544,8 @@ int main(int argc, char *argv[]) exit(EXIT_FAILURE); } - if ((mode_dump + mode_extract + mode_inject + mode_spifreq) == 0) { + if ((mode_dump + mode_extract + mode_inject + mode_spifreq + + mode_em100) == 0) { fprintf(stderr, "You need to specify a mode.\n\n"); print_usage(argv[0]); exit(EXIT_FAILURE); @@ -545,6 +598,9 @@ int main(int argc, char *argv[]) if (mode_spifreq) set_spi_frequency(filename, image, size, spifreq); + if (mode_em100) + set_em100_mode(filename, image, size); + free(image); return 0; diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 0571534..31361df 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -26,6 +26,15 @@ enum spi_frequency { SPI_FREQUENCY_50MHZ = 4, }; +enum component_density { + COMPONENT_DENSITY_512KB = 0, + COMPONENT_DENSITY_1MB = 1, + COMPONENT_DENSITY_2MB = 2, + COMPONENT_DENSITY_4MB = 3, + COMPONENT_DENSITY_8MB = 4, + COMPONENT_DENSITY_16MB = 5, +}; + // flash descriptor typedef struct { uint32_t flvalsig;

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Patch set updated for coreboot: 813532b chromeos: Fix compilation of coreboot-utils package
by Patrick Georgi 24 May '12

24 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1038 -gerrit commit 813532b8352bd643fb507c472d518fafebf1edfe Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 11 12:58:11 2012 -0700 chromeos: Fix compilation of coreboot-utils package The ChromeOS build system provides a set of CXXFLAGS, however those do not contain -DCOMPACT. This breaks the compilation of cbfstool in coreboot-utils. This fix overrides CXXFLAGS so that coreboot-utils compiles again. Change-Id: If9495bdd815fe2cdaeba5386afa953558742467b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbfstool/Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index 0b61342..7d667f8 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -3,7 +3,7 @@ obj ?= $(shell pwd) HOSTCXX ?= g++ HOSTCC ?= gcc CFLAGS ?= -g -Wall -CXXFLAGS ?=-DCOMPACT $(CFLAGS) +CXXFLAGS +=-DCOMPACT $(CFLAGS) LDFLAGS ?= -g BINARY:=$(obj)/cbfstool

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Patch set updated for coreboot: cb5e566 Converted the FRAMEBUFFER_VESA_MODE to a choice.
by Patrick Georgi 24 May '12

24 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1036 -gerrit commit cb5e566eb996dac15b34d56dc4982d8c094260ac Author: Steve Goodrich <steve.goodrich(a)se-eng.com> Date: Fri May 18 11:18:47 2012 -0600 Converted the FRAMEBUFFER_VESA_MODE to a choice. Being a diligent soul, I changed the "enter a numeric value for the mode you want" option to a choice of common modes. New modes can be added quite easily. Change-Id: I8cf4572c2d36ced6549541ec173c0c02d8eaca4a Signed-off-by: Steve Goodrich <steve.goodrich(a)se-eng.com> --- src/Kconfig | 129 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 files changed, 122 insertions(+), 7 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index a5a0f00..717146d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -151,7 +151,7 @@ config INCLUDE_CONFIG_FILE coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, offset 0x0 Alignment: 64 bytes - + Name Offset Type Size cmos_layout.bin 0x0 cmos layout 1159 fallback/romstage 0x4c0 stage 339756 @@ -615,16 +615,131 @@ config FRAMEBUFFER_SET_VESA_MODE help Set VESA framebuffer mode (needed for bootsplash) -# TODO: Turn this into a "choice". -config FRAMEBUFFER_VESA_MODE +choice prompt "VESA framebuffer video mode" - hex - default 0x117 + default FRAMEBUFFER_VESA_MODE_117 depends on FRAMEBUFFER_SET_VESA_MODE help This option sets the resolution used for the coreboot framebuffer (and - bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will - some day make this a "choice". + bootsplash screen). + +config FRAMEBUFFER_VESA_MODE_100 + bool "640x400 256-color" + +config FRAMEBUFFER_VESA_MODE_101 + bool "640x480 256-color" + +config FRAMEBUFFER_VESA_MODE_102 + bool "800x600 16-color" + +config FRAMEBUFFER_VESA_MODE_103 + bool "800x600 256-color" + +config FRAMEBUFFER_VESA_MODE_104 + bool "1024x768 16-color" + +config FRAMEBUFFER_VESA_MODE_105 + bool "1024x7686 256-color" + +config FRAMEBUFFER_VESA_MODE_106 + bool "1280x1024 16-color" + +config FRAMEBUFFER_VESA_MODE_107 + bool "1280x1024 256-color" + +config FRAMEBUFFER_VESA_MODE_108 + bool "80x60 text" + +config FRAMEBUFFER_VESA_MODE_109 + bool "132x25 text" + +config FRAMEBUFFER_VESA_MODE_10A + bool "132x43 text" + +config FRAMEBUFFER_VESA_MODE_10B + bool "132x50 text" + +config FRAMEBUFFER_VESA_MODE_10C + bool "132x60 text" + +config FRAMEBUFFER_VESA_MODE_10D + bool "320x200 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_10E + bool "320x200 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_10F + bool "320x200 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_110 + bool "640x480 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_111 + bool "640x480 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_112 + bool "640x480 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_113 + bool "800x600 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_114 + bool "800x600 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_115 + bool "800x600 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_116 + bool "1024x768 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_117 + bool "1024x768 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_118 + bool "1024x768 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_119 + bool "1280x1024 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_11A + bool "1280x1024 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_11B + bool "1280x1024 16.8M-color (8:8:8)" + +endchoice + +# Map the config names to an integer (KB). +config FRAMEBUFFER_VESA_MODE + hex + default 0x100 if FRAMEBUFFER_VESA_MODE_100 + default 0x101 if FRAMEBUFFER_VESA_MODE_101 + default 0x102 if FRAMEBUFFER_VESA_MODE_102 + default 0x103 if FRAMEBUFFER_VESA_MODE_103 + default 0x104 if FRAMEBUFFER_VESA_MODE_104 + default 0x105 if FRAMEBUFFER_VESA_MODE_105 + default 0x106 if FRAMEBUFFER_VESA_MODE_106 + default 0x107 if FRAMEBUFFER_VESA_MODE_107 + default 0x108 if FRAMEBUFFER_VESA_MODE_108 + default 0x109 if FRAMEBUFFER_VESA_MODE_109 + default 0x10A if FRAMEBUFFER_VESA_MODE_10A + default 0x10B if FRAMEBUFFER_VESA_MODE_10B + default 0x10C if FRAMEBUFFER_VESA_MODE_10C + default 0x10D if FRAMEBUFFER_VESA_MODE_10D + default 0x10E if FRAMEBUFFER_VESA_MODE_10E + default 0x10F if FRAMEBUFFER_VESA_MODE_10F + default 0x110 if FRAMEBUFFER_VESA_MODE_110 + default 0x111 if FRAMEBUFFER_VESA_MODE_111 + default 0x112 if FRAMEBUFFER_VESA_MODE_112 + default 0x113 if FRAMEBUFFER_VESA_MODE_113 + default 0x114 if FRAMEBUFFER_VESA_MODE_114 + default 0x115 if FRAMEBUFFER_VESA_MODE_115 + default 0x116 if FRAMEBUFFER_VESA_MODE_116 + default 0x117 if FRAMEBUFFER_VESA_MODE_117 + default 0x118 if FRAMEBUFFER_VESA_MODE_118 + default 0x119 if FRAMEBUFFER_VESA_MODE_119 + default 0x11A if FRAMEBUFFER_VESA_MODE_11A + default 0x11B if FRAMEBUFFER_VESA_MODE_11B config FRAMEBUFFER_KEEP_VESA_MODE prompt "Keep VESA framebuffer"

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Patch set updated for coreboot: b071aa2 abuild: Disable abuild-level parallelism for now
by Patrick Georgi 24 May '12

24 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1037 -gerrit commit b071aa230fe252af638aed7d0bfc979cb914b93e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon May 21 20:10:04 2012 +0200 abuild: Disable abuild-level parallelism for now It still failed because make touches files it isn't supposed to touch. Change-Id: I5a6ceaa9d5da212c1e34b121cf39fa9d27964747 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/abuild/abuild | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 481fbc2..65d9cea 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -309,6 +309,7 @@ function build_target HOSTCC='gcc' printf "Building $VENDOR/$MAINBOARD; " + mkdir -p $TOP/$TARGET/${VENDOR}_${MAINBOARD} XMLFILE=$TOP/$TARGET/${VENDOR}_${MAINBOARD}/abuild.xml xml "<mainboard>" @@ -606,12 +607,12 @@ USE_XARGS=0 if [ "$cpus" != "1" ]; then if [ "$target" = "" ]; then # Test if xargs supports the non-standard -P flag - echo | xargs -P 0$cpus -n 1 echo 2>/dev/null >/dev/null && USE_XARGS=1 + # FIXME: disabled until we managed to eliminate all the make(1) quirks + echo | xargs -P 0$cpus -n 1 echo 2>/dev/null >/dev/null # && USE_XARGS=1 fi fi if [ "$USE_XARGS" = "0" ]; then -export MAKEFLAGS="-j $cpus" build_all_targets() { for VENDOR in $( vendors ); do @@ -673,6 +674,7 @@ if [ "$target" != "" ]; then else build_all_targets rm -f $REAL_XMLFILE + XMLFILE=$REAL_XMLFILE xml '<?xml version="1.0" encoding="utf-8"?>' xml '<abuild>'

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New patch to review for coreboot: 2f5cfcc ChromeOS: Remove remnants of FDT support
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1052 -gerrit commit 2f5cfccdbbf588e1a6243080d357cc73cc20fb88 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 14:20:18 2012 -0700 ChromeOS: Remove remnants of FDT support Originally, on ChromeBooks, coreboot would provide a modified u-boot device tree (FDT) to u-boot in CBMEM. However, u-boot can now create all the information it needs from the coreboot table and add it to its device tree itself. This means we can drop this (anyways unused) code. Change-Id: I4ab20bbb8525e7349b18764aa202bbe81958d06a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/vendorcode/google/chromeos/gnvs.c | 42 --------------------------------- src/vendorcode/google/chromeos/gnvs.h | 1 - 2 files changed, 0 insertions(+), 43 deletions(-) diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 6b545f4..024dbf8 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -34,48 +34,6 @@ void chromeos_init_vboot(chromeos_acpi_t *chromeos) memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh)); } -void chromeos_set_vboot_data_ptr(void *blob) -{ - /* This code has to be rewritten to pass the vboot table - * pointer through the coreboot table instead of the - * FDT, since FDT support was rejected upstream. For now - * just make the code available for reference. - */ -#if 0 // CONFIG_ADD_FDT - int node_offset, addr_cell_len; - const u32 *cell; - uintptr_t table_addr = (uintptr_t)vboot_data; - u32 table_addr32; - u64 table_addr64; - void *table_ptr; - - cell = fdt_getprop(blob, 0, "#address-cells", NULL); - if (cell && *cell == 2) { - addr_cell_len = 8; - table_addr64 = cpu_to_fdt64(table_addr); - table_ptr = &table_addr64; - } else { - addr_cell_len = 4; - table_addr32 = cpu_to_fdt32(table_addr); - table_ptr = &table_addr32; - } - - node_offset = fdt_path_offset(blob, "/chromeos-config"); - if (node_offset < 0) { - printk(BIOS_ERR, - "Couldn't find /chromeos-config in the fdt.\n"); - return; - } - - if (fdt_setprop(blob, node_offset, "gnvs-vboot-table", - table_ptr, addr_cell_len) < 0) { - printk(BIOS_ERR, "Couldn't set gnvs-vboot-table.\n"); - } -#else - printk(BIOS_ERR, "Can't set gnvs-vboot-table.\n"); -#endif -} - void chromeos_set_me_hash(u32 *hash, int len) { if ((len*sizeof(u32)) > sizeof(vboot_data->mehh)) diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 36922ba..6dd740f 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -63,7 +63,6 @@ typedef struct { extern chromeos_acpi_t *vboot_data; void chromeos_init_vboot(chromeos_acpi_t *chromeos); -void chromeos_set_vboot_data_ptr(void *); void chromeos_set_me_hash(u32*, int); #endif

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New patch to review for coreboot: 941d3ed Sandybridge: Remove remnants of FDT support from MRC cache code
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1051 -gerrit commit 941d3ed66a17dc667ade5cc5bfaeee3207d0eeee Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 14:16:47 2012 -0700 Sandybridge: Remove remnants of FDT support from MRC cache code Originally, ChromeBooks would get the offset of the MRC cache from an entry in the u-boot device tree. Not everyone wants to use u-boot on Sandybridge systems, however. Since the new code (based on Kconfig) is now fully working, we can drop the u-boot device tree remnants. Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/mrccache.c | 80 ++++---------------------- 1 files changed, 11 insertions(+), 69 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index aad2b91..d774ff0 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -28,19 +28,6 @@ #include "sandybridge.h" #include <spi.h> #include <spi_flash.h> -/* Using the FDT FMAP for finding the MRC cache area requires including FDT - * support in coreboot, which we would like to avoid. There are a number of - * options: - * - Have each mainboard Kconfig supply a hard-coded offset - * - For ChromeOS devices: implement native FMAP - * - For non-ChromeOS devices: use CBFS - * For now let's leave this code in here until the issue is sorted out in - * a way that works for everyone. - */ -#undef USE_FDT_FMAP_FOR_MRC_CACHE -#ifdef USE_FDT_FMAP_FOR_MRC_CACHE -#include <fdt/libfdt.h> -#endif struct mrc_data_container *next_mrc_block(struct mrc_data_container *mrc_cache) { @@ -61,64 +48,19 @@ int is_mrc_cache(struct mrc_data_container *mrc_cache) return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); } +/* Right now, the offsets for the MRC cache area are hard-coded in the + * northbridge Kconfig. In order to make this more flexible, there are + * a number of options: + * - Have each mainboard Kconfig supply a hard-coded offset + * - For ChromeOS devices: implement native FMAP + * - For non-ChromeOS devices: use CBFS + */ u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { - u8 *mrc_region; - u32 region_size; -#ifdef USE_FDT_FMAP_FOR_MRC_CACHE - u32 *data; - const struct fdt_header *fdt_header; - const struct fdt_property *fdtp; - int offset, len; - const char *compatible = "chromeos,flashmap"; - const char *subnode = "rw-mrc-cache"; - const char *property = "reg"; - u64 flashrom_base = 0; - - fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT); - - if (!fdt_header) { - printk(BIOS_ERR, "%s: no FDT found!\n", __func__); - return 0; - } - - offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible); - if (offset < 0) { - printk(BIOS_ERR, "%s: no %s node found!\n", - __func__, compatible); - return 0; - } - - if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) { - printk(BIOS_ERR, "%s: no base address in node name!\n", - __func__); - return 0; - } - - offset = fdt_subnode_offset(fdt_header, offset, subnode); - if (offset < 0) { - printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode); - return 0; - } - - fdtp = fdt_get_property(fdt_header, offset, property, &len); - if (!fdtp || (len != 8)) { - printk(BIOS_ERR, "%s: property %s at %p, len %d!\n", - __func__, property, fdtp, len); - return 0; - } - - data = (u32 *)fdtp->data; - - // Calculate actual address of the MRC cache in memory - region_size = fdt32_to_cpu(data[1]); - mrc_region = (u8*)((unsigned long)flashrom_base + fdt32_to_cpu(data[0])); -#else - region_size = CONFIG_MRC_CACHE_SIZE; - mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); -#endif - *mrc_region_ptr = (struct mrc_data_container *)mrc_region; + u32 region_size = CONFIG_MRC_CACHE_SIZE; + *mrc_region_ptr = (struct mrc_data_container *) + (CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); return region_size; } @@ -182,7 +124,7 @@ struct mrc_data_container *find_current_mrc_cache(void) entry_id++; mrc_cache = mrc_next; mrc_next = next_mrc_block(mrc_cache); - /* Stay in the mrcdata region defined in fdt */ + /* Stay in the mrc data region */ if ((void*)mrc_next >= (void*)(mrc_region + region_size)) break; }

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New patch to review for coreboot: 4ca567a Fix full reset for Ivy Bridge platforms
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1050 -gerrit commit 4ca567ab4053c32aae87bd3cfd0a6e500d3dddb8 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 17 17:21:27 2012 -0700 Fix full reset for Ivy Bridge platforms Experiments have shown that writing plain value of 6 at byte io address of 0xcf9 causes the systems to reset and reboot reliably. Change-Id: Ie900e4b4014cded868647372b027918b7ff72578 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/southbridge/intel/bd82x6x/reset.c | 9 --------- 1 files changed, 0 insertions(+), 9 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c index 29b69ff..5324142 100644 --- a/src/southbridge/intel/bd82x6x/reset.c +++ b/src/southbridge/intel/bd82x6x/reset.c @@ -26,16 +26,7 @@ void soft_reset(void) outb(0x04, 0xcf9); } -#if 0 void hard_reset(void) { - /* Try rebooting through port 0xcf9. */ - outb((1 << 2) | (1 << 1), 0xcf9); -} -#endif - -void hard_reset(void) -{ - outb(0x02, 0xcf9); outb(0x06, 0xcf9); }

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New patch to review for coreboot: 61899d3 Provide functions to access arbitrary GPIO pins and vectors
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1049 -gerrit commit 61899d3c0595c73c0e2502a5af2215682dc28144 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 15 14:18:59 2012 -0700 Provide functions to access arbitrary GPIO pins and vectors This change adds utility functions which allow to read any GPIO pin, as well as a vector of GPIO pin values. As presented, these functions will be available to Sandy Bridge and Ivy Bridge systems only. There is no error checking: trying to read GPIO pin number which exceeds actual number of pins will return zero, trying to read GPIO which is not actually configured as such will return unpredictable value. When reading a GPIO pin vector, the pin numbers are passed in an array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass pointer to array of {4, 2, 15, -1}. Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/southbridge/intel/bd82x6x/gpio.c | 37 ++++++++++++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/gpio.h | 8 +++++++ 2 files changed, 45 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c index 598726a..2ba34ea 100644 --- a/src/southbridge/intel/bd82x6x/gpio.c +++ b/src/southbridge/intel/bd82x6x/gpio.c @@ -25,6 +25,8 @@ #include "pch.h" #include "gpio.h" +#define MAX_GPIO_NUMBER 75 /* zero based */ + void setup_pch_gpios(const struct pch_gpio_map *gpio) { u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; @@ -63,3 +65,38 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio) if (gpio->set3.reset) outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3); } + +int get_gpio(int gpio_num) +{ + static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48}; + u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + int index, bit; + + if (gpio_num > MAX_GPIO_NUMBER) + return 0; /* Just ignore wrong gpio numbers. */ + + index = gpio_num / 32; + bit = gpio_num % 32; + + return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1; +} + +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array) +{ + int gpio; + unsigned bitmask = 1; + unsigned vector = 0; + + while (bitmask && + ((gpio = *gpio_num_array++) != -1)) { + vector <<= 1; + if (get_gpio(gpio)) + vector |= bitmask; + bitmask <<= 1; + } + return vector; +} diff --git a/src/southbridge/intel/bd82x6x/gpio.h b/src/southbridge/intel/bd82x6x/gpio.h index 214947f..44e808a 100644 --- a/src/southbridge/intel/bd82x6x/gpio.h +++ b/src/southbridge/intel/bd82x6x/gpio.h @@ -150,4 +150,12 @@ struct pch_gpio_map { /* Configure GPIOs with mainboard provided settings */ void setup_pch_gpios(const struct pch_gpio_map *gpio); +/* get GPIO pin value */ +int get_gpio(int gpio_num); +/* + * get a number comprised of multiple GPIO values. gpio_num_array points to + * the array of gpio pin numbers to scan, terminated by -1. + */ +unsigned get_gpios(const int *gpio_num_array); + #endif

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New patch to review for coreboot: 5434dcc Add support for Panther Point to SPI driver
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1048 -gerrit commit 5434dcce2c63e3a0cec44ab26da170a1be02b8b4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 11:18:35 2012 -0700 Add support for Panther Point to SPI driver Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/device/pci_ids.h | 2 ++ src/southbridge/intel/bd82x6x/spi.c | 29 ++++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 1765293..4ebd572 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2504,6 +2504,8 @@ #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5d #define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc /* Intel 82801E (C-ICH) */ diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 95fbfb9..ccc530d 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -286,11 +286,24 @@ void spi_free_slave(struct spi_slave *_slave) free(slave); } -static inline int spi_is_cougarpoint_lpc(uint16_t device_id) +/* + * Check if this device ID matches one of supported Intel PCH devices. + * + * Return the ICH version if there is a match, or zero otherwise. + */ +static inline int get_ich_version(uint16_t device_id) { - return device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX; -}; + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) + return 7; + + if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || + (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) + return 9; + + return 0; +} void spi_init(void) { @@ -313,11 +326,9 @@ void spi_init(void) return; } - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) { - ich_version = 7; - } else if (spi_is_cougarpoint_lpc(device_id)) { - ich_version = 9; - } else { + ich_version = get_ich_version(device_id); + + if (!ich_version) { printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n"); return; }

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coreboot May 2012