coreboot May 2012

coreboot@coreboot.org

31 participants
287 discussions

New patch to review for coreboot: 58ba49e Drop config variable CPU_MODEL_INDEX
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1047 -gerrit commit 58ba49e59fd98b84a1267dd1308250e2e0ddcd11 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 11 16:30:54 2012 -0700 Drop config variable CPU_MODEL_INDEX It's only used in the ACPI generator for Sandybridge/Ivybridge CPUs and the code can easily be changed to not rely on any Kconfig magic. Change-Id: Ie2f92edfe8908f7eb2fda3088f77ad22f491ddcf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/model_206ax/Kconfig | 8 -------- src/cpu/intel/model_206ax/acpi.c | 11 ++--------- 2 files changed, 2 insertions(+), 17 deletions(-) diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index c11f21a..d2d4c73 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -36,18 +36,10 @@ if CPU_INTEL_MODEL_206AX config CPU_MODEL_NAME string default "Intel SandyBridge CPU" - - config CPU_MODEL_INDEX - hex - default 0x2a endif if CPU_INTEL_MODEL_306AX config CPU_MODEL_NAME string default "Intel IvyBridge CPU" - - config CPU_MODEL_INDEX - hex - default 0x3a endif diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 1a8ceb7..6153174 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -44,15 +44,8 @@ static int get_cores_per_package(void) if (c.x86 != 6) return 1; - switch (c.x86_model) { - case CONFIG_CPU_MODEL_INDEX: - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - break; - default: - cores = (cpuid_ebx(1) >> 16) & 0xff; - break; - } + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; return cores; }

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New patch to review for coreboot: c73f81e Sandybridge: Fix MRC cache calculation
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1046 -gerrit commit c73f81ecfd6058eaccaf50086298850fefbf5d9d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 11:21:10 2012 -0700 Sandybridge: Fix MRC cache calculation The MRC region is described by Kconfig variables, no further math or parsing is required at this point. Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sandybridge/mrccache.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 5c4c382..aad2b91 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -65,8 +65,8 @@ u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { u8 *mrc_region; u32 region_size; - u32 *data; #ifdef USE_FDT_FMAP_FOR_MRC_CACHE + u32 *data; const struct fdt_header *fdt_header; const struct fdt_property *fdtp; int offset, len; @@ -114,10 +114,8 @@ u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) region_size = fdt32_to_cpu(data[1]); mrc_region = (u8*)((unsigned long)flashrom_base + fdt32_to_cpu(data[0])); #else - data = (u32 *)((void *)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION + 12)); - region_size = CONFIG_MRC_CACHE_SIZE; - mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + be32_to_cpu(data[0])); + mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION); #endif *mrc_region_ptr = (struct mrc_data_container *)mrc_region;

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New patch to review for coreboot: 6bf01cb Reduce default verbosity of SPI flash drivers
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1045 -gerrit commit 6bf01cb29d9a59090affae34724b3220fd19d8cb Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 11:03:29 2012 -0700 Reduce default verbosity of SPI flash drivers Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled. Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/spi/eon.c | 2 ++ src/drivers/spi/macronix.c | 2 ++ src/drivers/spi/spansion.c | 2 ++ src/drivers/spi/stmicro.c | 2 ++ src/drivers/spi/winbond.c | 2 ++ 5 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index b7c0630..7d9bc44 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -85,9 +85,11 @@ static int eon_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 84e79ef..f74eb4f 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -141,9 +141,11 @@ static int macronix_write(struct spi_flash *flash, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index 5479cae..511091b 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -162,9 +162,11 @@ static int spansion_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 9322c06..ccdfa00 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -163,9 +163,11 @@ static int stmicro_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 7b6d105..01644b0 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -130,9 +130,11 @@ static int winbond_write(struct spi_flash *flash, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); if (ret < 0) {

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New patch to review for coreboot: 3a35661 Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1044 -gerrit commit 3a356617fd684e65e968f5737ec258cbec54da9e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 22 15:24:51 2012 -0700 Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled Right now coreboot compilation fails when SPI flash debugging is enabled. Fix it by using the right set of memory functions. Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/spi/spi_flash.c | 1 - src/southbridge/intel/bd82x6x/spi.c | 12 ++++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 2c0f702..0b859f3 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -264,7 +264,6 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, #if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: Got idcodes\n"); - print_buffer(0, idcode, 1, sizeof(idcode), 0); #endif /* count the number of continuation bytes */ diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 2508a96..95fbfb9 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -162,7 +162,7 @@ enum { static u8 readb_(const void *addr) { - u8 v = readb(addr); + u8 v = read8((unsigned long)addr); printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -170,7 +170,7 @@ static u8 readb_(const void *addr) static u16 readw_(const void *addr) { - u16 v = readw(addr); + u16 v = read16((unsigned long)addr); printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -178,7 +178,7 @@ static u16 readw_(const void *addr) static u32 readl_(const void *addr) { - u32 v = readl(addr); + u32 v = read32((unsigned long)addr); printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", v, ((unsigned) addr & 0xffff) - 0xf020); return v; @@ -186,21 +186,21 @@ static u32 readl_(const void *addr) static void writeb_(u8 b, const void *addr) { - writeb(b, addr); + write8((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } static void writew_(u16 b, const void *addr) { - writew(b, addr); + write16((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); } static void writel_(u32 b, const void *addr) { - writel(b, addr); + write32((unsigned long)addr, b); printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", b, ((unsigned) addr & 0xffff) - 0xf020); }

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New patch to review for coreboot: 0a0261a Implement %zu / %zd in printk
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1043 -gerrit commit 0a0261a3840f353ae35d752fadf537d72631149e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 15 13:28:07 2012 -0700 Implement %zu / %zd in printk The SPI drivers from u-boot make heavy use of %zu/%zd (size_t/ssize_t). Implement this in our printk implementation so we get useful output. Change-Id: I91798ff4f28b9c3cd4db204c7ec503596d247dcd Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/console/vtxprintf.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index a370e5f..28c5a60 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -170,7 +170,7 @@ repeat: /* get the conversion qualifier */ qualifier = -1; - if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') { + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt == 'z') { qualifier = *fmt; ++fmt; if (*fmt == 'l') { @@ -218,7 +218,6 @@ repeat: field_width, precision, flags); continue; - case 'n': if (qualifier == 'L') { long long *ip = va_arg(args, long long *); @@ -265,6 +264,8 @@ repeat: num = va_arg(args, unsigned long long); } else if (qualifier == 'l') { num = va_arg(args, unsigned long); + } else if (qualifier == 'z') { + num = va_arg(args, size_t); } else if (qualifier == 'h') { num = (unsigned short) va_arg(args, int); if (flags & SIGN)

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New patch to review for coreboot: c7e6509 Move subsystem IDs to devicetree.cb
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1042 -gerrit commit c7e6509905d5cb11ac611db29c55e19c12cccbda Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 15 12:36:57 2012 -0700 Move subsystem IDs to devicetree.cb A while back coreboot was changed to read the subsystem IDs from devicetree.cb to allow each onboard PCI device to have its own subsystem id. When we originally branched, this was not the case, and the sandybridge/ivybridge mainboards have not been updated yet. Also, drop the subsystem ID from Emerald Lake 2, since it's not a Google device. Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/intel/emeraldlake2/Kconfig | 8 -------- src/mainboard/samsung/lumpy/Kconfig | 8 -------- src/mainboard/samsung/lumpy/devicetree.cb | 1 + src/mainboard/samsung/stumpy/Kconfig | 8 -------- src/mainboard/samsung/stumpy/devicetree.cb | 1 + 5 files changed, 2 insertions(+), 24 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 9e4f347..873d273 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -43,12 +43,4 @@ config VGA_BIOS_FILE string default "pci8086,0166.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 - endif # BOARD_INTEL_EMERALDLAKE2 diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 200edac..0835012 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -44,14 +44,6 @@ config VGA_BIOS_FILE string default "pci8086,0106.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 - config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool default n diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 36af1ca..3e93df4 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -33,6 +33,7 @@ chip northbridge/intel/sandybridge end device pci_domain 0 on + subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index dda3002..18094cf 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -43,14 +43,6 @@ config VGA_BIOS_FILE string default "pci8086,0106.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1ae0 - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0xc000 - config MAINBOARD_POWER_ON_AFTER_POWER_FAIL bool default n diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index f10b283..b59dcb2 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -28,6 +28,7 @@ chip northbridge/intel/sandybridge end device pci_domain 0 on + subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller

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New patch to review for coreboot: 194a9c3 Fix printk types in SPI flash drivers
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1041 -gerrit commit 194a9c36f9a812241baa02a854ba8195f37f7912 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 14 13:52:32 2012 -0700 Fix printk types in SPI flash drivers - use %zu instead of %zd for size_t (%zd is for ssize_t) - use %x instead of %lx for u32 - break some long lines to avoid commit hook trouble Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/drivers/spi/eon.c | 2 +- src/drivers/spi/macronix.c | 6 ++++-- src/drivers/spi/spansion.c | 3 ++- src/drivers/spi/sst.c | 2 +- src/drivers/spi/stmicro.c | 3 ++- src/drivers/spi/winbond.c | 6 +++--- 6 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 4056953..b7c0630 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -86,7 +86,7 @@ static int eon_write(struct spi_flash *flash, cmd[3] = byte_addr; printk(BIOS_SPEW, - "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 130e746..84e79ef 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -141,7 +141,8 @@ static int macronix_write(struct spi_flash *flash, cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0); @@ -165,7 +166,8 @@ static int macronix_write(struct spi_flash *flash, byte_addr = 0; } - printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes @ 0x%lx\n", + printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes @" + " 0x%x\n", len, offset - len); spi_release_bus(flash->spi); diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index a4f370a..5479cae 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -162,7 +162,8 @@ static int spansion_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0); diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index c5bec12..3ca5563 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -194,7 +194,7 @@ sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) ret = sst_byte_write(flash, offset, buf + actual); done: - printk(BIOS_INFO, "SF: SST: program %s %zu bytes @ 0x%lx\n", + printk(BIOS_INFO, "SF: SST: program %s %zu bytes @ 0x%x\n", ret ? "failure" : "success", len, offset - actual); spi_release_bus(flash->spi); diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 8cbdad5..9322c06 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -163,7 +163,8 @@ static int stmicro_write(struct spi_flash *flash, cmd[2] = page_addr; cmd[3] = byte_addr; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n", + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 65818d5..7b6d105 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -130,8 +130,8 @@ static int winbond_write(struct spi_flash *flash, cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; - printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %ld\n", - buf + actual, + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); @@ -155,7 +155,7 @@ static int winbond_write(struct spi_flash *flash, byte_addr = 0; } - printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes @ 0x%lx\n", + printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes @ 0x%x\n", len, offset - len); ret = 0;

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New patch to review for coreboot: 7a0cac1 Fix size_t for certain versions of GCC
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1040 -gerrit commit 7a0cac14ac8891d927978c9c6f9cc22d1f406d4d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 14 13:21:08 2012 -0700 Fix size_t for certain versions of GCC When compiling coreboot with the latest ChromeOS toolchain, GCC complains that some printk calls use %zu in connection with size_t types since it resolves the typedefs to long unsigned int. The problem is solved by using the GCC built-in __SIZE_TYPE__ if it exists and define __SIZE_TYPE__ to long unsigned int otherwise. Change-Id: I449c3d385b5633a05e57204704e981de6e017b86 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/stddef.h | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/include/stddef.h b/src/arch/x86/include/stddef.h index e4fc019..c737be1 100644 --- a/src/arch/x86/include/stddef.h +++ b/src/arch/x86/include/stddef.h @@ -2,7 +2,10 @@ #define I386_STDDEF_H typedef long ptrdiff_t; -typedef unsigned long size_t; +#ifndef __SIZE_TYPE__ +#define __SIZE_TYPE__ long unsigned int +#endif +typedef __SIZE_TYPE__ size_t; typedef long ssize_t; typedef int wchar_t;

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New patch to review for coreboot: a5a2902 Add EM100 mode to Intel Firmware Descriptor tool
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1039 -gerrit commit a5a290269a4f478d2cc40cb40167286262e23cd4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 11 15:53:43 2012 -0700 Add EM100 mode to Intel Firmware Descriptor tool To avoid having two copies for every firmware descriptor (one for EM100 use and one for real SPI flash use), add an EM100 mode to ifdtool that allows to "dumb down" a fast image to the settings required for the EM100 to work. Change-Id: I0ed989f0a49316bc63d8627cb5d4bd988ae7a103 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/ifdtool/ifdtool.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++- util/ifdtool/ifdtool.h | 9 +++++++ 2 files changed, 67 insertions(+), 2 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 8c1077c..e78ac60 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -152,16 +152,52 @@ static void decode_spi_frequency(unsigned int freq) } } +static void decode_component_density(unsigned int density) +{ + switch (density) { + case COMPONENT_DENSITY_512KB: + printf("512KB"); + break; + case COMPONENT_DENSITY_1MB: + printf("1MB"); + break; + case COMPONENT_DENSITY_2MB: + printf("2MB"); + break; + case COMPONENT_DENSITY_4MB: + printf("4MB"); + break; + case COMPONENT_DENSITY_8MB: + printf("8MB"); + break; + case COMPONENT_DENSITY_16MB: + printf("16MB"); + break; + default: + printf("unknown<%x>MB", density); + } +} + static void dump_fcba(fcba_t * fcba) { printf("\nFound Component Section\n"); printf("FLCOMP 0x%08x\n", fcba->flcomp); + printf(" Dual Output Fast Read Support: %ssupported\n", + (fcba->flcomp & (1 << 30))?"":"not "); printf(" Read ID/Read Status Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 27) & 7); printf("\n Write/Erase Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 24) & 7); printf("\n Fast Read Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 21) & 7); + printf("\n Fast Read Support: %ssupported", + (fcba->flcomp & (1 << 20))?"":"not "); + printf("\n Read Clock Frequency: "); + decode_spi_frequency((fcba->flcomp >> 17) & 7); + printf("\n Component 2 Density: "); + decode_component_density((fcba->flcomp >> 3) & 7); + printf("\n Component 1 Density: "); + decode_component_density(fcba->flcomp & 7); printf("\n"); printf("FLILL 0x%08x\n", fcba->flill); printf("FLPB 0x%08x\n", fcba->flpb); @@ -303,6 +339,15 @@ static void set_spi_frequency(char *filename, char *image, int size, write_image(filename, image, size); } +static void set_em100_mode(char *filename, char *image, int size) +{ + fdbar_t *fdb = find_fd(image, size); + fcba_t *fcba = (fcba_t *) (image + (((fdb->flmap0) & 0xff) << 4)); + + fcba->flcomp &= ~(1 << 30); + set_spi_frequency(filename, image, size, SPI_FREQUENCY_20MHZ); +} + void inject_region(char *filename, char *image, int size, int region_type, char *region_fname) { @@ -389,6 +434,8 @@ static void print_usage(const char *name) " -x | --extract: extract intel fd modules\n" " -i | --inject <region>:<module> inject file <module> into region <region>\n" " -s | --spifreq <20|33|50> set the SPI frequency\n" + " -e | --em100 set SPI frequency to 20MHz and disable\n" + " Dual Output Fast Read Support\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n" @@ -399,6 +446,7 @@ int main(int argc, char *argv[]) { int opt, option_index = 0; int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0; + int mode_em100 = 0; char *region_type_string = NULL, *region_fname = NULL; int region_type = -1, inputfreq = 0; enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ; @@ -408,12 +456,13 @@ int main(int argc, char *argv[]) {"extract", 0, NULL, 'x'}, {"inject", 1, NULL, 'i'}, {"spifreq", 1, NULL, 's'}, + {"em100", 0, NULL, 'e'}, {"version", 0, NULL, 'v'}, {"help", 0, NULL, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "dxi:s:vh?", + while ((opt = getopt_long(argc, argv, "dxi:s:evh?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -473,6 +522,9 @@ int main(int argc, char *argv[]) } mode_spifreq = 1; break; + case 'e': + mode_em100 = 1; + break; case 'v': print_version(); exit(EXIT_SUCCESS); @@ -492,7 +544,8 @@ int main(int argc, char *argv[]) exit(EXIT_FAILURE); } - if ((mode_dump + mode_extract + mode_inject + mode_spifreq) == 0) { + if ((mode_dump + mode_extract + mode_inject + mode_spifreq + + mode_em100) == 0) { fprintf(stderr, "You need to specify a mode.\n\n"); print_usage(argv[0]); exit(EXIT_FAILURE); @@ -545,6 +598,9 @@ int main(int argc, char *argv[]) if (mode_spifreq) set_spi_frequency(filename, image, size, spifreq); + if (mode_em100) + set_em100_mode(filename, image, size); + free(image); return 0; diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 0571534..31361df 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -26,6 +26,15 @@ enum spi_frequency { SPI_FREQUENCY_50MHZ = 4, }; +enum component_density { + COMPONENT_DENSITY_512KB = 0, + COMPONENT_DENSITY_1MB = 1, + COMPONENT_DENSITY_2MB = 2, + COMPONENT_DENSITY_4MB = 3, + COMPONENT_DENSITY_8MB = 4, + COMPONENT_DENSITY_16MB = 5, +}; + // flash descriptor typedef struct { uint32_t flvalsig;

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New patch to review for coreboot: c369ce6 chromeos: Fix compilation of coreboot-utils package
by Stefan Reinauer 24 May '12

24 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1038 -gerrit commit c369ce65cc2d889cc8042656f45a38a373b531b7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 11 12:58:11 2012 -0700 chromeos: Fix compilation of coreboot-utils package The ChromeOS build system provides a set of CXXFLAGS, however those do not contain -DCOMPACT. This breaks the compilation of cbfstool in coreboot-utils. This fix overrides CXXFLAGS so that coreboot-utils compiles again. Change-Id: If9495bdd815fe2cdaeba5386afa953558742467b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/cbfstool/Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile index 0b61342..7d667f8 100644 --- a/util/cbfstool/Makefile +++ b/util/cbfstool/Makefile @@ -3,7 +3,7 @@ obj ?= $(shell pwd) HOSTCXX ?= g++ HOSTCC ?= gcc CFLAGS ?= -g -Wall -CXXFLAGS ?=-DCOMPACT $(CFLAGS) +CXXFLAGS +=-DCOMPACT $(CFLAGS) LDFLAGS ?= -g BINARY:=$(obj)/cbfstool

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coreboot May 2012