coreboot May 2012

coreboot@coreboot.org

31 participants
287 discussions

[AMD] Persimmon
by martin.meng＠mic.com.tw 23 May '12

23 May '12

Hello all, I check out coreboot and build and run persimmon project via menuconfig, Mainborad: AMD Mainboard Model: Persimon FlashSize: 4MB But it always show 0x00 on my PCI debug card. I do not know its 80 port default path is LPC or PCI, so I have tried to route 80 port to PCI in entry32.inc (src/cpu/x86/32bit), But it seem not work. Can someone help me to solve this issue, Thanks. Here is my configuration: NorthBridge: AMD family 14 SouthBridge: SB800 SIO: FNTEK F81865

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Add mainboard supermicro x7db8
by manasa gv 23 May '12

23 May '12

From: Manasa GV <manasa671989(a)gmail.com> This patch is to file x7db8.Build(Jenkins) results failed for patch set1 in patch493.Test results showing error. So i added cmos.layout file.Later i done abuild,then also it is showing errors. Errors are- need to add smbus.c, smbus.h ,early_setup.c file for Southbridge i63xx. So please suggest me to add these files. Signed-off-by: manasa gv<manasa671989(a)gmail.com> --- src/mainboard/supermicro/x7db8/cmos.layout | 72 ++++++++++++++++++++++++++++ 1 files changed, 72 insertions(+), 0 deletions(-) create mode 100644 src/mainboard/supermicro/x7db8/cmos.layout diff --git a/src/mainboard/supermicro/x7db8/cmos.layout b/src/mainboard/supermicro/x7db8/cmos.layout new file mode 100644 index 0000000..9d22590 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/cmos.layout @@ -0,0 +1,72 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM + +checksums + +checksum 392 1007 1008 -- 1.7.7.6

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Re: [coreboot] Adding Supermicro X9SCV-QV4
by Mike Bishton 22 May '12

22 May '12

Nachiketh, That board is very similar to the Emerald Lake (2) CRB which was recently added to coreboot, I would start there. This board is special because even though it's marketed as a server motherboard, it is actually based on the mobile platform. Hope it helps, Mike On 5/16/2012 11:25 AM, Nachiketh G wrote: > Hi, > If there is any particular board supported by coreboot which I can use > as reference for Intel QM67 chip set with the Intel core i5/i7 > processor families.... please let me know. I can use it as a reference > to build the support for the Supermicro motherboard that I have. > Thanks & Regards, > Nachiketh > > On Fri, May 11, 2012 at 10:19 AM, Peter Stuge <peter(a)stuge.se > <mailto:peter@stuge.se>> wrote: > > Nachiketh G wrote: > > I wanted to know if there is any existing code base > > No, I don't believe there is. > > > //Peter > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > http://www.coreboot.org/mailman/listinfo/coreboot > > > >

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New patch to review for coreboot: ef19ebf abuild: Disable abuild-level parallelism for now
by Patrick Georgi 21 May '12

21 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1037 -gerrit commit ef19ebfb6133089012cf505018afbafbea7cdb25 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon May 21 20:10:04 2012 +0200 abuild: Disable abuild-level parallelism for now It still failed because make touches files it isn't supposed to touch. Change-Id: I5a6ceaa9d5da212c1e34b121cf39fa9d27964747 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/abuild/abuild | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 481fbc2..3639cc6 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -606,12 +606,12 @@ USE_XARGS=0 if [ "$cpus" != "1" ]; then if [ "$target" = "" ]; then # Test if xargs supports the non-standard -P flag - echo | xargs -P 0$cpus -n 1 echo 2>/dev/null >/dev/null && USE_XARGS=1 + # FIXME: disabled until we managed to eliminate all the make(1) quirks + echo | xargs -P 0$cpus -n 1 echo 2>/dev/null >/dev/null # && USE_XARGS=1 fi fi if [ "$USE_XARGS" = "0" ]; then -export MAKEFLAGS="-j $cpus" build_all_targets() { for VENDOR in $( vendors ); do

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Patch merged into coreboot/master: a5a5432 Fix Persimmon build without S3.
by gerrit＠coreboot.org 21 May '12

21 May '12

the following patch was just integrated into master: commit a5a543259f455c6d99cf1a8e69cd12cb4bafee20 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue May 15 16:08:24 2012 -0600 Fix Persimmon build without S3. In the heap function, only check for S3 check when it is built in with CONFIG_HAVE_ACPI_RESUME. Change-Id: I439275a4e1b7b446b499bcf90c925785a14b980d Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed May 16 00:37:02 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu May 17 20:08:20 2012, giving +2 See http://review.coreboot.org/1034 for details. -gerrit

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New patch to review for coreboot: 52e4920 Converted the FRAMEBUFFER_VESA_MODE to a choice.
by Steve Goodrich 21 May '12

21 May '12

Steve Goodrich (steve.goodrich(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1036 -gerrit commit 52e492016ac13ac1190cb3e70975cfedde5e87a4 Author: Steve Goodrich <steve.goodrich(a)se-eng.com> Date: Fri May 18 11:18:47 2012 -0600 Converted the FRAMEBUFFER_VESA_MODE to a choice. Being a diligent soul, I changed the "enter a numeric value for the mode you want" option to a choice of common modes. New modes can be added quite easily. Change-Id: I8cf4572c2d36ced6549541ec173c0c02d8eaca4a Signed-off-by: Steve Goodrich <steve.goodrich(a)se-eng.com> --- src/Kconfig | 129 +++++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 files changed, 122 insertions(+), 7 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index a5a0f00..717146d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -151,7 +151,7 @@ config INCLUDE_CONFIG_FILE coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, offset 0x0 Alignment: 64 bytes - + Name Offset Type Size cmos_layout.bin 0x0 cmos layout 1159 fallback/romstage 0x4c0 stage 339756 @@ -615,16 +615,131 @@ config FRAMEBUFFER_SET_VESA_MODE help Set VESA framebuffer mode (needed for bootsplash) -# TODO: Turn this into a "choice". -config FRAMEBUFFER_VESA_MODE +choice prompt "VESA framebuffer video mode" - hex - default 0x117 + default FRAMEBUFFER_VESA_MODE_117 depends on FRAMEBUFFER_SET_VESA_MODE help This option sets the resolution used for the coreboot framebuffer (and - bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will - some day make this a "choice". + bootsplash screen). + +config FRAMEBUFFER_VESA_MODE_100 + bool "640x400 256-color" + +config FRAMEBUFFER_VESA_MODE_101 + bool "640x480 256-color" + +config FRAMEBUFFER_VESA_MODE_102 + bool "800x600 16-color" + +config FRAMEBUFFER_VESA_MODE_103 + bool "800x600 256-color" + +config FRAMEBUFFER_VESA_MODE_104 + bool "1024x768 16-color" + +config FRAMEBUFFER_VESA_MODE_105 + bool "1024x7686 256-color" + +config FRAMEBUFFER_VESA_MODE_106 + bool "1280x1024 16-color" + +config FRAMEBUFFER_VESA_MODE_107 + bool "1280x1024 256-color" + +config FRAMEBUFFER_VESA_MODE_108 + bool "80x60 text" + +config FRAMEBUFFER_VESA_MODE_109 + bool "132x25 text" + +config FRAMEBUFFER_VESA_MODE_10A + bool "132x43 text" + +config FRAMEBUFFER_VESA_MODE_10B + bool "132x50 text" + +config FRAMEBUFFER_VESA_MODE_10C + bool "132x60 text" + +config FRAMEBUFFER_VESA_MODE_10D + bool "320x200 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_10E + bool "320x200 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_10F + bool "320x200 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_110 + bool "640x480 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_111 + bool "640x480 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_112 + bool "640x480 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_113 + bool "800x600 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_114 + bool "800x600 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_115 + bool "800x600 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_116 + bool "1024x768 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_117 + bool "1024x768 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_118 + bool "1024x768 16.8M-color (8:8:8)" + +config FRAMEBUFFER_VESA_MODE_119 + bool "1280x1024 32k-color (1:5:5:5)" + +config FRAMEBUFFER_VESA_MODE_11A + bool "1280x1024 64k-color (5:6:5)" + +config FRAMEBUFFER_VESA_MODE_11B + bool "1280x1024 16.8M-color (8:8:8)" + +endchoice + +# Map the config names to an integer (KB). +config FRAMEBUFFER_VESA_MODE + hex + default 0x100 if FRAMEBUFFER_VESA_MODE_100 + default 0x101 if FRAMEBUFFER_VESA_MODE_101 + default 0x102 if FRAMEBUFFER_VESA_MODE_102 + default 0x103 if FRAMEBUFFER_VESA_MODE_103 + default 0x104 if FRAMEBUFFER_VESA_MODE_104 + default 0x105 if FRAMEBUFFER_VESA_MODE_105 + default 0x106 if FRAMEBUFFER_VESA_MODE_106 + default 0x107 if FRAMEBUFFER_VESA_MODE_107 + default 0x108 if FRAMEBUFFER_VESA_MODE_108 + default 0x109 if FRAMEBUFFER_VESA_MODE_109 + default 0x10A if FRAMEBUFFER_VESA_MODE_10A + default 0x10B if FRAMEBUFFER_VESA_MODE_10B + default 0x10C if FRAMEBUFFER_VESA_MODE_10C + default 0x10D if FRAMEBUFFER_VESA_MODE_10D + default 0x10E if FRAMEBUFFER_VESA_MODE_10E + default 0x10F if FRAMEBUFFER_VESA_MODE_10F + default 0x110 if FRAMEBUFFER_VESA_MODE_110 + default 0x111 if FRAMEBUFFER_VESA_MODE_111 + default 0x112 if FRAMEBUFFER_VESA_MODE_112 + default 0x113 if FRAMEBUFFER_VESA_MODE_113 + default 0x114 if FRAMEBUFFER_VESA_MODE_114 + default 0x115 if FRAMEBUFFER_VESA_MODE_115 + default 0x116 if FRAMEBUFFER_VESA_MODE_116 + default 0x117 if FRAMEBUFFER_VESA_MODE_117 + default 0x118 if FRAMEBUFFER_VESA_MODE_118 + default 0x119 if FRAMEBUFFER_VESA_MODE_119 + default 0x11A if FRAMEBUFFER_VESA_MODE_11A + default 0x11B if FRAMEBUFFER_VESA_MODE_11B config FRAMEBUFFER_KEEP_VESA_MODE prompt "Keep VESA framebuffer"

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Re: [coreboot] [SerialICE] Boots from PCI add-on card on Intel ICHs
by Patrick Georgi 21 May '12

21 May '12

Am Mo 21 Mai 2012 05:32:42 CEST schrieb ron minnich: > Maybe I misunderstand, but this is how Etherboot originally worked: > flash a new expansion rom onto, e.g., a 3c905 and that could take over > the boot process. But only after the PC BIOS did its work. This trick exploits that some chipsets allow PCI devices to respond to the system firmware region (4gb-flashsize), so it's coreboot running from the plugin card. Patrick

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Trac reminder: list of new ticket(s)
by coreboot tracker 21 May '12

21 May '12

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Re: [coreboot] [SerialICE] Boots from PCI add-on card on Intel ICHs
by Alexander Graf 21 May '12

21 May '12

On 21.05.2012, at 05:32, ron minnich <rminnich(a)gmail.com> wrote: > On Sun, May 20, 2012 at 1:23 AM, Kyösti Mälkki <kyosti.malkki(a)gmail.com> wrote: >> Hi >> >> I did not find this method of bypassing the mainboard flash chip and >> booting from PCI add-on card documented or discussed before. > > Maybe I misunderstand, but this is how Etherboot originally worked: > flash a new expansion rom onto, e.g., a 3c905 and that could take over > the boot process. If I read the original mail correctly, the method he describes maps the PCI card's option rom _over_ the mainboard one, so it allows for execution of code way earlier. However, couldn't the normal option rom code path be used to configure the BAR to 0xfff... and trigger a triple fault, rebooting the machine automatically into coreboot? That way you wouldn't have to manually enable coreboot, but only need to have your special PCI card plugged in ;) Alex

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Support of the MS-7091 mainboard
by Paul Du 18 May '12

18 May '12

Hello,I would like to know if my motherboard is or could be supported by coreboot. Thanks :)I was inspired from http://www.coreboot.org/pipermail/coreboot/2010-April/057128.html because I didn't find the answer of this mail so sorry if you've already answer for this motherboard.( Sorry if I didn't do the right things, it's my first mailing list. ) Step 1:My motherboard is a MSI-7091 (OEM-Board by MEDION) socket 775.The CPU is an Intel Pentium 4 524 3.06 Ghz with Hyperthreading.I found the Host bridge : Intel Corporation 82915G/P/GV/GL/PL/910GL Memory Controller HubThe PCI Bridge : Intel Corporation 82915G/P/GV/GL/PL/910GL PCI Express Root PortAnother PCI Bridge : Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1A third PCI Bridge : Intel Corporation 82801 PCI BridgeAn ISA Bridge : Intel Corporation 82801FB/FR (ICH6/ICH6R) LPC Interface BridgeA SMBUS : Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus ControllerMy System Operation is in 64 bits. Step 2 :-[0000:00]-+-00.0 Intel Corporation 82915G/P/GV/GL/PL/910GL Memory Controller Hub [8086:2580] +-01.0-[01]--+-00.0 Advanced Micro Devices [AMD] nee ATI Turks [Radeon HD 6670] [1002:6758] | \-00.1 Advanced Micro Devices [AMD] nee ATI Turks HDMI Audio [Radeon HD 6000 Series] [1002:aa90] +-1b.0 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller [8086:2668] +-1c.0-[02]-- +-1d.0 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 [8086:2658] +-1d.1 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 [8086:2659] +-1d.2 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 [8086:265a] +-1d.3 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 [8086:265b] +-1d.7 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller [8086:265c] +-1e.0-[03]--+-03.0 VIA Technologies, Inc. VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller [1106:3044] | \-06.0 VIA Technologies, Inc. VT6105/VT6106S [Rhine-III] [1106:3106] +-1f.0 Intel Corporation 82801FB/FR (ICH6/ICH6R) LPC Interface Bridge [8086:2640] +-1f.1 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller [8086:266f] +-1f.2 Intel Corporation 82801FB/FW (ICH6/ICH6W) SATA Controller [8086:2651] \-1f.3 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller [8086:266a] Step 3 :My Super I/O chip : WinBond W83637HF( I found it from dmesg : [ 0.488787] w83627hf: w83627hf: Found W83637HF chip at 0x290 ) superiotool rProbing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xffProbing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xffProbing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffffProbing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xc4f8, id=0xa170Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffffProbing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffffProbing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x70a1, rev=0xfProbing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xfProbing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xfProbing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xffProbing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xffProbing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xffProbing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xffProbing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffffProbing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffffProbing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0x70a1Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0x70a1, rev=0x00Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xffProbing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xffProbing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xffProbing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xffProbing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xffProbing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xffProbing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xffProbing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xffProbing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xffProbing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xffProbing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xffProbing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xffProbing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0x70/0x0f, rev=0xa1Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xffProbing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xffNo Super I/O found Step 4 :flashrom v0.9.5.2-r1515 on Linux 3.2.1-gentoo-r2 (x86_64), built with libpci 3.1.9, GCC 4.5.3, little endianflashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2019M loops per second, 10 myus = 10 us, 100 myus = 126 us, 1000 myus = 1021 us, 10000 myus = 10571 us, 4 myus = 7 us, OK.Initializing internal programmerNo coreboot table found.DMI string system-manufacturer: "MEDIONPC"DMI string system-product-name: "MS-7091"DMI string system-version: " "DMI string baseboard-manufacturer: "MICRO-STAR INTERNATIONAL CO., LTD"DMI string baseboard-product-name: "MS-7091"DMI string baseboard-version: " "DMI string chassis-type: "Desktop"Found chipset "Intel ICH6/ICH6R" with PCI ID 8086:2640. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x00xfff00000/0xffb00000 FWH IDSEL: 0x00xffe80000/0xffa80000 FWH IDSEL: 0x10xffe00000/0xffa00000 FWH IDSEL: 0x10xffd80000/0xff980000 FWH IDSEL: 0x20xffd00000/0xff900000 FWH IDSEL: 0x20xffc80000/0xff880000 FWH IDSEL: 0x30xffc00000/0xff800000 FWH IDSEL: 0x30xff700000/0xff300000 FWH IDSEL: 0x40xff600000/0xff200000 FWH IDSEL: 0x50xff500000/0xff100000 FWH IDSEL: 0x60xff400000/0xff000000 FWH IDSEL: 0x70xfff80000/0xffb80000 FWH decode enabled0xfff00000/0xffb00000 FWH decode enabled0xffe80000/0xffa80000 FWH decode disabled0xffe00000/0xffa00000 FWH decode disabled0xffd80000/0xff980000 FWH decode disabled0xffd00000/0xff900000 FWH decode disabled0xffc80000/0xff880000 FWH decode disabled0xffc00000/0xff800000 FWH decode disabled0xff700000/0xff300000 FWH decode disabled0xff600000/0xff200000 FWH decode disabled0xff500000/0xff100000 FWH decode disabled0xff400000/0xff000000 FWH decode disabledMaximum FWH chip size: 0x100000 bytesBIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0OK.The following protocols are supported: FWH.Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x5f, id2 0x8b, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash contentProbing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash contentProbing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0x34Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0x34Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xda, id2 0x34Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xda, id2 0x34Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xda, id2 0x34Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xda, id2 0x34Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash contentProbing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW002, 256 kB: probe_82802ab: id1 0x5f, id2 0x8b, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW040, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash contentProbing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash contentProbing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xda, id2 0x34Found Winbond flash chip "W39V040FA" (512 kB, FWH) at physical address 0xfff80000.Lockout bits:Hardware bootblock locking (#TBL) is active.Hardware remaining chip locking (#WP) is active..Software 64 kB bootblock locking is not active.Software 16 kB bootblock locking is not active.Lock status of block at 0x00000000 is Write Lock (Default State).Lock status of block at 0x00010000 is Write Lock (Default State).Lock status of block at 0x00020000 is Write Lock (Default State).Lock status of block at 0x00030000 is Write Lock (Default State).Lock status of block at 0x00040000 is Write Lock (Default State).Lock status of block at 0x00050000 is Write Lock (Default State).Lock status of block at 0x00060000 is Write Lock (Default State).Lock status of block at 0x00070000 is Write Lock (Default State).Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xda, id2 0x34Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xda, id2 0x34Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xda, id2 0x34Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xda, id2 0x34Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xda, id2 0x34Found Winbond flash chip "W39V040FA" (512 kB, FWH).No operations were specified.Restoring PCI config space for 00:1f:0 reg 0xdc Step 5:I didn't find the URL to the mainboard specifications page. :-( Thank you for reading my mail :)

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coreboot May 2012