coreboot May 2012

coreboot@coreboot.org

31 participants
287 discussions

Re: [coreboot] Adding Supermicro X9SCV-QV4
by Peter Stuge 16 May '12

16 May '12

Nachiketh G wrote: > If there is any particular board supported by coreboot which I can use as > reference for Intel QM67 chip set with the Intel core i5/i7 processor No, there is not. You have to develop chipset support from scratch. //Peter

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Re: [coreboot] Adding Supermicro X9SCV-QV4
by Peter Stuge 16 May '12

16 May '12

Nachiketh G wrote: > I wanted to know if there is any existing code base No, I don't believe there is. //Peter

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New patch to review for coreboot: a5a5432 Fix Persimmon build without S3.
by Marc Jones 16 May '12

16 May '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1034 -gerrit commit a5a543259f455c6d99cf1a8e69cd12cb4bafee20 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue May 15 16:08:24 2012 -0600 Fix Persimmon build without S3. In the heap function, only check for S3 check when it is built in with CONFIG_HAVE_ACPI_RESUME. Change-Id: I439275a4e1b7b446b499bcf90c925785a14b980d Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/mainboard/amd/persimmon/agesawrapper.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 0d63abb..195ff54 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -253,10 +253,12 @@ UINT32 GetHeapBase( { UINT32 heap; +#if CONFIG_HAVE_APCI_RESUME /* Both romstage and ramstage has this S3 detect. */ if (acpi_get_sleep_type() == 3) heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */ else +#endif heap = BIOS_HEAP_START_ADDRESS; /* low mem */ return heap;

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Patch merged into coreboot/master: 458c537 Fix fadt legacy free setting.
by gerrit＠coreboot.org 15 May '12

15 May '12

the following patch was just integrated into master: commit 458c5372d8945badcb47039b4e7622318d3a2611 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Sat May 12 09:56:45 2012 -0600 Fix fadt legacy free setting. The fadt legacy free logic was backwards. Change-Id: Ieb21ef335f7514ced70248d0bf8668ddb73cf59f Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue May 15 19:04:24 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue May 15 01:05:38 2012, giving +2 See http://review.coreboot.org/1030 for details. -gerrit

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Patch merged into coreboot/master: 4d479a5 Change the name of the romstage bootblock.ld
by gerrit＠coreboot.org 15 May '12

15 May '12

the following patch was just integrated into master: commit 4d479a511a819dec55b75051ba37f50492f2c9e0 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri May 11 13:23:45 2012 -0600 Change the name of the romstage bootblock.ld The bootblock.ld linkerscript is used by romstage. Name it accordingly to avoid confusion. Change-Id: I7ca9147bb821fe6f83224d170f5fe25654ef250f Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue May 15 07:37:55 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue May 15 07:02:58 2012, giving +2 See http://review.coreboot.org/1031 for details. -gerrit

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Patch merged into coreboot/master: 129d4e6 Fix Cygwin bootblock generation
by gerrit＠coreboot.org 15 May '12

15 May '12

the following patch was just integrated into master: commit 129d4e61e013b9f3ad4f6c13879661e29b47d6b3 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon May 14 16:20:26 2012 -0600 Fix Cygwin bootblock generation Cygwin is case insensitive, so bootblock.s and bootblock.S in the same directory cause a build failure. This changes bootblock.S to bootblock_inc.S, as it is generated from bootblock_inc. crt0.S and crt0.S also had this problem. This changes crt0.S to crt0.romstage.S. Change-Id: I29d230a93b0743e34f11228f9034880ceaf7ab7b Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue May 15 07:08:44 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue May 15 07:03:28 2012, giving +2 See http://review.coreboot.org/1032 for details. -gerrit

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Patch merged into coreboot/master: fb5306c Pass IASL to SeaBIOS
by gerrit＠coreboot.org 15 May '12

15 May '12

the following patch was just integrated into master: commit fb5306c489c07395984bcc59115ae0e2d3cb9f7b Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon May 14 21:06:10 2012 -0600 Pass IASL to SeaBIOS Use the coreboot IASL for building SeaBIOS. Change-Id: Ia6c802b090d53b7fbbc8ddb6edad3de6b822ff41 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue May 15 05:23:54 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue May 15 07:00:01 2012, giving +2 See http://review.coreboot.org/1033 for details. -gerrit

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Patch set updated for coreboot: 4d479a5 Change the name of the romstage bootblock.ld
by Marc Jones 15 May '12

15 May '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1031 -gerrit commit 4d479a511a819dec55b75051ba37f50492f2c9e0 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri May 11 13:23:45 2012 -0600 Change the name of the romstage bootblock.ld The bootblock.ld linkerscript is used by romstage. Name it accordingly to avoid confusion. Change-Id: I7ca9147bb821fe6f83224d170f5fe25654ef250f Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/init/bootblock.ld | 57 ---------------------------------------- src/arch/x86/init/romstage.ld | 57 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+), 58 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 5486bb1..5ccfaab 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -176,7 +176,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $( crt0s = $(src)/arch/x86/init/prologue.inc ldscripts = -ldscripts += $(src)/arch/x86/init/bootblock.ld +ldscripts += $(src)/arch/x86/init/romstage.ld crt0s += $(src)/cpu/x86/32bit/entry32.inc ldscripts += $(src)/cpu/x86/32bit/entry32.lds diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld deleted file mode 100644 index ca4e820..0000000 --- a/src/arch/x86/init/bootblock.ld +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* We use ELF as output format. So that we can debug the code in some form. */ -OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") -OUTPUT_ARCH(i386) - -TARGET(binary) -SECTIONS -{ - . = ROMSTAGE_BASE; - - .rom . : { - _rom = .; - *(.rom.text); - *(.rom.data); - *(.rodata); - *(.rodata.*); - *(.rom.data.*); - . = ALIGN(16); - _erom = .; - } - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } - - . = CONFIG_DCACHE_RAM_BASE; - .car.data . (NOLOAD) : { - *(.car.global_data); - *(.car.cbmem_console); - } - - _bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); - _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage"); -} diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld new file mode 100644 index 0000000..ca4e820 --- /dev/null +++ b/src/arch/x86/init/romstage.ld @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* We use ELF as output format. So that we can debug the code in some form. */ +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) + +TARGET(binary) +SECTIONS +{ + . = ROMSTAGE_BASE; + + .rom . : { + _rom = .; + *(.rom.text); + *(.rom.data); + *(.rodata); + *(.rodata.*); + *(.rom.data.*); + . = ALIGN(16); + _erom = .; + } + + /DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.eh_frame); + } + + . = CONFIG_DCACHE_RAM_BASE; + .car.data . (NOLOAD) : { + *(.car.global_data); + *(.car.cbmem_console); + } + + _bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); + _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage"); +}

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Patch set updated for coreboot: 129d4e6 Fix Cygwin bootblock generation
by Marc Jones 15 May '12

15 May '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1032 -gerrit commit 129d4e61e013b9f3ad4f6c13879661e29b47d6b3 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon May 14 16:20:26 2012 -0600 Fix Cygwin bootblock generation Cygwin is case insensitive, so bootblock.s and bootblock.S in the same directory cause a build failure. This changes bootblock.S to bootblock_inc.S, as it is generated from bootblock_inc. crt0.S and crt0.S also had this problem. This changes crt0.S to crt0.romstage.S. Change-Id: I29d230a93b0743e34f11228f9034880ceaf7ab7b Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/arch/x86/Makefile.inc | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 5ccfaab..49abfde 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -291,7 +291,7 @@ $(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ -$(objgenerated)/bootblock.S: $$(bootblock_inc) +$(objgenerated)/bootblock_inc.S: $$(bootblock_inc) @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ @@ -299,7 +299,7 @@ $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm -$(objgenerated)/bootblock.s: $(objgenerated)/bootblock.S $(obj)/config.h $(obj)/build.h +$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ @@ -346,7 +346,7 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin rm $@.tmp mv $@.tmp2 $@ -$(objgenerated)/crt0.S: $$(crt0s) +$(objgenerated)/crt0.romstage.S: $$(crt0s) @printf " GEN $(subst $(obj)/,,$(@))\n" printf '$(foreach crt0,$(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@ @@ -354,7 +354,7 @@ $(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm -$(objgenerated)/crt0.s: $(objgenerated)/crt0.S $(obj)/config.h $(obj)/build.h +$(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@

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New patch to review for coreboot: fb5306c Pass IASL to SeaBIOS
by Marc Jones 15 May '12

15 May '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1033 -gerrit commit fb5306c489c07395984bcc59115ae0e2d3cb9f7b Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon May 14 21:06:10 2012 -0600 Pass IASL to SeaBIOS Use the coreboot IASL for building SeaBIOS. Change-Id: Ia6c802b090d53b7fbbc8ddb6edad3de6b822ff41 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/arch/x86/Makefile.inc | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 5486bb1..1b1308e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -365,7 +365,7 @@ seabios: OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ - OUT=$(abspath $(obj)) + OUT=$(abspath $(obj)) IASL="$(IASL)" filo: $(MAKE) -C payloads/external/FILO -f Makefile.inc \

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coreboot May 2012