coreboot May 2012

coreboot@coreboot.org

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287 discussions

Patch set updated for coreboot: 2cae4a4 crossgcc: Test for m4 and bison
by Patrick Georgi 12 May '12

12 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1026 -gerrit commit 2cae4a41616ca7a7aba6c6db680d94c7bbbd5476 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 12 23:25:23 2012 +0200 crossgcc: Test for m4 and bison Happened way too often that crossgcc failed because m4 or bison wasn't installed already. Change-Id: Ibcca2183edd5db20608015e3898f8fff9a6d11e8 … [View More]

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Patch set updated for coreboot: 90c3179 crossgcc: update sources
by Patrick Georgi 12 May '12

12 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1025 -gerrit commit 90c31797677edfe30d196dd413e3cc1cff7708a8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 12 23:19:30 2012 +0200 crossgcc: update sources Update GNU project versions, download GNU project tarballs using ftpmirror.gnu.org (http, picking close servers). Update ACPICA tarballs, ignore https … [View More]

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New patch to review for coreboot: 31191fb SPI driver: style fix
by Patrick Georgi 12 May '12

12 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1029 -gerrit commit 31191fb9eacbada83ecdcba68325539ee019c20e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 12 23:30:36 2012 +0200 SPI driver: style fix lint tests for labels to start at BOL, no spaces before them. Change-Id: Icf6ce533f26998a81b4be46d17e2d0b6b868904d Signed-off-by: Patrick Georgi <patrick(a)… [View More]

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New patch to review for coreboot: 7fce5cb abuild: Move configuration handling together
by Patrick Georgi 12 May '12

12 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1028 -gerrit commit 7fce5cbc6ded8f65db42d0fd1c85ce72e44072ca Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue May 1 15:14:46 2012 +0200 abuild: Move configuration handling together Handling user options was spread out across the code. Collect as much as possible in the getopt loop. Change-Id: … [View More]I4979a14988da000c008e155023b960535b529b41 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/abuild/abuild | 106 ++++++++++++++++++++++----------------------------- 1 files changed, 46 insertions(+), 60 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 032aba5..481fbc2 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -32,9 +32,6 @@ CONTEXT=6 TESTSUBMISSION="http://qa.coreboot.org/deployment/send.php" -# Number of CPUs to compile on per default -cpus=1 - # Configure-only mode configureonly=0 @@ -61,21 +58,9 @@ silent= # clang mode enabled by -sb option. scanbuild=false -# use ccache -ccache=false - # stackprotect mode enabled by -ns option. stackprotect=false -# loglevel changed with -l / --loglevel option -loglevel=default - -# update existing image -update=false - -# CBFS prefix -cbfs_prefix=fallback - ARCH=`uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \ -e s/i86pc/i386/ \ -e s/arm.*/arm/ -e s/sa110/arm/ -e s/x86_64/amd64/ \ @@ -173,10 +158,8 @@ function create_config printf "Using payload $PAYLOAD\n" fi - [ "$update" = "true" ] && mv ${build_dir}/coreboot.rom coreboot.rom.tmp mkdir -p ${build_dir} mkdir -p $TARGET/sharedutils - [ "$update" = "true" ] && mv coreboot.rom.tmp ${build_dir}/coreboot.rom if [ "$CONFIG" != "" ]; then printf " Using existing configuration $CONFIG ... " @@ -192,7 +175,6 @@ function create_config grep "select[\t ]*ARCH" src/mainboard/$VENDOR/$MAINBOARD/Kconfig | \ sed "s,^.*$ARCH_.*$[^A-Z0-9_]*,CONFIG_\1=y," >> ${build_dir}/config.build echo "CONFIG_MAINBOARD_DIR=\"$VENDOR/$MAINBOARD\"" >> ${build_dir}/config.build - echo "CONFIG_CBFS_PREFIX=\"$cbfs_prefix\"" >> ${build_dir}/config.build if [ "$PAYLOAD" != "/dev/null" ]; then echo "# CONFIG_PAYLOAD_NONE is not set" >> ${build_dir}/config.build echo "# CONFIG_PAYLOAD_SEABIOS is not set" >> ${build_dir}/config.build @@ -200,37 +182,10 @@ function create_config echo "CONFIG_PAYLOAD_FILE=\"$PAYLOAD\"" >> ${build_dir}/config.build fi - if [ "$loglevel" != "default" ]; then - printf "(loglevel override) " - echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_$loglevel=y" >> ${build_dir}/config.build - echo "CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$loglevel" >> ${build_dir}/config.build - echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$loglevel=y" >> ${build_dir}/config.build - echo "CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$loglevel" >> ${build_dir}/config.build - fi - - if [ "$update" != "false" ]; then - printf "(update) " - echo "CONFIG_UPDATE_IMAGE=y" >> ${build_dir}/config.build - fi - - if [ "$ccache" = "true" ]; then - printf "(ccache enabled) " - echo "CONFIG_CCACHE=y" >> ${build_dir}/config.build - fi - - if [ "$enable_blobs" = "true" ]; then - printf "(blobs enabled) " - echo "CONFIG_USE_BLOBS=y" >> ${build_dir}/config.build - fi - - if [ "$scanbuild" = "true" ]; then - printf "(scan-build enabled) " - echo "CONFIG_SCANBUILD_ENABLE=y" >> ${build_dir}/config.build - echo "CONFIG_SCANBUILD_REPORT_LOCATION=\"$TARGET/scan-build-results-tmp\"" >> ${build_dir}/config.build - fi + printf "($customizing) " + printf "$configoptions" >> ${build_dir}/config.build fi - #yes "" | $MAKE oldconfig obj=${build_dir} objutil=$TARGET/sharedutils &> ${build_dir}/config.log yes "" | $MAKE oldconfig DOTCONFIG=${build_dir}/config.build obj=${build_dir} objutil=$TARGET/sharedutils &> ${build_dir}/config.log ret=$? if [ $ret -eq 0 ]; then @@ -286,10 +241,7 @@ function compile_target VENDOR=$1 MAINBOARD=$2 - printf " Compiling image " - test "$cpus" == "" && printf "in parallel .. " - test "$cpus" == "1" && printf "on 1 cpu .. " - test 0$cpus -gt 1 && printf "on %d cpus in parallel .. " $cpus + printf " Compiling image $cpuconfig .. " CURR=$( pwd ) #stime=`perl -e 'print time();' 2>/dev/null || date +%s` @@ -534,7 +486,7 @@ function myhelp printf " [-u|--update] update existing image\n" printf " [-P|--prefix <name>] file name prefix in CBFS\n" printf " [-B|--blobs] Allow using binary files\n" - printf " [lbroot] absolute path to coreboot sources\n" + printf " [cbroot] absolute path to coreboot sources\n" printf " (defaults to $ROOT)\n\n" } @@ -587,6 +539,8 @@ if [ $? != 0 ]; then exit 1 fi +customizing="" +configoptions="" while true ; do case "$1" in -x|--xml) shift; mode=xml; rm -f $XMLFILE ;; @@ -599,22 +553,55 @@ while true ; do -h|--help) shift; myversion; myhelp; exit 0;; -p|--payloads) shift; payloads="$1"; shift;; -T|--test) shift; hwtest=true;; - -c|--cpus) shift; cpus="$1"; test "$cpus" == "max" && cpus=""; shift;; + -c|--cpus) shift + export MAKEFLAGS="-j $1" + test "$MAKEFLAGS" == "-j max" && export MAKEFLAGS="-j" + test "$1" == "" && cpuconfig="in parallel" + test "$1" == "1" && cpuconfig="on 1 cpu" + test 0$1 -gt 1 && cpuconfig="on $1 cpus in parallel" + shift;; -s|--silent) shift; silent="-s";; -ns|--nostackprotect) shift; stackprotect=true;; - -sb|--scan-build) shift; scanbuild=true;; - -y|--ccache) shift; ccache=true;; + -sb|--scan-build) shift + scanbuild=true + customizing="${customizing}, scan-build" + configoptions="${configoptions}CONFIG_SCANBUILD_ENABLE=y\nCONFIG_SCANBUILD_REPORT_LOCATION=\"$TARGET/scan-build-results-tmp\"" + ;; + -y|--ccache) shift + customizing="${customizing}, ccache" + configoptions="${configoptions}CONFIG_CCACHE=y\n" + ;; -C|--config) shift; configureonly=1;; - -l|--loglevel) shift; loglevel="$1"; shift;; - -u|--update) shift; update="true";; - -P|--prefix) shift; cbfs_prefix="$1"; shift;; - -B|--blobs) shift; enable_blobs="true";; + -l|--loglevel) shift + customizing="${customizing}, loglevel $1" + configoptions="${configoptions}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_$1=y\n" + configoptions="${configoptions}CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=$1\n" + configoptions="${configoptions}CONFIG_DEFAULT_CONSOLE_LOGLEVEL_$1=y\n" + configoptions="${configoptions}CONFIG_DEFAULT_CONSOLE_LOGLEVEL=$1\n" + shift;; + -u|--update) shift + customizing="${customizing}, update" + configoptions="${configoptions}CONFIG_UPDATE_IMAGE=y\n" + ;; + -P|--prefix) shift + customizing="${customizing}, cbfs prefix $1" + configoptions="${configoptions}CONFIG_CBFS_PREFIX=\"$1\"" + shift;; + -B|--blobs) shift + customizing="${customizing}, blobs" + configoptions="${configoptions}CONFIG_USE_BLOBS=y\n" + ;; --) shift; break;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; *) break;; esac done +customizing=`echo $customizing |cut -c3-` +if [ "$customizing" = "" ]; then + customizing="default configuration" +fi + USE_XARGS=0 if [ "$cpus" != "1" ]; then if [ "$target" = "" ]; then @@ -659,7 +646,6 @@ build_all_targets() } fi -# /path/to/freebios2/ test -z "$1" || ROOT=$1 debug "ROOT=$ROOT" [View Less]

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New patch to review for coreboot: c9f2672 abuild: Remove abuild.info hack
by Patrick Georgi 12 May '12

12 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1027 -gerrit commit c9f2672d961f2b3f1cd5a315578529f356f50959 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Jan 10 21:59:08 2012 +0100 abuild: Remove abuild.info hack abuild used to allow boards to override certain environment variables using a file called abuild.info. This isn't used, this isn't needed. Drop it. … [View More]

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New patch to review for coreboot: bbed7b5 crossgcc: Test for m4
by Patrick Georgi 12 May '12

12 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1026 -gerrit commit bbed7b5eadfffdac4ce6ec771eb0148f108dc133 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 12 23:25:23 2012 +0200 crossgcc: Test for m4 Happened way too often that crossgcc failed because m4 wasn't installed already. Change-Id: Ibcca2183edd5db20608015e3898f8fff9a6d11e8 Signed-off-by: Patrick … [View More]

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New patch to review for coreboot: f453875 crossgcc: update sources
by Patrick Georgi 12 May '12

12 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1025 -gerrit commit f4538753b04dda01ccec9c6ca0835e9d144667b7 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 12 23:19:30 2012 +0200 crossgcc: update sources Update GNU project versions, download GNU project tarballs using ftpmirror.gnu.org (http, picking close servers). Update ACPICA tarballs, ignore https … [View More]

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Re: [coreboot] memory
by Stefan Reinauer 12 May '12

12 May '12

On 5/12/12 1:43 AM, ali hagigat wrote: > If the CPU wb (write back) cache is enabled for the memory range, > ramstage() is OK. But CPU can not work with UC(uncached) memory type > in Coreboot code. If i define the whole memory un-cached right before > jumping to ramstage code ( cbfs_and_run()), CPU does not execute > C_start.S and it is actually restarted! > Any clue or idea will be much appreciated. > It means your memory is misconfigured, but leaving the cache enabled … [View More]

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Re: [coreboot] please check coreboot supports for this given configuration
by Peter Stuge 12 May '12

12 May '12

manasa gv wrote: > product: Mobile 4 Series Chipset Memory Controller Hub Not supported. //Peter

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please check coreboot supports for this given configuration
by manasa gv 12 May '12

12 May '12

Hi, I have given below information about my system.. please let me know will coreboot support for this configuration.. Step 1: Board Vendor: TOSHIBA Board Name : Satellite L500 (Montevina_Fab) CPU : Pentium(R) Dual-Core CPU T4300 @ 2.10GHz CPU Vendor : Intel Corp I didn't find northbridge and southbridge information..So i added the output of 'lshw' .. description: Notebook product: Satellite L500 (Montevina_Fab) … [View More] vendor: TOSHIBA version: PSLLTG-007003 serial: Z9070791Q width: 64 bits capabilities: smbios-2.4 dmi-2.4 vsyscall32 configuration: boot=normal chassis=notebook family=Intel_Mobile sku=Montevina_Fab uuid=9A1C7C40-DAFE-11DE-BBA9-00266C35CC82 *-core description: Motherboard product: Portable PC vendor: TOSHIBA physical id: 0 version: Base Board Version serial: Base Board Serial Number slot: Base Board Chassis Location *-firmware description: BIOS vendor: INSYDE physical id: 0 version: 1.40 date: 09/07/2009 size: 1MiB capabilities: pci upgrade shadowing cdboot bootselect socketedrom edd int13floppynec int13floppytoshiba int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int9keyboard int10video acpi usb *-memory description: System Memory physical id: 13 slot: System board or motherboard size: 2GiB *-bank:0 description: SODIMM DDR2 Synchronous 800 MHz (1.2 ns) product: M4 70T5663EH3-CF7 vendor: Samsung physical id: 0 serial: 6553A654 slot: DIMM0 size: 2GiB width: 64 bits clock: 800MHz (1.2ns) *-bank:1 description: SODIMM [empty] physical id: 1 slot: DIMM2 *-cpu description: CPU product: Pentium(R) Dual-Core CPU T4300 @ 2.10GHz vendor: Intel Corp. physical id: 1c bus info: cpu@0 version: Pentium(R) Dual-Core CPU T4300 @ 2.10GHz slot: CPU size: 1200MHz capacity: 2100MHz width: 64 bits clock: 800MHz capabilities: fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx x86-64 constant_tsc arch_perfmon pebs bts rep_good nopl aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm xsave lahf_lm cpufreq *-cache:0 description: L2 cache physical id: 1d slot: Unknown size: 1MiB capacity: 1MiB capabilities: synchronous internal write-back unified *-cache:1 description: L1 cache physical id: 1f slot: Unknown size: 32KiB capacity: 32KiB capabilities: synchronous internal write-back data *-cache description: L1 cache physical id: 1e slot: Unknown size: 32KiB capacity: 32KiB capabilities: synchronous internal write-back instruction *-pci description: Host bridge product: Mobile 4 Series Chipset Memory Controller Hub vendor: Intel Corporation physical id: 100 bus info: pci@0000:00:00.0 version: 07 width: 32 bits clock: 33MHz configuration: driver=agpgart-intel resources: irq:0 *-display:0 description: VGA compatible controller product: Mobile 4 Series Chipset Integrated Graphics Controller vendor: Intel Corporation physical id: 2 bus info: pci@0000:00:02.0 version: 07 width: 64 bits clock: 33MHz capabilities: msi pm vga_controller bus_master cap_list rom configuration: driver=i915 latency=0 resources: irq:43 memory:90000000-903fffff memory:80000000-8fffffff ioport:4110(size=8) *-display:1 UNCLAIMED description: Display controller product: Mobile 4 Series Chipset Integrated Graphics Controller vendor: Intel Corporation physical id: 2.1 bus info: pci@0000:00:02.1 version: 07 width: 64 bits clock: 33MHz capabilities: pm bus_master cap_list configuration: latency=0 resources: memory:92500000-925fffff *-usb:0 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #4 vendor: Intel Corporation physical id: 1a bus info: pci@0000:00:1a.0 version: 03 width: 32 bits clock: 33MHz capabilities: uhci bus_master cap_list configuration: driver=uhci_hcd latency=0 resources: irq:16 ioport:40e0(size=32) *-usb:1 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #5 vendor: Intel Corporation physical id: 1a.1 bus info: pci@0000:00:1a.1 version: 03 width: 32 bits clock: 33MHz capabilities: uhci bus_master cap_list configuration: driver=uhci_hcd latency=0 resources: irq:21 ioport:40c0(size=32) *-usb:2 description: USB Controller product: 82801I (ICH9 Family) USB2 EHCI Controller #2 vendor: Intel Corporation physical id: 1a.7 bus info: pci@0000:00:1a.7 version: 03 width: 32 bits clock: 33MHz capabilities: pm debug ehci bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:19 memory:94604c00-94604fff *-multimedia description: Audio device product: 82801I (ICH9 Family) HD Audio Controller vendor: Intel Corporation physical id: 1b bus info: pci@0000:00:1b.0 version: 03 width: 64 bits clock: 33MHz capabilities: pm msi pciexpress bus_master cap_list configuration: driver=snd_hda_intel latency=0 resources: irq:45 memory:94600000-94603fff *-pci:0 description: PCI bridge product: 82801I (ICH9 Family) PCI Express Port 1 vendor: Intel Corporation physical id: 1c bus info: pci@0000:00:1c.0 version: 03 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:40 ioport:2000(size=8192) memory:93600000-945fffff ioport:90400000(size=17825792) *-network description: Ethernet interface product: RTL8101E/RTL8102E PCI Express Fast Ethernet controller vendor: Realtek Semiconductor Co., Ltd. physical id: 0 bus info: pci@0000:02:00.0 logical name: em1 version: 02 serial: 00:26:6c:35:cc:82 size: 100Mbit/s capacity: 100Mbit/s width: 64 bits clock: 33MHz capabilities: pm msi pciexpress msix vpd bus_master cap_list rom ethernet physical tp mii 10bt 10bt-fd 100bt 100bt-fd autonegotiation configuration: autonegotiation=on broadcast=yes driver=r8169 driverversion=2.3LK-NAPI duplex=full ip=192.168.1.7 latency=0 link=yes multicast=yes port=MII speed=100Mbit/s resources: irq:44 ioport:2000(size=256) memory:90410000-90410fff memory:90400000-9040ffff memory:90420000-9043ffff *-pci:1 description: PCI bridge product: 82801I (ICH9 Family) PCI Express Port 5 vendor: Intel Corporation physical id: 1c.4 bus info: pci@0000:00:1c.4 version: 03 width: 32 bits clock: 33MHz capabilities: pci pciexpress msi pm normal_decode bus_master cap_list configuration: driver=pcieport resources: irq:41 ioport:1000(size=4096) memory:92600000-935fffff ioport:91500000(size=16777216) *-usb:3 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #1 vendor: Intel Corporation physical id: 1d bus info: pci@0000:00:1d.0 version: 03 width: 32 bits clock: 33MHz capabilities: uhci bus_master cap_list configuration: driver=uhci_hcd latency=0 resources: irq:23 ioport:40a0(size=32) *-usb:4 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #2 vendor: Intel Corporation physical id: 1d.1 bus info: pci@0000:00:1d.1 version: 03 width: 32 bits clock: 33MHz capabilities: uhci bus_master cap_list configuration: driver=uhci_hcd latency=0 resources: irq:19 ioport:4080(size=32) *-usb:5 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #3 vendor: Intel Corporation physical id: 1d.2 bus info: pci@0000:00:1d.2 version: 03 width: 32 bits clock: 33MHz capabilities: uhci bus_master cap_list configuration: driver=uhci_hcd latency=0 resources: irq:16 ioport:4060(size=32) *-usb:6 description: USB Controller product: 82801I (ICH9 Family) USB UHCI Controller #6 vendor: Intel Corporation physical id: 1d.3 bus info: pci@0000:00:1d.3 version: 03 width: 32 bits clock: 33MHz capabilities: uhci bus_master cap_list configuration: driver=uhci_hcd latency=0 resources: irq:18 ioport:4040(size=32) *-usb:7 description: USB Controller product: 82801I (ICH9 Family) USB2 EHCI Controller #1 vendor: Intel Corporation physical id: 1d.7 bus info: pci@0000:00:1d.7 version: 03 width: 32 bits clock: 33MHz capabilities: pm debug ehci bus_master cap_list configuration: driver=ehci_hcd latency=0 resources: irq:23 memory:94604800-94604bff *-pci:2 description: PCI bridge product: 82801 Mobile PCI Bridge vendor: Intel Corporation physical id: 1e bus info: pci@0000:00:1e.0 version: 93 width: 32 bits clock: 33MHz capabilities: pci subtractive_decode bus_master cap_list *-isa description: ISA bridge product: ICH9M LPC Interface Controller vendor: Intel Corporation physical id: 1f bus info: pci@0000:00:1f.0 version: 03 width: 32 bits clock: 33MHz capabilities: isa bus_master cap_list configuration: latency=0 *-storage description: SATA controller product: ICH9M/M-E SATA AHCI Controller vendor: Intel Corporation physical id: 1f.2 bus info: pci@0000:00:1f.2 version: 03 width: 32 bits clock: 66MHz capabilities: storage msi pm ahci_1.0 bus_master cap_list configuration: driver=ahci latency=0 resources: irq:42 ioport:4108(size=8) ioport:411c(size=4) ioport:4100(size=8) ioport:4118(size=4) ioport:4020(size=32) memory:94604000-946047ff *-serial description: SMBus product: 82801I (ICH9 Family) SMBus Controller vendor: Intel Corporation physical id: 1f.3 bus info: pci@0000:00:1f.3 version: 03 width: 64 bits clock: 33MHz configuration: driver=i801_smbus latency=0 resources: irq:18 memory:94605000-946050ff ioport:4000(size=32) *-scsi:0 physical id: 1 logical name: scsi1 capabilities: emulated *-disk description: ATA Disk product: Hitachi HTS54503 vendor: Hitachi physical id: 0.0.0 bus info: scsi@1:0.0.0 logical name: /dev/sda version: PB3O serial: 091119PBPC00QDDVPLPL size: 298GiB (320GB) capabilities: partitioned partitioned:dos configuration: ansiversion=5 sectorsize=512 signature=a83da1d9 *-volume:0 description: Windows NTFS volume physical id: 1 bus info: scsi@1:0.0.0,1 logical name: /dev/sda1 version: 3.1 serial: eaa4ffec-6c05-8f45-998e-5d83ea471272 size: 29GiB capacity: 29GiB capabilities: primary bootable ntfs initialized configuration: clustersize=4096 created=2010-04-05 16:37:09 filesystem=ntfs label=win xp state=clean *-volume:1 description: Extended partition physical id: 2 bus info: scsi@1:0.0.0,2 logical name: /dev/sda2 size: 268GiB capacity: 268GiB capabilities: primary extended partitioned partitioned:extended *-logicalvolume:0 description: HPFS/NTFS partition physical id: 5 logical name: /dev/sda5 capacity: 78GiB *-logicalvolume:1 description: HPFS/NTFS partition physical id: 6 logical name: /dev/sda6 capacity: 78GiB *-logicalvolume:2 description: HPFS/NTFS partition physical id: 7 logical name: /dev/sda7 capacity: 58GiB *-logicalvolume:3 description: Linux filesystem partition physical id: 8 logical name: /dev/sda8 logical name: / capacity: 47GiB configuration: mount.fstype=ext4 mount.options=rw,seclabel,relatime,user_xattr,barrier=1,data=ordered state=mounted *-logicalvolume:4 description: Linux swap / Solaris partition physical id: 9 logical name: /dev/sda9 capacity: 6228MiB capabilities: nofs *-scsi:1 physical id: 2 logical name: scsi5 capabilities: emulated *-cdrom description: DVD-RAM writer product: DVDRAM GT20N vendor: HL-DT-ST physical id: 0.0.0 bus info: scsi@5:0.0.0 logical name: /dev/cdrom1 logical name: /dev/cdrw1 logical name: /dev/dvd1 logical name: /dev/dvdrw1 logical name: /dev/scd0 logical name: /dev/sr0 version: CT10 capabilities: removable audio cd-r cd-rw dvd dvd-r dvd-ram configuration: ansiversion=5 status=nodisc *-power UNCLAIMED description: OEM_Define1 product: OEM_Define4 vendor: OEM_Define2 physical id: 1 version: OEM_Define5 serial: OEM_Define2 capacity: 75mWh *-network:0 description: Wireless interface physical id: 2 bus info: usb@2:6 logical name: wlan0 serial: 70:1a:04:65:ff:36 capabilities: ethernet physical wireless configuration: broadcast=yes driver=rtl8187 driverversion=3.3.2-6.fc16.x86_64 firmware=N/A link=no multicast=yes wireless=IEEE 802.11bg *-network:1 DISABLED description: Ethernet interface physical id: 3 logical name: virbr0-nic serial: 52:54:00:7e:82:44 size: 10Mbit/s capabilities: ethernet physical configuration: autonegotiation=off broadcast=yes driver=tun driverversion=1.6 duplex=full link=no multicast=yes port=twisted pair speed=10Mbit/s STEP 2 : ' lspci -tvnn ' -[0000:00]-+-00.0 Intel Corporation Mobile 4 Series Chipset Memory Controller Hub [8086:2a40] +-02.0 Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a42] +-02.1 Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a43] +-1a.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 [8086:2937] +-1a.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 [8086:2938] +-1a.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 [8086:293c] +-1b.0 Intel Corporation 82801I (ICH9 Family) HD Audio Controller [8086:293e] +-1c.0-[02]----00.0 Realtek Semiconductor Co., Ltd. RTL8101E/RTL8102E PCI Express Fast Ethernet controller [10ec:8136] +-1c.4-[07-08]-- +-1d.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934] +-1d.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 [8086:2935] +-1d.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 [8086:2936] +-1d.3 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 [8086:2939] +-1d.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 [8086:293a] +-1e.0-[03]-- +-1f.0 Intel Corporation ICH9M LPC Interface Controller [8086:2919] +-1f.2 Intel Corporation ICH9M/M-E SATA AHCI Controller [8086:2929] \-1f.3 Intel Corporation 82801I (ICH9 Family) SMBus Controller [8086:2930] STEP 3 : superiotool r6543 STEP 4 : BIOS Information Vendor: INSYDE Version: 1.40 Release Date: 09/07/2009 ROM Size: 1024 kB Output of ' flashrom -v ' : flashrom v0.9.4-r1487 on Linux 3.3.2-6.fc16.x86_64 (x86_64), built with libpci 3.1.7, GCC 4.6.2 20111027 (Red Hat 4.6.2-1), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2074M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1003 us, 10000 myus = 10018 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "TOSHIBA" DMI string system-product-name: "Satellite L500" DMI string system-version: "PSLLTG-007003" DMI string baseboard-manufacturer: "TOSHIBA" DMI string baseboard-product-name: "Portable PC" DMI string baseboard-version: "Base Board Version" DMI string chassis-type: "Notebook" Laptop detected via DMI. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. Thanks, Manasa [View Less]

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coreboot May 2012