Patch set updated for coreboot: 4d479a5 Change the name of the romstage bootblock.ld

[Marc Jones]

Marc Jones ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1031

-gerrit

commit 4d479a511a819dec55b75051ba37f50492f2c9e0
Author: Marc Jones 
Date:   Fri May 11 13:23:45 2012 -0600

Change the name of the romstage bootblock.ld

The bootblock.ld linkerscript is used by romstage. Name it
    accordingly to avoid confusion.

Change-Id: I7ca9147bb821fe6f83224d170f5fe25654ef250f
    Signed-off-by: Marc Jones 
---
 src/arch/x86/Makefile.inc      |    2 +-
 src/arch/x86/init/bootblock.ld |   57 ----------------------------------------
 src/arch/x86/init/romstage.ld  |   57 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 58 insertions(+), 58 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 5486bb1..5ccfaab 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -176,7 +176,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(

crt0s = $(src)/arch/x86/init/prologue.inc
 ldscripts =
-ldscripts += $(src)/arch/x86/init/bootblock.ld
+ldscripts += $(src)/arch/x86/init/romstage.ld
 crt0s += $(src)/cpu/x86/32bit/entry32.inc
 ldscripts += $(src)/cpu/x86/32bit/entry32.lds

diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld
deleted file mode 100644
index ca4e820..0000000
--- a/src/arch/x86/init/bootblock.ld
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/* We use ELF as output format. So that we can debug the code in some form. */
-OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
-OUTPUT_ARCH(i386)
-
-TARGET(binary)
-SECTIONS
-{
-	. = ROMSTAGE_BASE;
-
-	.rom . : {
-		_rom = .;
-		*(.rom.text);
-		*(.rom.data);
-		*(.rodata);
-		*(.rodata.*);
-		*(.rom.data.*);
-		. = ALIGN(16);
-		_erom = .;
-	}
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.comment.*)
-		*(.note.*)
-		*(.eh_frame);
-	}
-
-	. = CONFIG_DCACHE_RAM_BASE;
-	.car.data . (NOLOAD) : {
-		*(.car.global_data);
-		*(.car.cbmem_console);
-	}
-
-	_bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage");
-}
diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld
new file mode 100644
index 0000000..ca4e820
--- /dev/null
+++ b/src/arch/x86/init/romstage.ld
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+
+TARGET(binary)
+SECTIONS
+{
+	. = ROMSTAGE_BASE;
+
+	.rom . : {
+		_rom = .;
+		*(.rom.text);
+		*(.rom.data);
+		*(.rodata);
+		*(.rodata.*);
+		*(.rom.data.*);
+		. = ALIGN(16);
+		_erom = .;
+	}
+
+	/DISCARD/ : {
+		*(.comment)
+		*(.note)
+		*(.comment.*)
+		*(.note.*)
+		*(.eh_frame);
+	}
+
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		*(.car.global_data);
+		*(.car.cbmem_console);
+	}
+
+	_bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
+	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage");
+}