coreboot May 2012

coreboot@coreboot.org

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287 discussions

New patch to review for coreboot: 36c386f Fix the location of "Setting variable MTRR" printk.
by Denis Carikli 29 May '12

29 May '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1058 -gerrit commit 36c386f5387d0726be59db2193edd62cb3880136 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat May 26 00:13:22 2012 +0200 Fix the location of "Setting variable MTRR" printk. Without that fix the debugging is harder because the person debugging coreboot will see the following twice(note the repeated MTRR number): Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB [...] Setting variable MTRR 1, base: 4096MB, range: 512MB, type WB Setting variable MTRR 1, base: 4608MB, range: 256MB, type WB Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC instead of the following twice: Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB [...] Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC Thanks to kmalkki on #coreboot's Freenode IRC channel for the idea: May 25 23:57:17 <kmalkki> I would add (move) that "Setting variable MTRR..." debug at the end of set_var_mtrrs() Change-Id: I9f4b7110ba34d017a58d8cc5fb06a7b1c3d0c8aa Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/cpu/x86/mtrr/mtrr.c | 11 ++++++----- 1 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index cce526a..f8b2591 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -140,6 +140,12 @@ static void set_var_mtrr( wrmsr (MTRRphysMask_MSR(reg), mask); enable_cache(); + + printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", + reg, basek >>10, sizek >> 10, + (type==MTRR_TYPE_UNCACHEABLE)?"UC": + ((type==MTRR_TYPE_WRBACK)?"WB":"Other") + ); } /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ @@ -284,11 +290,6 @@ static unsigned int range_to_mtrr(unsigned int reg, align = max_align; } sizek = 1 << align; - printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", - reg, range_startk >>10, sizek >> 10, - (type==MTRR_TYPE_UNCACHEABLE)?"UC": - ((type==MTRR_TYPE_WRBACK)?"WB":"Other") - ); /* if range is above 4GB, MTRR is needed * only if above4gb flag is set

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Patch set updated for coreboot: d655d68 Use ld manually when compiling with clang
by Patrick Georgi 29 May '12

29 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/785 -gerrit commit d655d6881dbb3a69f66486e7d1b6074f9bfe0805 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Mar 11 20:15:21 2012 +0100 Use ld manually when compiling with clang clang does its own linking, incompatible to our binutils-centric linker magic. Change-Id: I243597adcb6bc3f7343c3431d7473610c327353d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/Makefile.inc | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 9739555..f498831 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -149,11 +149,19 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @printf " CC $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/coreboot_ram.ld +else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $< +endif $(objgenerated)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(objgenerated)/ramstage.a $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD) -m elf_i386 -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(objgenerated)/ramstage.a $(LIBGCC_FILE_NAME) --end-group +else $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(objgenerated)/ramstage.a $(LIBGCC_FILE_NAME) -Wl,--end-group +endif $(objgenerated)/ramstage.a: $$(ramstage-objs) @printf " AR $(subst $(obj)/,,$(@))\n" @@ -311,18 +319,30 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOC $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD) -m elf_i386 -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld +else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< +endif ####################################################################### # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage_null.ld +else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld $(romstage-objs) +endif $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage_xip.ld +else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld $(romstage-objs) +endif $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n"

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Patch set updated for coreboot: e7067cb Use ld manually when compiling with clang
by Patrick Georgi 29 May '12

29 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/785 -gerrit commit e7067cbbaa642694d06d8652c35a8562ef87aba7 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Mar 11 20:15:21 2012 +0100 Use ld manually when compiling with clang clang does its own linking, incompatible to our binutils-centric linker magic. Change-Id: I243597adcb6bc3f7343c3431d7473610c327353d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/Makefile.inc | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 9739555..6b13c04 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -149,11 +149,19 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @printf " CC $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_CLANG),y) + $(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/coreboot_ram.ld +else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $< +endif $(objgenerated)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(objgenerated)/ramstage.a $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_CLANG),y) + $(LD) -m elf_i386 -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(objgenerated)/ramstage.a $(LIBGCC_FILE_NAME) --end-group +else $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(objgenerated)/ramstage.a $(LIBGCC_FILE_NAME) -Wl,--end-group +endif $(objgenerated)/ramstage.a: $$(ramstage-objs) @printf " AR $(subst $(obj)/,,$(@))\n" @@ -311,18 +319,30 @@ $(objgenerated)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOC $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_CLANG),y) + $(LD) -m elf_i386 -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld +else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< +endif ####################################################################### # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_CLANG),y) + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage_null.ld +else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld $(romstage-objs) +endif $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld @printf " LINK $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_CLANG),y) + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage_xip.ld +else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld $(romstage-objs) +endif $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n"

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No parallel port set up on Alix 1D board
by Joao Bonina 29 May '12

29 May '12

Hello Paul, sorry about that. I'm attaching the serial console debug, as well as the dmesg output. I'm using coreboot v4.0-2408-gad422c0 SeaBIOS is version -20120527_232947-debian (as outputted by SeaBIOS build). Distribution is Debian Squeeze, and kernel version is 2.6.38-bpo.2-486. Thanks in advance! ----- Original Message ----- From: Paul Menzel <paulepanter(a)users.sourceforge.net> To: Joao Bonina <bonina_2001(a)yahoo.com> Cc: coreboot(a)coreboot.org Sent: Sunday, 27 May 2012, 13:34 Subject: Re: [coreboot] No parallel port set up on Alix 1D board Dear Joao, at first, could you in the future please just send plain text messages to the list [1][2]? That would be awesome. Am Sonntag, den 27.05.2012, 04:55 -0700 schrieb Joao Bonina: > I just started using coreboot with SeaBIOS as payload on an Alix 1D > board and began testing functionality. > > I noticed that the parallel port isn't working (the /dev/parport0 > isn't created), and parallel port support is selected in coreboot's > config. > > Anyone have any clues or hints? Unfortunately you do not provide enough information for developers to help you. Please tell them the coreboot version, the SeaBIOS version, the distribution and so and on. Also please attach coreboot’s debugging output and the Linux kernel messages. Thanks, Paul [1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette [2] http://mailformat.dan.info/config/yahoo.html -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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Patch merged into coreboot/master: a9f436f Drop config variable CPU_MODEL_INDEX
by gerrit＠coreboot.org 29 May '12

29 May '12

the following patch was just integrated into master: commit a9f436fa6f13d46f9d4a2b9f4f849a3f828ab5cd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 11 16:30:54 2012 -0700 Drop config variable CPU_MODEL_INDEX It's only used in the ACPI generator for Sandybridge/Ivybridge CPUs and the code can easily be changed to not rely on any Kconfig magic. Change-Id: Ie2f92edfe8908f7eb2fda3088f77ad22f491ddcf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue May 29 19:55:40 2012, giving +2 See http://review.coreboot.org/1047 for details. -gerrit

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Patch merged into coreboot/master: 3255dae Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled
by gerrit＠coreboot.org 29 May '12

29 May '12

the following patch was just integrated into master: commit 3255dae09981daa753118fd3f9cd46dbd071001a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 22 15:24:51 2012 -0700 Fix compilation with CONFIG_DEBUG_SPI_FLASH enabled Right now coreboot compilation fails when SPI flash debugging is enabled. Fix it by using the right set of memory functions. Change-Id: I5e372c4a5df53b4d46aaed9e251e5205ff68cb5b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue May 29 11:29:54 2012, giving +2 See http://review.coreboot.org/1044 for details. -gerrit

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Patch merged into coreboot/master: a050f7e Fix full reset for Ivy Bridge platforms
by gerrit＠coreboot.org 29 May '12

29 May '12

the following patch was just integrated into master: commit a050f7eef23798440022face8181eb0598b4363e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 17 17:21:27 2012 -0700 Fix full reset for Ivy Bridge platforms Experiments have shown that writing plain value of 6 at byte io address of 0xcf9 causes the systems to reset and reboot reliably. Change-Id: Ie900e4b4014cded868647372b027918b7ff72578 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue May 29 11:29:24 2012, giving +2 See http://review.coreboot.org/1050 for details. -gerrit

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Patch merged into coreboot/master: 7993afd ChromeOS: Remove remnants of FDT support
by gerrit＠coreboot.org 29 May '12

29 May '12

the following patch was just integrated into master: commit 7993afd7b1bb29dd3bcbc4ea3f56232ff30998be Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 14:20:18 2012 -0700 ChromeOS: Remove remnants of FDT support Originally, on ChromeBooks, coreboot would provide a modified u-boot device tree (FDT) to u-boot in CBMEM. However, u-boot can now create all the information it needs from the coreboot table and add it to its device tree itself. This means we can drop this (anyways unused) code. Change-Id: I4ab20bbb8525e7349b18764aa202bbe81958d06a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue May 29 11:28:42 2012, giving +2 See http://review.coreboot.org/1052 for details. -gerrit

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Patch merged into coreboot/master: 63acdad Sandybridge: Remove remnants of FDT support from MRC cache code
by gerrit＠coreboot.org 29 May '12

29 May '12

the following patch was just integrated into master: commit 63acdad535f94580b137661a97a99264c5d00541 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 14:16:47 2012 -0700 Sandybridge: Remove remnants of FDT support from MRC cache code Originally, ChromeBooks would get the offset of the MRC cache from an entry in the u-boot device tree. Not everyone wants to use u-boot on Sandybridge systems, however. Since the new code (based on Kconfig) is now fully working, we can drop the u-boot device tree remnants. Change-Id: I4e012ea981f16dce9a4d155254facd29874b28ef Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue May 29 11:27:41 2012, giving +2 See http://review.coreboot.org/1051 for details. -gerrit

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Patch merged into coreboot/master: 1560649 Sandybridge: Fix MRC cache calculation
by gerrit＠coreboot.org 29 May '12

29 May '12

the following patch was just integrated into master: commit 15606496889239bcfa231ed416b7a1f34033ccb7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 11:21:10 2012 -0700 Sandybridge: Fix MRC cache calculation The MRC region is described by Kconfig variables, no further math or parsing is required at this point. Change-Id: I290d8788b69ef007e9ea2317ce55aefa2d791883 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue May 29 11:26:31 2012, giving +2 See http://review.coreboot.org/1046 for details. -gerrit

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coreboot May 2012