coreboot May 2012

coreboot@coreboot.org

31 participants
287 discussions

New patch to review for coreboot: 99a57ad Improve parsing of --cpu parameter in abuild script.
by Raymond Danks 31 May '12

31 May '12

Raymond Danks (ray.danks(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1068 -gerrit commit 99a57ad9cf6a565e9343c4bdd43de4ed34111b66 Author: Raymond Danks <ray.danks(a)se-eng.com> Date: Wed May 30 16:03:48 2012 -0600 Improve parsing of --cpu parameter in abuild script. * -c "" need never be tested if getopt params are handled; fail abuild script when getopt parsing fails * use expr to resolve numeric test fails with -c max * cpus variable may be being passed in the environment. Don't overwrite MAKEFLAGS if it is not. Change-Id: I96236ef719a1a9f942b8e15bfcf015d60068e58a Signed-off-by: Raymond Danks <ray.danks(a)se-eng.com> --- util/abuild/abuild | 11 +++++------ 1 files changed, 5 insertions(+), 6 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 65d9cea..dfd520f 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -527,7 +527,7 @@ cmdline="$* -c 1" getoptbrand="`getopt -V`" if [ "${getoptbrand:0:6}" == "getopt" ]; then # Detected GNU getopt that supports long options. - args=`getopt -l version,verbose,help,all,target:,payloads:,test,cpus:,silent,junit,xml,config,loglevel:,remove,prefix:,update,nostackprotect,scan-build,ccache,blobs -o Vvhat:p:Tc:sJxCl:rP:uyB -- "$@"` + args=`getopt -l version,verbose,help,all,target:,payloads:,test,cpus:,silent,junit,xml,config,loglevel:,remove,prefix:,update,nostackprotect,scan-build,ccache,blobs -o Vvhat:p:Tc:sJxCl:rP:uyB -- "$@"` || exit 1 eval set -- $args else # Detected non-GNU getopt @@ -556,10 +556,9 @@ while true ; do -T|--test) shift; hwtest=true;; -c|--cpus) shift export MAKEFLAGS="-j $1" - test "$MAKEFLAGS" == "-j max" && export MAKEFLAGS="-j" - test "$1" == "" && cpuconfig="in parallel" + test "$MAKEFLAGS" == "-j max" && export MAKEFLAGS="-j" && cpuconfig="in parallel" test "$1" == "1" && cpuconfig="on 1 cpu" - test 0$1 -gt 1 && cpuconfig="on $1 cpus in parallel" + expr "$1" : '-\?[0-9]\+$' > /dev/null && test 0$1 -gt 1 && cpuconfig="on $1 cpus in parallel" shift;; -s|--silent) shift; silent="-s";; -ns|--nostackprotect) shift; stackprotect=true;; @@ -607,12 +606,12 @@ USE_XARGS=0 if [ "$cpus" != "1" ]; then if [ "$target" = "" ]; then # Test if xargs supports the non-standard -P flag - # FIXME: disabled until we managed to eliminate all the make(1) quirks - echo | xargs -P 0$cpus -n 1 echo 2>/dev/null >/dev/null # && USE_XARGS=1 + echo | xargs -P 0$cpus -n 1 echo 2>/dev/null >/dev/null && USE_XARGS=1 fi fi if [ "$USE_XARGS" = "0" ]; then +test "$MAKEFLAGS" == "" && test "$cpus" != "" && export MAKEFLAGS="-j $cpus" build_all_targets() { for VENDOR in $( vendors ); do

1 0

Patch merged into coreboot/master: d45a87a Initializer of a static member in union.
by gerrit＠coreboot.org 30 May '12

30 May '12

the following patch was just integrated into master: commit d45a87a4461dc78c19b9c7ab89968abf911e91a7 Author: zbao <fishbaozi(a)gmail.com> Date: Tue May 29 14:59:38 2012 +0800 Initializer of a static member in union. It is just me or does anybody have the same build error without this patch? ------ src/arch/x86/boot/acpigen.c: In function 'acpigen_write_empty_PTC': src/arch/x86/boot/acpigen.c:347:3: error: unknown field 'resv' specified in initializer src/arch/x86/boot/acpigen.c:347:3: warning: missing braces around initializer src/arch/x86/boot/acpigen.c:347:3:warning: (near initialization for 'addr.<anonymous>') ------- Anyway, I believe at least this will cause warnings. "resv" is a member of a union, not of acpi_addr_t. So it should be wrapped by a brace in the initializer. Change-Id: I72624386816c987d5bb2d3a3a64c7c58eb9af389 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue May 29 07:57:18 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue May 29 19:45:05 2012, giving +2 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Wed May 30 23:01:23 2012, giving +2 See http://review.coreboot.org/1056 for details. -gerrit

1 0

Patch merged into coreboot/master: 856a155 sconfig: Some fixes
by gerrit＠coreboot.org 30 May '12

30 May '12

the following patch was just integrated into master: commit 856a15569d36eba648c8b9f544442703216a59a6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed May 30 16:26:30 2012 +0200 sconfig: Some fixes clang complained about a missing include and wrong fprintf use. Change-Id: Idc023b653e694147c624d5f8f9ed3b797c462e9f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Wed May 30 17:27:39 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed May 30 19:43:01 2012, giving +2 See http://review.coreboot.org/1067 for details. -gerrit

1 0

New patch to review for coreboot: 856a155 sconfig: Some fixes
by Patrick Georgi 30 May '12

30 May '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1067 -gerrit commit 856a15569d36eba648c8b9f544442703216a59a6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed May 30 16:26:30 2012 +0200 sconfig: Some fixes clang complained about a missing include and wrong fprintf use. Change-Id: Idc023b653e694147c624d5f8f9ed3b797c462e9f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/sconfig/main.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 181be38..5d97274 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ +#include <ctype.h> #include "sconfig.h" #include "sconfig.tab.h" @@ -336,7 +337,7 @@ static void pass0(FILE *fil, struct device *ptr) { static void pass1(FILE *fil, struct device *ptr) { if (!ptr->used && (ptr->type == device)) { if (ptr->id != 0) - fprintf(fil, "static ", ptr->name); + fprintf(fil, "static "); fprintf(fil, "struct device %s = {\n", ptr->name); fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0"); fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, ptr->bus->link); @@ -358,7 +359,7 @@ static void pass1(FILE *fil, struct device *ptr) { if (ptr->children || ptr->multidev) fprintf(fil, "\t.link_list = &%s_links[0],\n", ptr->name); else - fprintf(fil, "\t.link_list = NULL,\n", ptr->name); + fprintf(fil, "\t.link_list = NULL,\n"); if (ptr->sibling) fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name); if (ptr->chip->chiph_exists) {

1 0

Re: [coreboot] No parallel port set up on Alix 1D board
by Joao Bonina 30 May '12

30 May '12

Thank you. I'm analysing the source code for the Winbond W83627HF chip, to see if I can do something about it. Best regards, Joao Bonina ________________________________ From: QingPei Wang <wangqingpei(a)gmail.com> To: Joao Bonina <bonina_2001(a)yahoo.com> Cc: Marc Jones <marcj303(a)gmail.com>; "paulepanter(a)users.sourceforge.net" <paulepanter(a)users.sourceforge.net>; "coreboot(a)coreboot.org" <coreboot(a)coreboot.org> Sent: Wednesday, 30 May 2012, 5:34 Subject: Re: [coreboot] No parallel port set up on Alix 1D board you can check your SIO code under coreboot/src/superio/(chip brand)/chip/* . it seems the parallel port are not configured correctly. Best wishes QingPei Wang Phone: 86+018930528086 On Wed, May 30, 2012 at 3:04 AM, Joao Bonina <bonina_2001(a)yahoo.com> wrote: Hello Marc, > > >can you give me some pointers on that? Is there a tutorial or information resource for that? > > > >Where could I check the SIO code for that? > > >Thanks, >Joao > > > >________________________________ > From: Marc Jones <marcj303(a)gmail.com> >To: Joao Bonina <bonina_2001(a)yahoo.com> >Cc: "paulepanter(a)users.sourceforge.net" <paulepanter(a)users.sourceforge.net>; "coreboot(a)coreboot.org" <coreboot(a)coreboot.org> >Sent: Tuesday, 29 May 2012, 19:58 > >Subject: Re: [coreboot] No parallel port set up on Alix 1D board > > >On Sun, May 27, 2012 at 5:30 PM, Joao Bonina <bonina_2001(a)yahoo.com> wrote: >> >> >> Hello Paul, >> >> >> sorry about that. >> >> I'm attaching the serial console debug, as well as the dmesg output. >> >> I'm using coreboot v4.0-2408-gad422c0 >> >> SeaBIOS is version -20120527_232947-debian (as outputted by SeaBIOS build). >> >> Distribution is Debian Squeeze, and kernel version is 2.6.38-bpo.2-486. >> >> Thanks in advance! >> >> >> >> >> ----- Original Message ----- >> From: Paul Menzel <paulepanter(a)users.sourceforge.net> >> To: Joao Bonina <bonina_2001(a)yahoo.com> >> Cc: coreboot(a)coreboot.org >> Sent: Sunday, 27 May 2012, 13:34 >> Subject: Re: [coreboot] No parallel port set up on Alix 1D board >> >> Dear Joao, >> >> >> at first, could you in the future please just send plain text messages >> to the list [1][2]? That would be awesome. >> >> Am Sonntag, den 27.05.2012, 04:55 -0700 schrieb Joao Bonina: >> >>> I just started using coreboot with SeaBIOS as payload on an Alix 1D >>> board and began testing functionality. >>> >>> I noticed that the parallel port isn't working (the /dev/parport0 >>> isn't created), and parallel port support is selected in coreboot's >>> config. >>> >>> Anyone have any clues or hints? >> >> Unfortunately you do not provide enough information for developers to >> help you. Please tell them the coreboot version, the SeaBIOS version, >> the distribution and so and on. >> >> Also please attach coreboot’s debugging output and the Linux kernel >> messages. >> >> >> Thanks, >> >> Paul >> >> >> [1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette >> [2] http://mailformat.dan.info/config/yahoo.html >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > >The error is in your log: >PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io >PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq >ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned > >You'll need to see what is going on in the SIO code for that device. >The setting is done in the mainboard devicetree.cb. > >Marc > > > >-- >http://se-eng.com > > > >-- >coreboot mailing list: coreboot(a)coreboot.org >http://www.coreboot.org/mailman/listinfo/coreboot > -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

1 0

Patch merged into coreboot/master: 36c386f Fix the location of "Setting variable MTRR" printk.
by gerrit＠coreboot.org 30 May '12

30 May '12

the following patch was just integrated into master: commit 36c386f5387d0726be59db2193edd62cb3880136 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat May 26 00:13:22 2012 +0200 Fix the location of "Setting variable MTRR" printk. Without that fix the debugging is harder because the person debugging coreboot will see the following twice(note the repeated MTRR number): Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB [...] Setting variable MTRR 1, base: 4096MB, range: 512MB, type WB Setting variable MTRR 1, base: 4608MB, range: 256MB, type WB Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC instead of the following twice: Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB [...] Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC Thanks to kmalkki on #coreboot's Freenode IRC channel for the idea: May 25 23:57:17 <kmalkki> I would add (move) that "Setting variable MTRR..." debug at the end of set_var_mtrrs() Change-Id: I9f4b7110ba34d017a58d8cc5fb06a7b1c3d0c8aa Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> See http://review.coreboot.org/1058 for details. -gerrit

1 0

Re: [coreboot] No parallel port set up on Alix 1D board
by Joao Bonina 30 May '12

30 May '12

Hello Marc, can you give me some pointers on that? Is there a tutorial or information resource for that? Where could I check the SIO code for that? Thanks, Joao ________________________________ From: Marc Jones <marcj303(a)gmail.com> To: Joao Bonina <bonina_2001(a)yahoo.com> Cc: "paulepanter(a)users.sourceforge.net" <paulepanter(a)users.sourceforge.net>; "coreboot(a)coreboot.org" <coreboot(a)coreboot.org> Sent: Tuesday, 29 May 2012, 19:58 Subject: Re: [coreboot] No parallel port set up on Alix 1D board On Sun, May 27, 2012 at 5:30 PM, Joao Bonina <bonina_2001(a)yahoo.com> wrote: > > > Hello Paul, > > > sorry about that. > > I'm attaching the serial console debug, as well as the dmesg output. > > I'm using coreboot v4.0-2408-gad422c0 > > SeaBIOS is version -20120527_232947-debian (as outputted by SeaBIOS build). > > Distribution is Debian Squeeze, and kernel version is 2.6.38-bpo.2-486. > > Thanks in advance! > > > > > ----- Original Message ----- > From: Paul Menzel <paulepanter(a)users.sourceforge.net> > To: Joao Bonina <bonina_2001(a)yahoo.com> > Cc: coreboot(a)coreboot.org > Sent: Sunday, 27 May 2012, 13:34 > Subject: Re: [coreboot] No parallel port set up on Alix 1D board > > Dear Joao, > > > at first, could you in the future please just send plain text messages > to the list [1][2]? That would be awesome. > > Am Sonntag, den 27.05.2012, 04:55 -0700 schrieb Joao Bonina: > >> I just started using coreboot with SeaBIOS as payload on an Alix 1D >> board and began testing functionality. >> >> I noticed that the parallel port isn't working (the /dev/parport0 >> isn't created), and parallel port support is selected in coreboot's >> config. >> >> Anyone have any clues or hints? > > Unfortunately you do not provide enough information for developers to > help you. Please tell them the coreboot version, the SeaBIOS version, > the distribution and so and on. > > Also please attach coreboot’s debugging output and the Linux kernel > messages. > > > Thanks, > > Paul > > > [1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette > [2] http://mailformat.dan.info/config/yahoo.html > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot The error is in your log: PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned You'll need to see what is going on in the SIO code for that device. The setting is done in the mainboard devicetree.cb. Marc -- http://se-eng.com

2 1

Patch merged into coreboot/master: 3a99e2c Provide functions to access arbitrary GPIO pins and vectors
by gerrit＠coreboot.org 30 May '12

30 May '12

the following patch was just integrated into master: commit 3a99e2cd0443e017d6978930db98ad579af5a93f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 15 14:18:59 2012 -0700 Provide functions to access arbitrary GPIO pins and vectors This change adds utility functions which allow to read any GPIO pin, as well as a vector of GPIO pin values. As presented, these functions will be available to Sandy Bridge and Ivy Bridge systems only. There is no error checking: trying to read GPIO pin number which exceeds actual number of pins will return zero, trying to read GPIO which is not actually configured as such will return unpredictable value. When reading a GPIO pin vector, the pin numbers are passed in an array, terminated by -1. For instance, to read GPIO pins 4, 2, 15 as a three bit number GPIO4 * 4 + GPIO2 * 2 + GPIO15 * 1, one should pass pointer to array of {4, 2, 15, -1}. Change-Id: I042c12dbcb3c46d14ed864a48fc37d54355ced7d Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Build-Tested: build bot (Jenkins) at Sat May 26 01:50:10 2012, giving +1 See http://review.coreboot.org/1049 for details. -gerrit

1 0

Patch merged into coreboot/master: a770d5e Add support for Panther Point to SPI driver
by gerrit＠coreboot.org 30 May '12

30 May '12

the following patch was just integrated into master: commit a770d5e34857f2641e973806f64aad6364ed6fbb Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 11:18:35 2012 -0700 Add support for Panther Point to SPI driver Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sat May 26 00:07:43 2012, giving +1 See http://review.coreboot.org/1048 for details. -gerrit

1 0

Patch merged into coreboot/master: d655d68 Use ld manually when compiling with clang
by gerrit＠coreboot.org 29 May '12

29 May '12

the following patch was just integrated into master: commit d655d6881dbb3a69f66486e7d1b6074f9bfe0805 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Mar 11 20:15:21 2012 +0100 Use ld manually when compiling with clang clang does its own linking, incompatible to our binutils-centric linker magic. Change-Id: I243597adcb6bc3f7343c3431d7473610c327353d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/785 for details. -gerrit

1 0

← Newer
1
2
3
4
5
6
7
...
29
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot May 2012