coreboot May 2012

coreboot@coreboot.org

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287 discussions

New patch to review for coreboot: d45a87a Initializer of a static member in union.
by Zheng Bao 29 May '12

29 May '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1056 -gerrit commit d45a87a4461dc78c19b9c7ab89968abf911e91a7 Author: zbao <fishbaozi(a)gmail.com> Date: Tue May 29 14:59:38 2012 +0800 Initializer of a static member in union. It is just me or does anybody have the same build error without this patch? ------ src/arch/x86/boot/acpigen.c: In function 'acpigen_write_empty_PTC': src/arch/x86/boot/acpigen.c:347:3: error: unknown field 'resv' specified in initializer src/arch/x86/boot/acpigen.c:347:3: warning: missing braces around initializer src/arch/x86/boot/acpigen.c:347:3:warning: (near initialization for 'addr.<anonymous>') ------- Anyway, I believe at least this will cause warnings. "resv" is a member of a union, not of acpi_addr_t. So it should be wrapped by a brace in the initializer. Change-Id: I72624386816c987d5bb2d3a3a64c7c58eb9af389 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index e7a297d..71aa10c 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -344,7 +344,9 @@ int acpigen_write_empty_PTC(void) .space_id = ACPI_ADDRESS_SPACE_FIXED, .bit_width = 0, .bit_offset = 0, - .resv = 0, + { + .resv = 0 + }, .addrl = 0, .addrh = 0, };

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Patch merged into coreboot/master: 241e572 Enable USE_OPTION_TABLE for ThinkPad X60
by gerrit＠coreboot.org 28 May '12

28 May '12

the following patch was just integrated into master: commit 241e57244fe64f0a3b15f72972129ebaacd75d2f Author: Motiejus Jakštys <desired.mta(a)gmail.com> Date: Tue May 1 21:47:16 2012 +0100 Enable USE_OPTION_TABLE for ThinkPad X60 Without this option bluetooth configuration value in nvram is not consulted properly. It also enables built-in volume control (read-only). Tested on: ThinkPad X60s, 1702. Change-Id: I2fc6bb527c6e086a083e63922d1253eda7d4a36d Signed-off-by: Motiejus Jakštys <desired.mta(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue May 1 23:26:37 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Mon May 28 21:14:19 2012, giving +2 See http://review.coreboot.org/985 for details. -gerrit

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Trac reminder: list of new ticket(s)
by coreboot tracker 28 May '12

28 May '12

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Parallel port on Alix 1D board
by Joao Bonina 27 May '12

27 May '12

Hello All, I just started using coreboot with SeaBIOS as payload on an Alix 1D board and began testing functionality. I noticed that the parallel port isn't working (the /dev/parport0 isn't created), and parallel port support is selected in coreboot's config. Anyone have any clues or hints? Thanks in advance!

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Patch merged into coreboot/master: ae114e9 Implement %zu / %zd in printk
by gerrit＠coreboot.org 26 May '12

26 May '12

the following patch was just integrated into master: commit ae114e94989a273015a758ffcd4260d88be8050f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 15 13:28:07 2012 -0700 Implement %zu / %zd in printk The SPI drivers from u-boot make heavy use of %zu/%zd (size_t/ssize_t). Implement this in our printk implementation so we get useful output. Change-Id: I91798ff4f28b9c3cd4db204c7ec503596d247dcd Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat May 26 07:16:39 2012, giving +2 See http://review.coreboot.org/1043 for details. -gerrit

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Patch merged into coreboot/master: 1d0ab4d Move subsystem IDs to devicetree.cb
by gerrit＠coreboot.org 26 May '12

26 May '12

the following patch was just integrated into master: commit 1d0ab4d60b763fe740e4ae94d0dd4ca692286494 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 15 12:36:57 2012 -0700 Move subsystem IDs to devicetree.cb A while back coreboot was changed to read the subsystem IDs from devicetree.cb to allow each onboard PCI device to have its own subsystem id. When we originally branched, this was not the case, and the sandybridge/ivybridge mainboards have not been updated yet. Also, drop the subsystem ID from Emerald Lake 2, since it's not a Google device. Change-Id: Ie96fd67cd2ff65ad6ff725914e3bad843e78712e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat May 26 07:16:00 2012, giving +2 See http://review.coreboot.org/1042 for details. -gerrit

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Patch merged into coreboot/master: f394b77 Reduce default verbosity of SPI flash drivers
by gerrit＠coreboot.org 25 May '12

25 May '12

the following patch was just integrated into master: commit f394b77b035c83008bdc67a6ff532ae587267dd2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 11:03:29 2012 -0700 Reduce default verbosity of SPI flash drivers Only print PP: lines if CONFIG_DEBUG_SPI_FLASH is enabled. Change-Id: If25e916ecb585f37c90d42980e933a6cd1a3d956 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri May 25 23:22:53 2012, giving +1 See http://review.coreboot.org/1045 for details. -gerrit

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Patch merged into coreboot/master: 1ef774a Fix printk types in SPI flash drivers
by gerrit＠coreboot.org 25 May '12

25 May '12

the following patch was just integrated into master: commit 1ef774ab8232f66de72fb2dcd796ee819476b213 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 14 13:52:32 2012 -0700 Fix printk types in SPI flash drivers - use %zu instead of %zd for size_t (%zd is for ssize_t) - use %x instead of %lx for u32 - break some long lines to avoid commit hook trouble Change-Id: Idfad716523dbcd2a595d26317240e972b5253e8b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri May 25 23:08:15 2012, giving +1 See http://review.coreboot.org/1041 for details. -gerrit

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Patch set updated for coreboot: 7993afd ChromeOS: Remove remnants of FDT support
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1052 -gerrit commit 7993afd7b1bb29dd3bcbc4ea3f56232ff30998be Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 23 14:20:18 2012 -0700 ChromeOS: Remove remnants of FDT support Originally, on ChromeBooks, coreboot would provide a modified u-boot device tree (FDT) to u-boot in CBMEM. However, u-boot can now create all the information it needs from the coreboot table and add it to its device tree itself. This means we can drop this (anyways unused) code. Change-Id: I4ab20bbb8525e7349b18764aa202bbe81958d06a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/vendorcode/google/chromeos/gnvs.c | 42 --------------------------------- src/vendorcode/google/chromeos/gnvs.h | 1 - 2 files changed, 0 insertions(+), 43 deletions(-) diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 6b545f4..024dbf8 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -34,48 +34,6 @@ void chromeos_init_vboot(chromeos_acpi_t *chromeos) memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh)); } -void chromeos_set_vboot_data_ptr(void *blob) -{ - /* This code has to be rewritten to pass the vboot table - * pointer through the coreboot table instead of the - * FDT, since FDT support was rejected upstream. For now - * just make the code available for reference. - */ -#if 0 // CONFIG_ADD_FDT - int node_offset, addr_cell_len; - const u32 *cell; - uintptr_t table_addr = (uintptr_t)vboot_data; - u32 table_addr32; - u64 table_addr64; - void *table_ptr; - - cell = fdt_getprop(blob, 0, "#address-cells", NULL); - if (cell && *cell == 2) { - addr_cell_len = 8; - table_addr64 = cpu_to_fdt64(table_addr); - table_ptr = &table_addr64; - } else { - addr_cell_len = 4; - table_addr32 = cpu_to_fdt32(table_addr); - table_ptr = &table_addr32; - } - - node_offset = fdt_path_offset(blob, "/chromeos-config"); - if (node_offset < 0) { - printk(BIOS_ERR, - "Couldn't find /chromeos-config in the fdt.\n"); - return; - } - - if (fdt_setprop(blob, node_offset, "gnvs-vboot-table", - table_ptr, addr_cell_len) < 0) { - printk(BIOS_ERR, "Couldn't set gnvs-vboot-table.\n"); - } -#else - printk(BIOS_ERR, "Can't set gnvs-vboot-table.\n"); -#endif -} - void chromeos_set_me_hash(u32 *hash, int len) { if ((len*sizeof(u32)) > sizeof(vboot_data->mehh)) diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 36922ba..6dd740f 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -63,7 +63,6 @@ typedef struct { extern chromeos_acpi_t *vboot_data; void chromeos_init_vboot(chromeos_acpi_t *chromeos); -void chromeos_set_vboot_data_ptr(void *); void chromeos_set_me_hash(u32*, int); #endif

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Patch set updated for coreboot: a050f7e Fix full reset for Ivy Bridge platforms
by Stefan Reinauer 25 May '12

25 May '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1050 -gerrit commit a050f7eef23798440022face8181eb0598b4363e Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 17 17:21:27 2012 -0700 Fix full reset for Ivy Bridge platforms Experiments have shown that writing plain value of 6 at byte io address of 0xcf9 causes the systems to reset and reboot reliably. Change-Id: Ie900e4b4014cded868647372b027918b7ff72578 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/southbridge/intel/bd82x6x/reset.c | 9 --------- 1 files changed, 0 insertions(+), 9 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c index 29b69ff..5324142 100644 --- a/src/southbridge/intel/bd82x6x/reset.c +++ b/src/southbridge/intel/bd82x6x/reset.c @@ -26,16 +26,7 @@ void soft_reset(void) outb(0x04, 0xcf9); } -#if 0 void hard_reset(void) { - /* Try rebooting through port 0xcf9. */ - outb((1 << 2) | (1 << 1), 0xcf9); -} -#endif - -void hard_reset(void) -{ - outb(0x02, 0xcf9); outb(0x06, 0xcf9); }

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coreboot May 2012