coreboot April 2012

coreboot@coreboot.org

39 participants
459 discussions

Patch merged into coreboot/master: dda4cff Revamp Intel microcode update code
by gerrit＠coreboot.org 25 Apr '12

25 Apr '12

the following patch was just integrated into master: commit dda4cfface9283ef98fa0c898be7a2464c2919e2 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 25 22:58:23 2012 +0200 Revamp Intel microcode update code - add GPLv2 + copyright header after talking to Ron - "bits" in struct microcode served no real purpose but getting its address taken. Hence drop it - use asm volatile instead of __asm__ volatile - drop superfluous wrmsr (that seems to be harmless but is still wrong) in read_microcode_rev - use u32 instead of unsigned int where appropriate - make code usable both in bootblock and in ramstage - drop ROMCC style print_debug statements - drop microcode update copy in Sandybridge bootblock Change-Id: Iec4d5c7bfac210194caf577e8d72446e6dfb4b86 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Apr 25 23:51:47 2012, giving +1 See http://review.coreboot.org/928 for details. -gerrit

1 0

Patch set updated for coreboot: dda4cff Revamp Intel microcode update code
by Stefan Reinauer 25 Apr '12

25 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/928 -gerrit commit dda4cfface9283ef98fa0c898be7a2464c2919e2 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 25 22:58:23 2012 +0200 Revamp Intel microcode update code - add GPLv2 + copyright header after talking to Ron - "bits" in struct microcode served no real purpose but getting its address taken. Hence drop it - use asm volatile instead of __asm__ volatile - drop superfluous wrmsr (that seems to be harmless but is still wrong) in read_microcode_rev - use u32 instead of unsigned int where appropriate - make code usable both in bootblock and in ramstage - drop ROMCC style print_debug statements - drop microcode update copy in Sandybridge bootblock Change-Id: Iec4d5c7bfac210194caf577e8d72446e6dfb4b86 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/microcode/microcode.c | 79 ++++++++++++++++++----------- src/cpu/intel/model_206ax/bootblock.c | 89 +-------------------------------- src/include/cpu/intel/microcode.h | 21 ++++++++ 3 files changed, 71 insertions(+), 118 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 9a80077..91f7762 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -1,6 +1,24 @@ -/* microcode.c: Microcode update for PIII and later CPUS +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* Microcode update for Intel PIII and later CPUs */ + #include <stdint.h> #include <console/console.h> #include <cpu/cpu.h> @@ -9,30 +27,28 @@ struct microcode { u32 hdrver; /* Header Version */ - u32 rev; /* Patch ID */ - u32 date; /* DATE */ - u32 sig; /* CPUID */ + u32 rev; /* Update Revision */ + u32 date; /* Date */ + u32 sig; /* Processor Signature */ - u32 cksum; /* Checksum */ - u32 ldrver; /* Loader Version */ - u32 pf; /* Platform ID */ + u32 cksum; /* Checksum */ + u32 ldrver; /* Loader Revision */ + u32 pf; /* Processor Flags */ - u32 data_size; /* Data size */ - u32 total_size; /* Total size */ + u32 data_size; /* Data Size */ + u32 total_size; /* Total Size */ u32 reserved[3]; - u32 bits[1012]; }; static inline u32 read_microcode_rev(void) { - /* Some Intel Cpus can be very finicky about the + /* Some Intel CPUs can be very finicky about the * CPUID sequence used. So this is implemented in * assembly so that it works reliably. */ msr_t msr; - __asm__ volatile ( - "wrmsr\n\t" + asm volatile ( "xorl %%eax, %%eax\n\t" "xorl %%edx, %%edx\n\t" "movl $0x8b, %%ecx\n\t" @@ -52,14 +68,14 @@ static inline u32 read_microcode_rev(void) void intel_update_microcode(const void *microcode_updates) { - unsigned int eax; - unsigned int pf, rev, sig; + u32 eax; + u32 pf, rev, sig; unsigned int x86_model, x86_family; const struct microcode *m; const char *c; msr_t msr; - /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0; wrmsr(0x8B, msr); @@ -75,35 +91,38 @@ void intel_update_microcode(const void *microcode_updates) msr = rdmsr(0x17); pf = 1 << ((msr.hi >> 18) & 7); } - print_debug("microcode_info: sig = 0x"); - print_debug_hex32(sig); - print_debug(" pf=0x"); - print_debug_hex32(pf); - print_debug(" rev = 0x"); - print_debug_hex32(rev); - print_debug("\n"); +#if !defined(__ROMCC__) + /* If this code is compiled with ROMCC we're probably in + * the bootblock and don't have console output yet. + */ + printk(BIOS_DEBUG, "microcode_info: sig=0x%08x pf=0x%08x rev=0x%08x\n", + sig, pf, rev); +#endif m = microcode_updates; - for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { + for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { if ((m->sig == sig) && (m->pf & pf)) { unsigned int new_rev; - msr.lo = (unsigned long)(&m->bits) & 0xffffffff; + msr.lo = (unsigned long)c + sizeof(struct microcode); msr.hi = 0; wrmsr(0x79, msr); /* Read back the new microcode version */ new_rev = read_microcode_rev(); - print_debug("microcode updated to revision: "); - print_debug_hex32(new_rev); - print_debug(" from revision "); - print_debug_hex32(rev); - print_debug("\n"); +#if !defined(__ROMCC__) + printk(BIOS_DEBUG, "microcode updated to revision: " + "%08x from revision %08x\n", new_rev, rev); +#endif break; } + if (m->total_size) { c += m->total_size; } else { +#if !defined(__ROMCC__) + printk(BIOS_WARNING, "Microcode has no valid size field!\n"); +#endif c += 2048; } } diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 7925315..9549d23 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -27,94 +27,7 @@ static const uint32_t microcode_updates[] = { #include "x06_microcode.h" }; -struct microcode { - u32 hdrver; /* Header Version */ - u32 rev; /* Patch ID */ - u32 date; /* DATE */ - u32 sig; /* CPUID */ - - u32 cksum; /* Checksum */ - u32 ldrver; /* Loader Version */ - u32 pf; /* Platform ID */ - - u32 data_size; /* Data size */ - u32 total_size; /* Total size */ - - u32 reserved[3]; - u32 bits[1012]; -}; - -static inline u32 read_microcode_rev(void) -{ - /* Some Intel Cpus can be very finicky about the - * CPUID sequence used. So this is implemented in - * assembly so that it works reliably. - */ - msr_t msr; - __asm__ volatile ( - "wrmsr\n\t" - "xorl %%eax, %%eax\n\t" - "xorl %%edx, %%edx\n\t" - "movl $0x8b, %%ecx\n\t" - "wrmsr\n\t" - "movl $0x01, %%eax\n\t" - "cpuid\n\t" - "movl $0x08b, %%ecx\n\t" - "rdmsr \n\t" - : /* outputs */ - "=a" (msr.lo), "=d" (msr.hi) - : /* inputs */ - : /* trashed */ - "ecx" - ); - return msr.hi; -} - -void intel_update_microcode(const void *microcode_updates) -{ - unsigned int eax; - unsigned int pf, rev, sig; - unsigned int x86_model, x86_family; - const struct microcode *m; - const char *c; - msr_t msr; - - /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ - msr.lo = 0; - msr.hi = 0; - wrmsr(0x8B, msr); - eax = cpuid_eax(1); - msr = rdmsr(0x8B); - rev = msr.hi; - x86_model = (eax >>4) & 0x0f; - x86_family = (eax >>8) & 0x0f; - sig = eax; - - pf = 0; - if ((x86_model >= 5)||(x86_family>6)) { - msr = rdmsr(0x17); - pf = 1 << ((msr.hi >> 18) & 7); - } - - m = microcode_updates; - for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { - if ((m->sig == sig) && (m->pf & pf)) { - unsigned int new_rev; - msr.lo = (unsigned long)(&m->bits) & 0xffffffff; - msr.hi = 0; - wrmsr(0x79, msr); - - /* Read back the new microcode version */ - new_rev = read_microcode_rev(); - break; - } - if (m->total_size) { - c += m->total_size; - } else { - c += 2048; - } - } -} +#include <cpu/intel/microcode/microcode.c> static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index f2f044a..4139c01 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -1 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if !defined(__ROMCC__) void intel_update_microcode(const void *microcode_updates); +#endif

1 0

Patch set updated for coreboot: ac88373 Revamp Intel microcode update code
by Stefan Reinauer 25 Apr '12

25 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/928 -gerrit commit ac883737827dc696ea204c0abe3d0eaa1ffd5af7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 25 22:58:23 2012 +0200 Revamp Intel microcode update code - add GPLv2 + copyright header after talking to Ron - "bits" in struct microcode served no real purpose but getting its address taken. Hence drop it - use asm volatile instead of __asm__ volatile - drop superfluous wrmsr (that seems to be harmless but is still wrong) in read_microcode_rev - use u32 instead of unsigned int where appropriate - make code usable both in bootblock and in ramstage - drop ROMCC style print_debug statements - drop microcode update copy in Sandybridge bootblock Change-Id: Iec4d5c7bfac210194caf577e8d72446e6dfb4b86 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/microcode/microcode.c | 79 ++++++++++++++++++----------- src/cpu/intel/model_206ax/bootblock.c | 89 +-------------------------------- src/include/cpu/intel/microcode.h | 21 ++++++++ 3 files changed, 71 insertions(+), 118 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 9a80077..01a11b2 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -1,6 +1,24 @@ -/* microcode.c: Microcode update for PIII and later CPUS +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* Microcode update for Intel PIII and later CPUs */ + #include <stdint.h> #include <console/console.h> #include <cpu/cpu.h> @@ -9,30 +27,28 @@ struct microcode { u32 hdrver; /* Header Version */ - u32 rev; /* Patch ID */ - u32 date; /* DATE */ - u32 sig; /* CPUID */ + u32 rev; /* Update Revision */ + u32 date; /* Date */ + u32 sig; /* Processor Signature */ - u32 cksum; /* Checksum */ - u32 ldrver; /* Loader Version */ - u32 pf; /* Platform ID */ + u32 cksum; /* Checksum */ + u32 ldrver; /* Loader Revision */ + u32 pf; /* Processor Flags */ - u32 data_size; /* Data size */ - u32 total_size; /* Total size */ + u32 data_size; /* Data Size */ + u32 total_size; /* Total Size */ u32 reserved[3]; - u32 bits[1012]; }; static inline u32 read_microcode_rev(void) { - /* Some Intel Cpus can be very finicky about the + /* Some Intel CPUs can be very finicky about the * CPUID sequence used. So this is implemented in * assembly so that it works reliably. */ msr_t msr; - __asm__ volatile ( - "wrmsr\n\t" + asm volatile ( "xorl %%eax, %%eax\n\t" "xorl %%edx, %%edx\n\t" "movl $0x8b, %%ecx\n\t" @@ -52,14 +68,14 @@ static inline u32 read_microcode_rev(void) void intel_update_microcode(const void *microcode_updates) { - unsigned int eax; - unsigned int pf, rev, sig; + u32 eax; + u32 pf, rev, sig; unsigned int x86_model, x86_family; const struct microcode *m; const char *c; msr_t msr; - /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0; wrmsr(0x8B, msr); @@ -75,35 +91,38 @@ void intel_update_microcode(const void *microcode_updates) msr = rdmsr(0x17); pf = 1 << ((msr.hi >> 18) & 7); } - print_debug("microcode_info: sig = 0x"); - print_debug_hex32(sig); - print_debug(" pf=0x"); - print_debug_hex32(pf); - print_debug(" rev = 0x"); - print_debug_hex32(rev); - print_debug("\n"); +#if !defined(__ROMCC__) + /* If this code is compiled with ROMCC we're probably in + * the bootblock and don't have console output yet. + */ + printk(BIOS_DEBUG, "microcode_info: sig=0x%08x pf=0x%08x rev=0x%08x\n", + sig, pf, rev); +#endif m = microcode_updates; - for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { + for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { if ((m->sig == sig) && (m->pf & pf)) { unsigned int new_rev; - msr.lo = (unsigned long)(&m->bits) & 0xffffffff; + msr.lo = (unsigned long)c + sizeof(struct microcode); msr.hi = 0; wrmsr(0x79, msr); /* Read back the new microcode version */ new_rev = read_microcode_rev(); - print_debug("microcode updated to revision: "); - print_debug_hex32(new_rev); - print_debug(" from revision "); - print_debug_hex32(rev); - print_debug("\n"); +#if !defined(__ROMCC__) + printk(BIOS_DEBUG, "microcode updated to revision: " + "%08x from revision %08x\n", new_rev, rev); +#endif break; } + if (m->total_size) { c += m->total_size; } else { +#if !defined(__ROMCC__) + printk(BIOS_WARN, "Microcode has no valid size field!\n"); +#endif c += 2048; } } diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 7925315..9549d23 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -27,94 +27,7 @@ static const uint32_t microcode_updates[] = { #include "x06_microcode.h" }; -struct microcode { - u32 hdrver; /* Header Version */ - u32 rev; /* Patch ID */ - u32 date; /* DATE */ - u32 sig; /* CPUID */ - - u32 cksum; /* Checksum */ - u32 ldrver; /* Loader Version */ - u32 pf; /* Platform ID */ - - u32 data_size; /* Data size */ - u32 total_size; /* Total size */ - - u32 reserved[3]; - u32 bits[1012]; -}; - -static inline u32 read_microcode_rev(void) -{ - /* Some Intel Cpus can be very finicky about the - * CPUID sequence used. So this is implemented in - * assembly so that it works reliably. - */ - msr_t msr; - __asm__ volatile ( - "wrmsr\n\t" - "xorl %%eax, %%eax\n\t" - "xorl %%edx, %%edx\n\t" - "movl $0x8b, %%ecx\n\t" - "wrmsr\n\t" - "movl $0x01, %%eax\n\t" - "cpuid\n\t" - "movl $0x08b, %%ecx\n\t" - "rdmsr \n\t" - : /* outputs */ - "=a" (msr.lo), "=d" (msr.hi) - : /* inputs */ - : /* trashed */ - "ecx" - ); - return msr.hi; -} - -void intel_update_microcode(const void *microcode_updates) -{ - unsigned int eax; - unsigned int pf, rev, sig; - unsigned int x86_model, x86_family; - const struct microcode *m; - const char *c; - msr_t msr; - - /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ - msr.lo = 0; - msr.hi = 0; - wrmsr(0x8B, msr); - eax = cpuid_eax(1); - msr = rdmsr(0x8B); - rev = msr.hi; - x86_model = (eax >>4) & 0x0f; - x86_family = (eax >>8) & 0x0f; - sig = eax; - - pf = 0; - if ((x86_model >= 5)||(x86_family>6)) { - msr = rdmsr(0x17); - pf = 1 << ((msr.hi >> 18) & 7); - } - - m = microcode_updates; - for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { - if ((m->sig == sig) && (m->pf & pf)) { - unsigned int new_rev; - msr.lo = (unsigned long)(&m->bits) & 0xffffffff; - msr.hi = 0; - wrmsr(0x79, msr); - - /* Read back the new microcode version */ - new_rev = read_microcode_rev(); - break; - } - if (m->total_size) { - c += m->total_size; - } else { - c += 2048; - } - } -} +#include <cpu/intel/microcode/microcode.c> static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index f2f044a..4139c01 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -1 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if !defined(__ROMCC__) void intel_update_microcode(const void *microcode_updates); +#endif

1 0

New patch to review for coreboot: d2fcb38 Revamp Intel microcode update code
by Stefan Reinauer 25 Apr '12

25 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/928 -gerrit commit d2fcb381aa20c03e501abbe30740650f005f8695 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 25 22:58:23 2012 +0200 Revamp Intel microcode update code - add GPLv2 + copyright header after talking to Ron - "bits" in struct microcode served no real purpose but getting its address taken. Hence drop it - use asm volatile instead of __asm__ volatile - drop superfluous wrmsr (that seems to be harmless but is still wrong) in read_microcode_rev - use u32 instead of unsigned int where appropriate - make code usable both in bootblock and in ramstage - drop ROMCC style print_debug statements - drop microcode update copy in Sandybridge bootblock Change-Id: Iec4d5c7bfac210194caf577e8d72446e6dfb4b86 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/microcode/microcode.c | 82 +++++++++++++++++++----------- src/cpu/intel/model_206ax/bootblock.c | 89 +-------------------------------- src/include/cpu/intel/microcode.h | 21 ++++++++ 3 files changed, 73 insertions(+), 119 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 9a80077..f118c5f 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -1,6 +1,24 @@ -/* microcode.c: Microcode update for PIII and later CPUS +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* Microcode update for Intel PIII and later CPUS */ + #include <stdint.h> #include <console/console.h> #include <cpu/cpu.h> @@ -9,30 +27,28 @@ struct microcode { u32 hdrver; /* Header Version */ - u32 rev; /* Patch ID */ - u32 date; /* DATE */ - u32 sig; /* CPUID */ + u32 rev; /* Update Revision */ + u32 date; /* Date */ + u32 sig; /* Processor Signature */ - u32 cksum; /* Checksum */ - u32 ldrver; /* Loader Version */ - u32 pf; /* Platform ID */ + u32 cksum; /* Checksum */ + u32 ldrver; /* Loader Revision */ + u32 pf; /* Processor Flags */ - u32 data_size; /* Data size */ - u32 total_size; /* Total size */ + u32 data_size; /* Data Size */ + u32 total_size; /* Total Size */ u32 reserved[3]; - u32 bits[1012]; }; static inline u32 read_microcode_rev(void) { - /* Some Intel Cpus can be very finicky about the + /* Some Intel CPUs can be very finicky about the * CPUID sequence used. So this is implemented in * assembly so that it works reliably. */ msr_t msr; - __asm__ volatile ( - "wrmsr\n\t" + asm volatile ( "xorl %%eax, %%eax\n\t" "xorl %%edx, %%edx\n\t" "movl $0x8b, %%ecx\n\t" @@ -52,17 +68,18 @@ static inline u32 read_microcode_rev(void) void intel_update_microcode(const void *microcode_updates) { - unsigned int eax; - unsigned int pf, rev, sig; + u32 eax; + u32 pf, rev, sig; unsigned int x86_model, x86_family; const struct microcode *m; const char *c; msr_t msr; - /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0; wrmsr(0x8B, msr); + eax = cpuid_eax(1); msr = rdmsr(0x8B); rev = msr.hi; @@ -75,35 +92,38 @@ void intel_update_microcode(const void *microcode_updates) msr = rdmsr(0x17); pf = 1 << ((msr.hi >> 18) & 7); } - print_debug("microcode_info: sig = 0x"); - print_debug_hex32(sig); - print_debug(" pf=0x"); - print_debug_hex32(pf); - print_debug(" rev = 0x"); - print_debug_hex32(rev); - print_debug("\n"); +#if !defined(__ROMCC__) + /* If this code is compiled with ROMCC we're probably in + * the bootblock and don't have console output yet. + */ + printk(BIOS_DEBUG, "microcode_info: sig=0x%08x pf=0x%08x rev=0x%08x\n", + sig, pf, rev); +#endif m = microcode_updates; - for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { + for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { if ((m->sig == sig) && (m->pf & pf)) { unsigned int new_rev; - msr.lo = (unsigned long)(&m->bits) & 0xffffffff; + msr.lo = (unsigned long)c + sizeof(struct microcode); msr.hi = 0; wrmsr(0x79, msr); /* Read back the new microcode version */ new_rev = read_microcode_rev(); - - print_debug("microcode updated to revision: "); - print_debug_hex32(new_rev); - print_debug(" from revision "); - print_debug_hex32(rev); - print_debug("\n"); + +#if !defined(__ROMCC__) + printk(BIOS_DEBUG, "microcode updated to revision: " + "%08x from revision %08x\n", new_rev, rev); +#endif break; } + if (m->total_size) { c += m->total_size; } else { +#if !defined(__ROMCC__) + printk(BIOS_WARN, "Microcode has no valid size field!\n"); +#endif c += 2048; } } diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 7925315..9549d23 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -27,94 +27,7 @@ static const uint32_t microcode_updates[] = { #include "x06_microcode.h" }; -struct microcode { - u32 hdrver; /* Header Version */ - u32 rev; /* Patch ID */ - u32 date; /* DATE */ - u32 sig; /* CPUID */ - - u32 cksum; /* Checksum */ - u32 ldrver; /* Loader Version */ - u32 pf; /* Platform ID */ - - u32 data_size; /* Data size */ - u32 total_size; /* Total size */ - - u32 reserved[3]; - u32 bits[1012]; -}; - -static inline u32 read_microcode_rev(void) -{ - /* Some Intel Cpus can be very finicky about the - * CPUID sequence used. So this is implemented in - * assembly so that it works reliably. - */ - msr_t msr; - __asm__ volatile ( - "wrmsr\n\t" - "xorl %%eax, %%eax\n\t" - "xorl %%edx, %%edx\n\t" - "movl $0x8b, %%ecx\n\t" - "wrmsr\n\t" - "movl $0x01, %%eax\n\t" - "cpuid\n\t" - "movl $0x08b, %%ecx\n\t" - "rdmsr \n\t" - : /* outputs */ - "=a" (msr.lo), "=d" (msr.hi) - : /* inputs */ - : /* trashed */ - "ecx" - ); - return msr.hi; -} - -void intel_update_microcode(const void *microcode_updates) -{ - unsigned int eax; - unsigned int pf, rev, sig; - unsigned int x86_model, x86_family; - const struct microcode *m; - const char *c; - msr_t msr; - - /* cpuid sets msr 0x8B iff a microcode update has been loaded. */ - msr.lo = 0; - msr.hi = 0; - wrmsr(0x8B, msr); - eax = cpuid_eax(1); - msr = rdmsr(0x8B); - rev = msr.hi; - x86_model = (eax >>4) & 0x0f; - x86_family = (eax >>8) & 0x0f; - sig = eax; - - pf = 0; - if ((x86_model >= 5)||(x86_family>6)) { - msr = rdmsr(0x17); - pf = 1 << ((msr.hi >> 18) & 7); - } - - m = microcode_updates; - for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { - if ((m->sig == sig) && (m->pf & pf)) { - unsigned int new_rev; - msr.lo = (unsigned long)(&m->bits) & 0xffffffff; - msr.hi = 0; - wrmsr(0x79, msr); - - /* Read back the new microcode version */ - new_rev = read_microcode_rev(); - break; - } - if (m->total_size) { - c += m->total_size; - } else { - c += 2048; - } - } -} +#include <cpu/intel/microcode/microcode.c> static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index f2f044a..4139c01 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -1 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if !defined(__ROMCC__) void intel_update_microcode(const void *microcode_updates); +#endif

1 0

Patch merged into coreboot/master: 411f98e Replace cache control magic numbers with symbols
by gerrit＠coreboot.org 25 Apr '12

25 Apr '12

the following patch was just integrated into master: commit 411f98e044309c532df5c514b839d1a91c11ddd1 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 31 12:52:21 2012 +0200 Replace cache control magic numbers with symbols Instead of opaque numbers like (1<<29), use symbols like CR0_NoWriteThrough. Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Wed Apr 25 09:04:34 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Apr 25 16:27:04 2012, giving +2 See http://review.coreboot.org/833 for details. -gerrit

1 0

New patch to review for coreboot: d7b1d94 Potentially speed up ccache builds
by Patrick Georgi 25 Apr '12

25 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/927 -gerrit commit d7b1d9468910f8465bfa5d2cbdb5765e9541e2a5 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Apr 25 12:22:17 2012 +0200 Potentially speed up ccache builds This might speed up ccache builds. While direct mode is faster in evaluating if files changed, the special situation of coreboot prevents ccache from using build results of previously built boards in the same run. This is because Kconfig adds board information to config.h which is part of the hashed data set in direct mode. In preprocessor mode the preprocessor copes with them before ccache decides if the file is the same. Change-Id: Ia4b4fab24de1379a489633593b702630d03df17c Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index 2723efb..7bc5d18 100644 --- a/Makefile +++ b/Makefile @@ -123,7 +123,7 @@ CCACHE:=$(word 1,$(wildcard $(addsuffix /ccache,$(subst :, ,$(PATH))))) ifeq ($(CCACHE),) $(error ccache selected, but not found in PATH) endif -CCACHE:=CCACHE_COMPILERCHECK=content CCACHE_BASEDIR=$(top) $(CCACHE) +CCACHE:=CCACHE_COMPILERCHECK=content CCACHE_NODIRECT=yes CCACHE_BASEDIR=$(top) $(CCACHE) CC := $(CCACHE) $(CC) HOSTCC := $(CCACHE) $(HOSTCC) HOSTCXX := $(CCACHE) $(HOSTCXX)

1 0

Patch merged into coreboot/master: c036828 ASUS M4A785T-M mainboard: fix screen flickering issues
by gerrit＠coreboot.org 25 Apr '12

25 Apr '12

the following patch was just integrated into master: commit c03682861a1d8716900b74ec3f197faa9a68cecd Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat Apr 14 14:30:49 2012 +0200 ASUS M4A785T-M mainboard: fix screen flickering issues Without that fix the screen flickered with resolutions superior to 832x624 because the cpu_ht_freq was 0 (so it ran at 200Mhz). Change-Id: I1056d76b1d77f6177594ed9d03ecc5ae7b3c2c13 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Wed Apr 25 12:07:06 2012, giving +2 See http://review.coreboot.org/900 for details. -gerrit

1 0

New patch to review for coreboot: 422ac12 Split the SCRATCH_SIZE to SRATCH_HEAP_SIZE and SCRATCH_STACK_SIZE
by Zheng Bao 25 Apr '12

25 Apr '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/926 -gerrit commit 422ac12b0e8d2c21e6f3d12ab53ae7ae30b6b634 Author: zbao <fishbaozi(a)gmail.com> Date: Wed Apr 25 18:59:30 2012 +0800 Split the SCRATCH_SIZE to SRATCH_HEAP_SIZE and SCRATCH_STACK_SIZE Please note it is not just changing the hardcode to macro. The orignal SCRATCH_SIZE did not contain the HEAP_SIZE. It was incorrect. Change-Id: I1d9fade0e6da8752a0c86b47c9eabe54daa015cb Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/Kconfig | 6 +++++- src/arch/x86/boot/tables.c | 2 +- src/cpu/amd/agesa/family14/Kconfig | 8 +++++++- src/cpu/amd/agesa/s3_resume.c | 3 +-- src/include/cbmem.h | 2 +- src/mainboard/amd/persimmon/BiosCallOuts.h | 2 +- src/mainboard/amd/persimmon/agesawrapper.c | 2 +- 7 files changed, 17 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index e8a560d..602bcb2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -270,7 +270,11 @@ config HAVE_INIT_TIMER default n if UDELAY_IO default y -config HIGH_SCRATCH_MEMORY_SIZE +config HIGH_SCRATCH_STACK_MEMORY_SIZE + hex + default 0x0 + +config HIGH_SCRATCH_HEAP_MEMORY_SIZE hex default 0x0 diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 70f3117..0f3b347 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -237,7 +237,7 @@ struct lb_memory *write_tables(void) * the result right now. If it fails, ACPI resume will be disabled. */ cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); - cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE); + cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_HEAP_MEMORY_SIZE + CONFIG_HIGH_SCRATCH_STACK_MEMORY_SIZE); #endif #if CONFIG_MULTIBOOT diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 6713660..a8541ce 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -67,8 +67,14 @@ config HAVE_INIT_TIMER default y depends on CPU_AMD_AGESA_FAMILY14 -config HIGH_SCRATCH_MEMORY_SIZE +config HIGH_SCRATCH_STACK_MEMORY_SIZE hex # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) default 0x71000 depends on CPU_AMD_AGESA_FAMILY14 + +config HIGH_SCRATCH_HEAP_MEMORY_SIZE + hex + # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) + default 0x20000 + depends on CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 16c959a..32e75a5 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -137,8 +137,7 @@ void move_stack_high_mem(void) void *high_stack; high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH); - memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, - (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); + memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, CONFIG_HIGH_SCRATCH_HEAP_MEMORY_SIZE); __asm__ volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 33e2de4..c1519ad 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -29,7 +29,7 @@ #if CONFIG_HAVE_ACPI_RESUME #define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) -#define HIGH_MEMORY_SIZE (HIGH_MEMORY_SAVE + CONFIG_HIGH_SCRATCH_MEMORY_SIZE + HIGH_MEMORY_DEF_SIZE) +#define HIGH_MEMORY_SIZE (HIGH_MEMORY_SAVE + CONFIG_HIGH_SCRATCH_STACK_MEMORY_SIZE + CONFIG_HIGH_SCRATCH_HEAP_MEMORY_SIZE + HIGH_MEMORY_DEF_SIZE) /* Delegation of resume backup memory so we don't have to * (slowly) handle backing up OS memory in romstage.c diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index cd23110..0f58f23 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -24,7 +24,7 @@ #include "AGESA.h" #define BIOS_HEAP_START_ADDRESS 0x10000 /* HEAP during cold boot */ -#define BIOS_HEAP_SIZE 0x20000 +#define BIOS_HEAP_SIZE CONFIG_HIGH_SCRATCH_HEAP_MEMORY_SIZE #define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index e60673e..fcd7875 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -255,7 +255,7 @@ UINT32 GetHeapBase( /* Both romstage and ramstage has this S3 detect. */ if (acpi_get_sleep_type() == 3) - heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */ + heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + CONFIG_HIGH_SCRATCH_STACK_MEMORY_SIZE; /* Skip the stack. */ else heap = BIOS_HEAP_START_ADDRESS; /* low mem */

1 0

Re: [coreboot] FILO compilation error on latest svn
by Motiejus Jakštys 25 Apr '12

25 Apr '12

On Wed, Apr 25, 2012 at 10:40, Motiejus Jakštys <desired.mta(a)gmail.com> wrote: > and here is the end result: > http://paste.ubuntu.com/945420/ This directory does not exist: coreboot/payloads/filo/build/i386/ However, this does: coreboot/payloads/filo/build/arch/i386/ As a possible step further, I symlinked: coreboot/payloads/filo/build$ ln -s arch/i386 coreboot/payloads/filo/build$ cd .. coreboot/payloads/filo$ make Found Libpayload /home/motiejus/code/stuff/coreboot/payloads/filo/build/libpayload/lib/libpayload.a. CC build/i386/context.o AS build/i386/switch.S.o CC build/i386/segment.o CC build/i386/timer.o CC build/i386/sys_info.o CC build/i386/linux_load.o /home/motiejus/code/stuff/coreboot/payloads/filo/i386/linux_load.c:752: error: expected identifier or ‘(’ before numeric constant make: *** [/home/motiejus/code/stuff/coreboot/payloads/filo/build/i386/linux_load.o] Error 1 gcc 4:4.4.5-1 Debian Squeeze x86 Thanks -- Motiejus Jakštys

1 0

FILO compilation error on latest svn
by Motiejus Jakštys 25 Apr '12

25 Apr '12

Hi, I was trying to compile FILO. coreboot/payloads$ git svn clone svn://coreboot.org/filo/trunk/filo coreboot/payloads$ cd filo coreboot/payloads/filo$ make menuconfig yadda yadda yadda coreboot/payloads/filo$ make and here is the end result: http://paste.ubuntu.com/945420/ Filo: Last Changed Author: stepan Last Changed Rev: 143 Last Changed Date: 2011-03-31 22:26:40 +0100 (Kt, 31 Kov 2011) Coreboot last commit: commit 02c204706f1f43dd49e8c9cb5136b6a87117dc72 Author: Alec Ari <neotheuser(a)ymail.com> Date: Mon Apr 23 20:24:24 2012 -0500 -- Motiejus Jakštys

1 0

← Newer
1
...
10
11
12
13
14
15
16
...
46
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2012