coreboot April 2012

coreboot@coreboot.org

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459 discussions

New patch to review for coreboot: 33a8fab ChromeOS: add missing string.h in gnvs.c
by Stefan Reinauer 26 Apr '12

26 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/935 -gerrit commit 33a8fabdf07f07531b8ef2e3d88e95836acacaae Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 00:48:58 2012 +0200 ChromeOS: add missing string.h in gnvs.c string.h is required to build with the reference toolchain. Change-Id: I9fd8d2ea8fc676d3502989cbcc7aefe3b2d738b6 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/vendorcode/google/chromeos/gnvs.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 8d0f9bb..6b545f4 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -18,6 +18,7 @@ */ #include <types.h> +#include <string.h> #include <cbfs.h> #include <console/console.h> #include "gnvs.h"

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New patch to review for coreboot: 56ddc41 SMSC MEC1308: Fix ACPI code to work with newer IASL versions
by Stefan Reinauer 26 Apr '12

26 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/934 -gerrit commit 56ddc41d17986ff7be91a5382c08c8beddd90663 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 00:47:21 2012 +0200 SMSC MEC1308: Fix ACPI code to work with newer IASL versions Newer versions of IASL didn't like our IO constructs. Use FixedIO instead, it's also shorter. Change-Id: I9364d993ecb71ffd84c0313ca1e2f870af59eb24 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/superio/smsc/mec1308/acpi/superio.asl | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl index 96f2ef8..2b32e33 100644 --- a/src/superio/smsc/mec1308/acpi/superio.asl +++ b/src/superio/smsc/mec1308/acpi/superio.asl @@ -249,12 +249,12 @@ Device (SIO) { Name (_CRS, ResourceTemplate() { - IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34) + FixedIO (SIO_SMBX_IO0, 0x34) }) Name (_PRS, ResourceTemplate() { - IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34) + FixedIO (SIO_SMBX_IO0, 0x34) }) } #endif

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New patch to review for coreboot: 29e5654 SMM: unify mainboard APM command handlers
by Stefan Reinauer 26 Apr '12

26 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/933 -gerrit commit 29e565474ac898c7b846d45aa5d4e27e2eb6b4db Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 00:44:04 2012 +0200 SMM: unify mainboard APM command handlers rename from mainboard_apm_cnt to mainboard_smi_apmc to match the function naming scheme of the other handlers. Add prototype for mainboard_smi_sleep (mainboard specific S3 sleep handlers in SMM) that is required by Sandybridge. Change-Id: Ib479397e460e33772d90d9d41dba267e4e7e3008 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/cpu/x86/smm.h | 4 +++- src/mainboard/lenovo/t60/mainboard_smi.c | 2 +- src/mainboard/lenovo/x60/mainboard_smi.c | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/i82801gx/smihandler.c | 2 +- 5 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 60959f5..89257e5 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -279,7 +279,9 @@ void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_ void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save); void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); -int __attribute__((weak)) mainboard_apm_cnt(u8 data); +int __attribute__((weak)) mainboard_smi_apmc(u8 data); +void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ); + #if !CONFIG_SMM_TSEG void smi_release_lock(void); #endif diff --git a/src/mainboard/lenovo/t60/mainboard_smi.c b/src/mainboard/lenovo/t60/mainboard_smi.c index eb28256..6ea5037 100644 --- a/src/mainboard/lenovo/t60/mainboard_smi.c +++ b/src/mainboard/lenovo/t60/mainboard_smi.c @@ -159,7 +159,7 @@ void mainboard_smi_gpi(u16 gpi) mainboard_smi_handle_ec_sci(); } -int mainboard_apm_cnt(u8 data) +int mainboard_smi_apmc(u8 data) { u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; u8 tmp; diff --git a/src/mainboard/lenovo/x60/mainboard_smi.c b/src/mainboard/lenovo/x60/mainboard_smi.c index bd1333a..c0d8440 100644 --- a/src/mainboard/lenovo/x60/mainboard_smi.c +++ b/src/mainboard/lenovo/x60/mainboard_smi.c @@ -165,7 +165,7 @@ void mainboard_smi_gpi(u16 gpi) mainboard_smi_handle_ec_sci(); } -int mainboard_apm_cnt(u8 data) +int mainboard_smi_apmc(u8 data) { u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; u8 tmp; diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index e311d95..d7690ba 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -405,7 +405,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state { u32 pmctrl; u8 reg8; - void (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc; + int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc; /* Emulate B2 register as the FADT / Linux expects it */ diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 401c9ad..9d71fa3 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -366,7 +366,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state /* Emulate B2 register as the FADT / Linux expects it */ reg8 = inb(APM_CNT); - if (mainboard_apm_cnt && mainboard_apm_cnt(reg8)) + if (mainboard_smi_apmc && mainboard_smi_apmc(reg8)) return; switch (reg8) {

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New patch to review for coreboot: 93fef85 cpu/cpu.h: add ROMCC guards
by Stefan Reinauer 26 Apr '12

26 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/932 -gerrit commit 93fef85dc9f8e732c1905cf53828ee5782e43df1 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 00:39:17 2012 +0200 cpu/cpu.h: add ROMCC guards In order to use the generic microcode update code in the bootblock, cpu/cpu.h needs ROMCC guards. Also, delete the unused struct device declaration and move the struct bus declaration to where it's used. Change-Id: I0cc731c555593946e931a680ec93994932530599 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/cpu/cpu.h | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index cca2be1..c2113c1 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -1,11 +1,11 @@ #ifndef CPU_CPU_H #define CPU_CPU_H -struct device; -struct bus; #include <arch/cpu.h> +#if !defined(__ROMCC__) void cpu_initialize(void); +struct bus; void initialize_cpus(struct bus *cpu_bus); void secondary_cpu_init(void); @@ -26,5 +26,6 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1); extern struct cpu_driver cpu_drivers[]; /** end of compile time generated pci driver array */ extern struct cpu_driver ecpu_drivers[]; +#endif /* !__ROMCC__ */ #endif /* CPU_CPU_H */

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New patch to review for coreboot: 52c1746 coreboot_table.c: Add missing include files
by Stefan Reinauer 26 Apr '12

26 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/931 -gerrit commit 52c1746e86e7b742b3dede6337114d409dfdb928 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 00:34:54 2012 +0200 coreboot_table.c: Add missing include files If compiling coreboot with ChromeOS support, two more include files are required. Change-Id: I7e042e250e4a89e7dd4bab58443824d503c3f709 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/coreboot_table.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 219de7a..9ceca45 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -34,6 +34,10 @@ #if CONFIG_USE_OPTION_TABLE #include <option_table.h> #endif +#if CONFIG_CHROMEOS +#include <arch/acpi.h> +#include <vendorcode/google/chromeos/gnvs.h> +#endif static struct lb_header *lb_table_init(unsigned long addr) {

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New patch to review for coreboot: e9eb5cf Updates to x86/include/arch/acpi.h for use in fadt.c
by Martin Roth 26 Apr '12

26 Apr '12

Martin Roth (martin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/930 -gerrit commit e9eb5cf237734e291b037b4224449cce336409e0 Author: Martin Roth <martin(a)se-eng.com> Date: Thu Apr 26 15:54:15 2012 -0600 Updates to x86/include/arch/acpi.h for use in fadt.c - Added a union to identify the byte that was reserved in the Generic Address Structure from ACPI 2.0 to ACPI 2.0b as the Access Size byte for ACPI 2.0c to ACPI 5.0 - Added various #defines for use in the FADT - Added a couple of comments for the #endifs Change-Id: I294ddfd89fcb0ad88bb6e52d911f807d84671e82 Signed-off-by: Martin L Roth <martin(a)se-eng.com> --- src/arch/x86/include/arch/acpi.h | 35 +++++++++++++++++++++++++++++------ 1 files changed, 29 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 60e400d..d46cbc2 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -55,7 +55,10 @@ typedef struct acpi_gen_regaddr { u8 space_id; /* Address space ID */ u8 bit_width; /* Register size in bits */ u8 bit_offset; /* Register bit offset */ - u8 resv; /* FIXME: Access size in ACPI 2.0/3.0/4.0 */ + union { + u8 resv; /* Reserved in ACPI 2.0 - 2.0b */ + u8 access_size; /* Access size in ACPI 2.0c/3.0/4.0/5.0 */ + }; u32 addrl; /* Register address, low 32 bits */ u32 addrh; /* Register address, high 32 bits */ } __attribute__ ((packed)) acpi_addr_t; @@ -65,10 +68,18 @@ typedef struct acpi_gen_regaddr { #define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ #define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ #define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ +#define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ #define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ /* 0x80-0xbf: Reserved */ /* 0xc0-0xff: OEM defined */ +/* Access size definitions for Generic address structure */ +#define ACPI_ACCESS_SIZE_UNDEFINED 0 /* Undefined (legacy reasons) */ +#define ACPI_ACCESS_SIZE_BYTE_ACCESS 1 +#define ACPI_ACCESS_SIZE_WORD_ACCESS 2 +#define ACPI_ACCESS_SIZE_DWORD_ACCESS 3 +#define ACPI_ACCESS_SIZE_QWORD_ACCESS 4 + /* Generic ACPI header, provided by (almost) all tables */ typedef struct acpi_table_header { char signature[4]; /* ACPI signature (4 ASCII characters) */ @@ -286,6 +297,13 @@ typedef struct acpi_fadt { struct acpi_gen_regaddr x_gpe1_blk; } __attribute__ ((packed)) acpi_fadt_t; +/* FADT TABLE Revision values */ +#define ACPI_FADT_REV_ACPI_1_0 1 +#define ACPI_FADT_REV_ACPI_2_0 3 +#define ACPI_FADT_REV_ACPI_3_0 4 +#define ACPI_FADT_REV_ACPI_4_0 4 +#define ACPI_FADT_REV_ACPI_5_0 5 + /* FADT Feature Flags */ #define ACPI_FADT_WBINVD (1 << 0) #define ACPI_FADT_WBINVD_FLUSH (1 << 1) @@ -307,7 +325,10 @@ typedef struct acpi_fadt { #define ACPI_FADT_REMOTE_POWER_ON (1 << 17) #define ACPI_FADT_APIC_CLUSTER (1 << 18) #define ACPI_FADT_APIC_PHYSICAL (1 << 19) -/* Bits 20-31: reserved */ +/* Bits 20-31: reserved ACPI 3.0 & 4.0 */ +#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20) +#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21) +/* bits 22-31: reserved ACPI 5.0 */ /* FADT Boot Architecture Flags */ #define ACPI_FADT_LEGACY_DEVICES (1 << 0) @@ -315,6 +336,7 @@ typedef struct acpi_fadt { #define ACPI_FADT_VGA_NOT_PRESENT (1 << 2) #define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3) #define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4) +#define ACPI_FADT_LEGACY_FREE 0; /* No legacy devices (including 8042) */ /* FADT Preferred Power Management Profile */ enum acpi_preferred_pm_profiles { @@ -326,6 +348,7 @@ enum acpi_preferred_pm_profiles { PM_SOHO_SERVER = 5, PM_APPLIANCE_PC = 6, PM_PERFORMANCE_SERVER = 7, + PM_TABLET = 8, /* ACPI 5.0 */ }; /* FACS (Firmware ACPI Control Structure) */ @@ -458,9 +481,9 @@ void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr); int acpi_get_sleep_type(void); -#else +#else /* CONFIG_HAVE_ACPI_RESUME */ #define acpi_slp_type 0 -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ /* northbridge/amd/amdfam10/amdfam10_acpi.c */ unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current); @@ -473,6 +496,6 @@ void generate_cpu_entries(void); #define write_acpi_tables(start) (start) #define acpi_slp_type 0 -#endif +#endif /* CONFIG_GENERATE_ACPI_TABLES */ -#endif +#endif /* __ASM_ACPI_H */

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Patch set updated for coreboot: 6cf94df cbtypes.h: Unify cbtypes.h used in AMD board's code
by Vikram Narayanan 26 Apr '12

26 Apr '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/912 -gerrit commit 6cf94dfec7b4ac5cdb3716ae45726a5fa8ea0235 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sat Apr 21 23:47:56 2012 +0530 cbtypes.h: Unify cbtypes.h used in AMD board's code Remove all the repeated sections of code in cbtypes.h and place it in a common location. Add include dir in vendor code's Makefile. Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/include/cpu/amd/common/cbtypes.h | 66 +++++++++++++++++++++++++ src/mainboard/amd/torpedo/gpio.h | 2 +- src/northbridge/amd/cimx/rd890/NbPlatform.h | 2 +- src/northbridge/amd/cimx/rd890/amd.h | 3 +- src/northbridge/amd/cimx/rd890/cbtypes.h | 71 --------------------------- src/southbridge/amd/cimx/sb700/Platform.h | 2 +- src/southbridge/amd/cimx/sb700/cbtypes.h | 53 -------------------- src/southbridge/amd/cimx/sb800/cbtypes.h | 53 -------------------- src/southbridge/amd/cimx/sb900/cbtypes.h | 59 ---------------------- src/vendorcode/amd/cimx/rd890/Makefile.inc | 1 + src/vendorcode/amd/cimx/sb700/Makefile.inc | 1 + src/vendorcode/amd/cimx/sb800/Makefile.inc | 1 + src/vendorcode/amd/cimx/sb900/Makefile.inc | 1 + 13 files changed, 74 insertions(+), 241 deletions(-) diff --git a/src/include/cpu/amd/common/cbtypes.h b/src/include/cpu/amd/common/cbtypes.h new file mode 100644 index 0000000..dd9e469 --- /dev/null +++ b/src/include/cpu/amd/common/cbtypes.h @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CBTYPES_H_ +#define _CBTYPES_H_ + +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN; +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef signed int INT32; +typedef unsigned long long UINT64; +typedef unsigned char BOOLEAN; + +#define DMSG_SB_TRACE 0x02 +#define TRACE(Arguments) + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef VOLATILE +#define VOLATILE volatile +#endif +#ifndef CONST +#define CONST const +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + + +#ifndef STATIC +#define STATIC static +#endif +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#endif diff --git a/src/mainboard/amd/torpedo/gpio.h b/src/mainboard/amd/torpedo/gpio.h index 45394ef..a33323e 100644 --- a/src/mainboard/amd/torpedo/gpio.h +++ b/src/mainboard/amd/torpedo/gpio.h @@ -27,7 +27,7 @@ #define _GPIO_H_ #include <stdint.h> -#include <cbtypes.h> +#include <cpu/amd/common/cbtypes.h> /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h index 824057a..629e810 100644 --- a/src/northbridge/amd/cimx/rd890/NbPlatform.h +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -94,7 +94,7 @@ #define CIMX_S3_SAVE 1 -#include "cbtypes.h" +#include <cpu/amd/common/cbtypes.h> #include <console/console.h> #include "amd.h" //cimx typedef diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h index d99f90f..3e2e78f 100644 --- a/src/northbridge/amd/cimx/rd890/amd.h +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -20,8 +20,7 @@ #ifndef _AMD_H_ #define _AMD_H_ -#include "cbtypes.h" - +#include <cpu/amd/common/cbtypes.h> #define VOLATILE volatile #define CALLCONV diff --git a/src/northbridge/amd/cimx/rd890/cbtypes.h b/src/northbridge/amd/cimx/rd890/cbtypes.h deleted file mode 100644 index ade55d7..0000000 --- a/src/northbridge/amd/cimx/rd890/cbtypes.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _CBTYPES_H_ -#define _CBTYPES_H_ - -//#include <stdint.h> - -/* -typedef int64_t __int64; -typedef void VOID; -typedef uint32_t UINTN;// -typedef int8_t CHAR8; -typedef uint8_t UINT8; -typedef uint16_t UINT16; -typedef uint32_t UINT32; -typedef uint64_t UINT64; -*/ -typedef signed long long __int64; -typedef void VOID; -typedef unsigned int UINTN;// -typedef signed char CHAR8; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef signed int INT32; -typedef unsigned long long UINT64; - -#define TRUE 1 -#define FALSE 0 -typedef unsigned char BOOLEAN; - -#ifndef VOLATILE -#define VOLATILE volatile -#endif - -#ifndef IN -#define IN -#endif -#ifndef OUT -#define OUT -#endif - -//porting.h -#ifndef CONST -#define CONST const -#endif -#ifndef STATIC -#define STATIC static -#endif -#ifndef VOLATILE -#define VOLATILE volatile -#endif - -#endif diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h index 15e5b07..d70345d 100644 --- a/src/southbridge/amd/cimx/sb700/Platform.h +++ b/src/southbridge/amd/cimx/sb700/Platform.h @@ -22,7 +22,7 @@ #pragma pack(push,1) -#include "cbtypes.h" +#include <cpu/amd/common/cbtypes.h> #include <console/console.h> #include <console/loglevel.h> #ifdef NULL diff --git a/src/southbridge/amd/cimx/sb700/cbtypes.h b/src/southbridge/amd/cimx/sb700/cbtypes.h deleted file mode 100644 index d37e1e3..0000000 --- a/src/southbridge/amd/cimx/sb700/cbtypes.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _CBTYPES_H_ -#define _CBTYPES_H_ - -//#include <stdint.h> - -typedef signed long long __int64; -typedef void VOID; -typedef unsigned int UINTN; -typedef signed char CHAR8; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef unsigned long long UINT64; - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif -typedef unsigned char BOOLEAN; - -#ifndef VOLATILE -#define VOLATILE volatile -#endif - -#ifndef IN -#define IN -#endif -#ifndef OUT -#define OUT -#endif - -#endif diff --git a/src/southbridge/amd/cimx/sb800/cbtypes.h b/src/southbridge/amd/cimx/sb800/cbtypes.h deleted file mode 100644 index 03a0854..0000000 --- a/src/southbridge/amd/cimx/sb800/cbtypes.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _CBTYPES_H_ -#define _CBTYPES_H_ - -//#include <stdint.h> - -typedef signed long long __int64; -typedef void VOID; -typedef unsigned int UINTN; -typedef signed char CHAR8; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef unsigned long long UINT64; - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif -typedef unsigned char BOOLEAN; - -#ifndef VOLATILE -#define VOLATILE volatile -#endif - -#ifndef IN -#define IN -#endif -#ifndef OUT -#define OUT -#endif - -#endif diff --git a/src/southbridge/amd/cimx/sb900/cbtypes.h b/src/southbridge/amd/cimx/sb900/cbtypes.h deleted file mode 100644 index 4c97a33..0000000 --- a/src/southbridge/amd/cimx/sb900/cbtypes.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _CBTYPES_H_ -#define _CBTYPES_H_ - -//#include <stdint.h> - -typedef signed long long __int64; -typedef void VOID; -typedef unsigned int UINTN; -typedef signed char CHAR8; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef unsigned long long UINT64; -typedef unsigned char BOOLEAN; - -#define DMSG_SB_TRACE 0x02 -#define TRACE(Arguments) - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef VOLATILE -#define VOLATILE volatile -#endif -#ifndef CONST -#define CONST const -#endif - -#ifndef IN -#define IN -#endif -#ifndef OUT -#define OUT -#endif - -#endif diff --git a/src/vendorcode/amd/cimx/rd890/Makefile.inc b/src/vendorcode/amd/cimx/rd890/Makefile.inc index 8a05570..feeb2cd 100644 --- a/src/vendorcode/amd/cimx/rd890/Makefile.inc +++ b/src/vendorcode/amd/cimx/rd890/Makefile.inc @@ -32,6 +32,7 @@ CIMX_ROOT = $(src)/vendorcode/amd/cimx NB_CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR) NB_CIMX_INC += -I$(src)/northbridge/amd/cimx/rd890 +NB_CIMX_INC += -I$(src)/include/cpu/amd/common NB_CIMX_INC += -I$(CIMX_ROOT)/rd890 romstage-y += amdAcpiIvrs.c diff --git a/src/vendorcode/amd/cimx/sb700/Makefile.inc b/src/vendorcode/amd/cimx/sb700/Makefile.inc index 8954133..10d03e6 100644 --- a/src/vendorcode/amd/cimx/sb700/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb700/Makefile.inc @@ -32,6 +32,7 @@ CIMX_ROOT = $(src)/vendorcode/amd/cimx SB_CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR) SB_CIMX_INC += -I$(src)/southbridge/amd/cimx/sb700 +SB_CIMX_INC += -I$(src)/include/cpu/amd/common SB_CIMX_INC += -I$(CIMX_ROOT)/sb700 romstage-y += ACPILIB.c diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc index 7badca5..00ba471 100644 --- a/src/vendorcode/amd/cimx/sb800/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb800/Makefile.inc @@ -22,6 +22,7 @@ CIMX_ROOT = $(src)/vendorcode/amd/cimx CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR) CIMX_INC += -I$(src)/southbridge/amd/cimx/sb800 +CIMX_INC += -I$(src)/include/cpu/amd/common CIMX_INC += -I$(CIMX_ROOT)/sb800 romstage-y += ACPILIB.c diff --git a/src/vendorcode/amd/cimx/sb900/Makefile.inc b/src/vendorcode/amd/cimx/sb900/Makefile.inc index 76b610f..e29bdc9 100755 --- a/src/vendorcode/amd/cimx/sb900/Makefile.inc +++ b/src/vendorcode/amd/cimx/sb900/Makefile.inc @@ -22,6 +22,7 @@ CIMX_ROOT = $(src)/vendorcode/amd/cimx CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR) CIMX_INC += -I$(src)/southbridge/amd/cimx/sb900 +CIMX_INC += -I$(src)/include/cpu/amd/common CIMX_INC += -I$(CIMX_ROOT)/sb900 romstage-y += AcpiLib.c

1 0

[RFC] Announcement for Bifferboard port
by Paul Menzel 25 Apr '12

25 Apr '12

Dear coreboot folks, Rudolf did a great job porting coreboot to the Bifferboard. He wants to announce it to their list and sent me his draft asking for help improving the text. I formatted the text using Markdown [1], so you can also create a HTML page running *just one* of the following commands. 1. $ markdown bifferboard-announcement.mdwn 2. $ pandoc -o bifferboard-announcement.html bifferboard-announcement.mdwn Also adding the instructions to the Wiki should be easier now. In my opinion before posting the announcement a Bifferboard page should be created in our Wiki though. Could some of you go over the text and proof read it? Maybe formulate it the way, people get even more excited or interested? ;-) That would be awesome. Thanks, Paul [1] https://en.wikipedia.org/wiki/Markdown

2 2

Patch merged into coreboot/master: a47c78c microcode: print date of microcode and unify output
by gerrit＠coreboot.org 25 Apr '12

25 Apr '12

the following patch was just integrated into master: commit a47c78cd07f694b35de5f82270cae93da7780125 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 26 02:04:53 2012 +0200 microcode: print date of microcode and unify output Most subsystems print their name with a colon, and then the message. Do the same thing for the microcode update code. Also, each microcode update has a date header. Print the date from that header to make it easier to determine whether you're running the latest microcode. Change-Id: Ic22947c4b9f0502d4091d975e1f1ab42f70aa1aa Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu Apr 26 02:23:05 2012, giving +1 See http://review.coreboot.org/929 for details. -gerrit

1 0

New patch to review for coreboot: a47c78c microcode: print date of microcode and unify output
by Stefan Reinauer 25 Apr '12

25 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/929 -gerrit commit a47c78cd07f694b35de5f82270cae93da7780125 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 26 02:04:53 2012 +0200 microcode: print date of microcode and unify output Most subsystems print their name with a colon, and then the message. Do the same thing for the microcode update code. Also, each microcode update has a date header. Print the date from that header to make it easier to determine whether you're running the latest microcode. Change-Id: Ic22947c4b9f0502d4091d975e1f1ab42f70aa1aa Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/microcode/microcode.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 91f7762..1511798 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -95,7 +95,7 @@ void intel_update_microcode(const void *microcode_updates) /* If this code is compiled with ROMCC we're probably in * the bootblock and don't have console output yet. */ - printk(BIOS_DEBUG, "microcode_info: sig=0x%08x pf=0x%08x rev=0x%08x\n", + printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n", sig, pf, rev); #endif @@ -111,8 +111,10 @@ void intel_update_microcode(const void *microcode_updates) new_rev = read_microcode_rev(); #if !defined(__ROMCC__) - printk(BIOS_DEBUG, "microcode updated to revision: " - "%08x from revision %08x\n", new_rev, rev); + printk(BIOS_DEBUG, "microcode: updated to revision " + "0x%x date=%04x-%02x-%02x\n", new_rev, + m->date & 0xffff, (m->date >> 16) & 0xff, + (m->date >> 24) & 0xff); #endif break; }

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coreboot April 2012