coreboot April 2012

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Patch set updated for coreboot: d0aa673 acpigen: make acpigen_write_len_f() non static
by Stefan Reinauer 27 Apr '12

27 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/947 -gerrit commit d0aa673acb3e7e0a4323482a3fec46af32e30a14 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 21:55:05 2012 +0200 acpigen: make acpigen_write_len_f() non static since it is used in CPU specific ACPI generation code Change-Id: I2559658f43c89dc5b4dc8230dea8847d2802990c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/acpigen.c | 2 +- src/arch/x86/include/arch/acpigen.h | 1 + 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index ac1dec2..34067ba 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -35,7 +35,7 @@ static char *gencurrent; char *len_stack[ACPIGEN_LENSTACK_SIZE]; int ltop = 0; -static int acpigen_write_len_f(void) +int acpigen_write_len_f(void) { ASSERT(ltop < (ACPIGEN_LENSTACK_SIZE - 1)) len_stack[ltop++] = gencurrent; diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 335d1bc..ae8aaf7 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -25,6 +25,7 @@ #include <stdint.h> #include <arch/acpi.h> +int acpigen_write_len_f(void); void acpigen_patch_len(int len); void acpigen_set_current(char *curr); char *acpigen_get_current(void);

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Patch set updated for coreboot: f1bb274 ChromeOS: Add missing prototype for acpi_get_vdat_info()
by Stefan Reinauer 27 Apr '12

27 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/946 -gerrit commit f1bb274ab1dd579276755ae1db31ce95bc03a4b4 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 21:53:12 2012 +0200 ChromeOS: Add missing prototype for acpi_get_vdat_info() Change-Id: I4bd9b52cfc24a8ff73be05ee535b9e16c0d9bd79 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/acpi.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 5859d54..be62008 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -519,4 +519,8 @@ void generate_cpu_entries(void); #endif /* CONFIG_GENERATE_ACPI_TABLES */ +#if CONFIG_CHROMEOS +void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size); +#endif /* CONFIG_CHROMEOS */ + #endif /* __ASM_ACPI_H */

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Patch set updated for coreboot: 088c7a4 acpi: Add defines for functional fixed hardware
by Stefan Reinauer 27 Apr '12

27 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/945 -gerrit commit 088c7a404691bbd1c1057fc24ee51ead6532dc48 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 21:51:49 2012 +0200 acpi: Add defines for functional fixed hardware Change-Id: I9c5148eb315e2f478cb753d9918144a19e417379 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/acpi.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 587c484..5859d54 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -70,6 +70,12 @@ typedef struct acpi_gen_regaddr { #define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ #define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ #define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ +#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ +#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ +#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ +#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ +#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ +#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ /* 0x80-0xbf: Reserved */ /* 0xc0-0xff: OEM defined */

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Patch set updated for coreboot: 32eb84d acpigen: Add support for generating T state tables
by Stefan Reinauer 27 Apr '12

27 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/944 -gerrit commit 32eb84d2ff1caca403f0d33ac8f94b432f1287ca Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 21:49:28 2012 +0200 acpigen: Add support for generating T state tables Change-Id: I58050591198bb06de5f0ca58ca3a02f1cfa95069 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/acpigen.c | 125 +++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpi.h | 8 ++ src/arch/x86/include/arch/acpigen.h | 4 + 3 files changed, 137 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index b44f9b9..ac1dec2 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -315,6 +315,59 @@ int acpigen_write_empty_PCT(void) return acpigen_emit_stream(stream, ARRAY_SIZE(stream)); } +int acpigen_write_empty_PTC(void) +{ +/* + Name (_PTC, Package (0x02) + { + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + } + }) +*/ + int len, nlen, rlen; + acpi_addr_t addr = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 0, + .bit_offset = 0, + .resv = 0, + .addrl = 0, + .addrh = 0, + }; + + nlen = acpigen_write_name("_PTC"); + len = acpigen_write_package(2); + + /* ControlRegister */ + rlen = acpigen_write_resourcetemplate_header(); + rlen += acpigen_write_register(&addr); + len += acpigen_write_resourcetemplate_footer(rlen); + len += rlen; + + /* StatusRegister */ + rlen = acpigen_write_resourcetemplate_header(); + rlen += acpigen_write_register(&addr); + len += acpigen_write_resourcetemplate_footer(rlen); + len += rlen; + + acpigen_patch_len(len - 1); + return len + nlen; +} + /* generates a func with max supported P states */ int acpigen_write_PPC(u8 nr) { @@ -341,6 +394,27 @@ int acpigen_write_PPC(u8 nr) return len; } +int acpigen_write_TPC(const char *gnvs_tpc_limit) +{ +/* + // Sample _TPC method + Method (_TPC, 0, NotSerialized) + { + Return (\TLVL) + } + */ + int len; + + len = acpigen_emit_byte(0x14); /* MethodOp */ + len += acpigen_write_len_f(); /* PkgLength */ + len += acpigen_emit_namestring("_TPC"); + len += acpigen_emit_byte(0x00); /* No Arguments */ + len += acpigen_emit_byte(0xa4); /* ReturnOp */ + len += acpigen_emit_namestring(gnvs_tpc_limit); + acpigen_patch_len(len - 1); + return len; +} + int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status) { @@ -409,6 +483,57 @@ int acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) return len + lenh; } +int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) +{ +/* + Sample _TSS package with 100% and 50% duty cycles + Name (_TSS, Package (0x02) + { + Package(){100, 1000, 0, 0x00, 0) + Package(){50, 520, 0, 0x18, 0) + }) + */ + int i, len, plen, nlen; + acpi_tstate_t *tstate = tstate_list; + + nlen = acpigen_write_name("_TSS"); + plen = acpigen_write_package(entries); + + for (i = 0; i < entries; i++) { + len = acpigen_write_package(5); + len += acpigen_write_dword(tstate->percent); + len += acpigen_write_dword(tstate->power); + len += acpigen_write_dword(tstate->latency); + len += acpigen_write_dword(tstate->control); + len += acpigen_write_dword(tstate->status); + acpigen_patch_len(len - 1); + tstate++; + plen += len; + } + + acpigen_patch_len(plen - 1); + return plen + nlen; +} + +int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) +{ + int len, lenh, lenp; + lenh = acpigen_write_name("_TSD"); + lenp = acpigen_write_package(1); + len = acpigen_write_package(5); + len += acpigen_write_byte(5); // 5 values + len += acpigen_write_byte(0); // revision 0 + len += acpigen_write_dword(domain); + len += acpigen_write_dword(coordtype); + len += acpigen_write_dword(numprocs); + acpigen_patch_len(len - 1); + len += lenp; + acpigen_patch_len(len - 1); + return len + lenh; +} + + + int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) { /* diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index ea85d9f..587c484 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -418,6 +418,14 @@ typedef struct acpi_cstate { acpi_addr_t resource; } __attribute__ ((packed)) acpi_cstate_t; +typedef struct acpi_tstate { + u32 percent; + u32 power; + u32 latency; + u32 control; + u32 status; +} __attribute__ ((packed)) acpi_tstate_t; + /* These are implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 4d16040..335d1bc 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -42,12 +42,16 @@ int acpigen_write_name_byte(const char *name, uint8_t val); int acpigen_write_scope(const char *name); int acpigen_write_PPC(u8 nr); int acpigen_write_empty_PCT(void); +int acpigen_write_empty_PTC(void); +int acpigen_write_TPC(const char *gnvs_tpc_limit); int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status); typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); int acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); +int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); +int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); int acpigen_write_register(acpi_addr_t *addr);

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Patch set updated for coreboot: 8dd1dfe Rework ACPI CST table generation
by Stefan Reinauer 27 Apr '12

27 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/943 -gerrit commit 8dd1dfea17870fb58c44e74bbc225a1723b8bc75 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 21:34:16 2012 +0200 Rework ACPI CST table generation ... in order to unify the Sandybridge and Lenovo implementations currently used in the tree. - use acpi_addr_t in acpigen_write_register() - use acpi_cstate_t for cstate tables (and fix up the x60 and t60) - drop cst_entry from acpigen.h Change-Id: Icb87418d44d355f607c4a67300107b40f40b3b3f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/acpigen.c | 50 ++++++++++++++++----------------- src/arch/x86/include/arch/acpi.h | 7 +++++ src/arch/x86/include/arch/acpigen.h | 18 +++--------- src/cpu/amd/model_fxx/Makefile.inc | 2 +- src/cpu/intel/speedstep/acpi.c | 4 +- src/mainboard/lenovo/t60/mainboard.c | 10 +++--- src/mainboard/lenovo/x60/mainboard.c | 10 +++--- 7 files changed, 48 insertions(+), 53 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 7dc7fed..b44f9b9 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -374,7 +374,7 @@ int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) return len + lenh; } -static int acpigen_write_CST_package_entry(struct cst_entry *entry) +static int acpigen_write_CST_package_entry(acpi_cstate_t *cstate) { int len, len0; char *start, *end; @@ -382,19 +382,19 @@ static int acpigen_write_CST_package_entry(struct cst_entry *entry) len0 = acpigen_write_package(4); len = acpigen_write_resourcetemplate_header(); start = acpigen_get_current(); - acpigen_write_register(entry->type, entry->width, entry->offset, entry->addrsize, entry->address); + acpigen_write_register(&cstate->resource); end = acpigen_get_current(); - len += end-start; + len += end - start; len += acpigen_write_resourcetemplate_footer(len); len += len0; - len += acpigen_write_dword(entry->ctype); - len += acpigen_write_dword(entry->latency); - len += acpigen_write_dword(entry->power); + len += acpigen_write_dword(cstate->ctype); + len += acpigen_write_dword(cstate->latency); + len += acpigen_write_dword(cstate->power); acpigen_patch_len(len - 1); return len; } -int acpigen_write_CST_package(struct cst_entry *entry, int nentries) +int acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) { int len, lenh, lenp, i; lenh = acpigen_write_name("_CST"); @@ -402,7 +402,7 @@ int acpigen_write_CST_package(struct cst_entry *entry, int nentries) len = acpigen_write_dword(nentries); for (i = 0; i < nentries; i++) - len += acpigen_write_CST_package_entry(entry + i); + len += acpigen_write_CST_package_entry(cstate + i); len += lenp; acpigen_patch_len(len - 1); @@ -434,25 +434,23 @@ int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) return 12; } -int acpigen_write_register(int type, int width, int offset, int addrsize, u64 address) +int acpigen_write_register(acpi_addr_t *addr) { - acpigen_emit_byte(0x82); - /* Byte 1+2: length (0x000c) */ - acpigen_emit_byte(0x0c); - acpigen_emit_byte(0x00); - /* bit1-7 are ignored */ - acpigen_emit_byte(type); /* FFixedHW */ - acpigen_emit_byte(width); /* register width */ - acpigen_emit_byte(offset); /* register offset */ - acpigen_emit_byte(addrsize); /* register address size */ - acpigen_emit_byte(address & 0xff); /* register address 0-7 */ - acpigen_emit_byte((address >> 8) & 0xff); /* register address 8-15 */ - acpigen_emit_byte((address >> 16) & 0xff); /* register address 16-23 */ - acpigen_emit_byte((address >> 24) & 0xff); /* register address 24-31 */ - acpigen_emit_byte((address >> 32) & 0xff); /* register address 32-39 */ - acpigen_emit_byte((address >> 40) & 0xff); /* register address 40-47 */ - acpigen_emit_byte((address >> 48) & 0xff); /* register address 48-55 */ - acpigen_emit_byte((address >> 56) & 0xff); /* register address 56-63 */ + acpigen_emit_byte(0x82); /* Register Descriptor */ + acpigen_emit_byte(0x0c); /* Register Length 7:0 */ + acpigen_emit_byte(0x00); /* Register Length 15:8 */ + acpigen_emit_byte(addr->space_id); /* Address Space ID */ + acpigen_emit_byte(addr->bit_width); /* Register Bit Width */ + acpigen_emit_byte(addr->bit_offset); /* Register Bit Offset */ + acpigen_emit_byte(addr->resv); /* Register Access Size */ + acpigen_emit_byte(addr->addrl & 0xff); /* Register Address Low */ + acpigen_emit_byte((addr->addrl >> 8) & 0xff); + acpigen_emit_byte((addr->addrl >> 16) & 0xff); + acpigen_emit_byte((addr->addrl >> 24) & 0xff); + acpigen_emit_byte(addr->addrh & 0xff); /* Register Address High */ + acpigen_emit_byte((addr->addrh >> 8) & 0xff); + acpigen_emit_byte((addr->addrh >> 16) & 0xff); + acpigen_emit_byte((addr->addrh >> 24) & 0xff); return 15; } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index d46cbc2..ea85d9f 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -411,6 +411,13 @@ typedef struct acpi_hest_hen { u32 error_threshold_win; } __attribute__ ((packed)) acpi_hest_hen_t; +typedef struct acpi_cstate { + u8 ctype; + u16 latency; + u32 power; + acpi_addr_t resource; +} __attribute__ ((packed)) acpi_cstate_t; + /* These are implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 9dc9675..4d16040 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -23,17 +23,7 @@ #include <assert.h> #include <stdlib.h> #include <stdint.h> - -struct cst_entry { - int type; - int width; - int offset; - int addrsize; - u64 address; - int ctype; - int latency; - int power; -}; +#include <arch/acpi.h> void acpigen_patch_len(int len); void acpigen_set_current(char *curr); @@ -56,16 +46,16 @@ int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat u32 control, u32 status); typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); -int acpigen_write_CST_package(struct cst_entry *entry, int nentries); +int acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); -int acpigen_write_register(int type, int width, int offset, int addrsize, u64 address); +int acpigen_write_register(acpi_addr_t *addr); int acpigen_write_resourcetemplate_header(void); int acpigen_write_resourcetemplate_footer(int len); int acpigen_write_mainboard_resource_template(void); int acpigen_write_mainboard_resources(const char *scope, const char *name); -int get_cst_entries(struct cst_entry **); +int get_cst_entries(acpi_cstate_t **); #endif diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index 948e235..50b6f61 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -3,4 +3,4 @@ driver-y += model_fxx_init.c ramstage-y += apic_timer.c ramstage-y += model_fxx_update_microcode.c ramstage-y += processor_name.c -ramstage-y += powernow_acpi.c +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += powernow_acpi.c diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 00c4ae9..5cc4c1d 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -62,7 +62,7 @@ static int get_fsb(void) return 200; } -int __attribute__((weak)) get_cst_entries(struct cst_entry **entries __attribute__((unused))) +int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries __attribute__((unused))) { return 0; } @@ -76,7 +76,7 @@ void generate_cpu_entries(void) int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout int count; - struct cst_entry *cst_entries; + acpi_cstate_t *cst_entries; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 1817b4b..a9f4117 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -37,13 +37,13 @@ #include <pc80/mc146818rtc.h> #include <arch/x86/include/arch/acpigen.h> -static struct cst_entry cst_entries[] = { - { 0x7f, 1, 2, 0, 1, 1, 1, 1000 }, - { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 }, - { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 }, +static acpi_cstate_t cst_entries[] = { + { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, + { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } }, + { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, }; -int get_cst_entries(struct cst_entry **entries) +int get_cst_entries(acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 89ac489..b45342a 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -38,13 +38,13 @@ #include "dock.h" #include <arch/x86/include/arch/acpigen.h> -static struct cst_entry cst_entries[] = { - { 0x7f, 1, 2, 0, 1, 1, 1, 1000 }, - { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 }, - { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 }, +static acpi_cstate_t cst_entries[] = { + { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, + { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } }, + { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, }; -int get_cst_entries(struct cst_entry **entries) +int get_cst_entries(acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries);

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New patch to review for coreboot: 1d3222e acpigen: make acpigen_write_len_f() non static
by Stefan Reinauer 27 Apr '12

27 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/947 -gerrit commit 1d3222e17f07de0e46d7f866208e9bef48125559 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 21:55:05 2012 +0200 acpigen: make acpigen_write_len_f() non static since it is used in CPU specific ACPI generation code Change-Id: I2559658f43c89dc5b4dc8230dea8847d2802990c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/acpigen.c | 2 +- src/arch/x86/include/arch/acpigen.h | 1 + 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index ac1dec2..34067ba 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -35,7 +35,7 @@ static char *gencurrent; char *len_stack[ACPIGEN_LENSTACK_SIZE]; int ltop = 0; -static int acpigen_write_len_f(void) +int acpigen_write_len_f(void) { ASSERT(ltop < (ACPIGEN_LENSTACK_SIZE - 1)) len_stack[ltop++] = gencurrent; diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 335d1bc..ae8aaf7 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -25,6 +25,7 @@ #include <stdint.h> #include <arch/acpi.h> +int acpigen_write_len_f(void); void acpigen_patch_len(int len); void acpigen_set_current(char *curr); char *acpigen_get_current(void);

1 0

New patch to review for coreboot: 97b0eed ChromeOS: Add missing prototype for acpi_get_vdat_info()
by Stefan Reinauer 27 Apr '12

27 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/946 -gerrit commit 97b0eed6807523bb729454533eb6fee050650193 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 21:53:12 2012 +0200 ChromeOS: Add missing prototype for acpi_get_vdat_info() Change-Id: I4bd9b52cfc24a8ff73be05ee535b9e16c0d9bd79 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/acpi.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 5859d54..be62008 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -519,4 +519,8 @@ void generate_cpu_entries(void); #endif /* CONFIG_GENERATE_ACPI_TABLES */ +#if CONFIG_CHROMEOS +void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size); +#endif /* CONFIG_CHROMEOS */ + #endif /* __ASM_ACPI_H */

1 0

New patch to review for coreboot: afafe47 acpi: Add defines for functional fixed hardware
by Stefan Reinauer 27 Apr '12

27 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/945 -gerrit commit afafe472b035ebc7d5dda713f453cc349906b75f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 21:51:49 2012 +0200 acpi: Add defines for functional fixed hardware Change-Id: I9c5148eb315e2f478cb753d9918144a19e417379 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/acpi.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 587c484..5859d54 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -70,6 +70,12 @@ typedef struct acpi_gen_regaddr { #define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ #define ACPI_ADDRESS_SPACE_PCC 0x0A /* Platform Comm. Channel */ #define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ +#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ +#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ +#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ +#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ +#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ +#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ /* 0x80-0xbf: Reserved */ /* 0xc0-0xff: OEM defined */

1 0

New patch to review for coreboot: e779ab8 acpigen: Add support for generating T state tables
by Stefan Reinauer 27 Apr '12

27 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/944 -gerrit commit e779ab829e221d55f2fffc76280b2d3cd53b7934 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 21:49:28 2012 +0200 acpigen: Add support for generating T state tables Change-Id: I58050591198bb06de5f0ca58ca3a02f1cfa95069 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/acpigen.c | 125 +++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpi.h | 8 ++ src/arch/x86/include/arch/acpigen.h | 4 + 3 files changed, 137 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index b44f9b9..ac1dec2 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -315,6 +315,59 @@ int acpigen_write_empty_PCT(void) return acpigen_emit_stream(stream, ARRAY_SIZE(stream)); } +int acpigen_write_empty_PTC(void) +{ +/* + Name (_PTC, Package (0x02) + { + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (FFixedHW, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + } + }) +*/ + int len, nlen, rlen; + acpi_addr_t addr = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 0, + .bit_offset = 0, + .resv = 0, + .addrl = 0, + .addrh = 0, + }; + + nlen = acpigen_write_name("_PTC"); + len = acpigen_write_package(2); + + /* ControlRegister */ + rlen = acpigen_write_resourcetemplate_header(); + rlen += acpigen_write_register(&addr); + len += acpigen_write_resourcetemplate_footer(rlen); + len += rlen; + + /* StatusRegister */ + rlen = acpigen_write_resourcetemplate_header(); + rlen += acpigen_write_register(&addr); + len += acpigen_write_resourcetemplate_footer(rlen); + len += rlen; + + acpigen_patch_len(len - 1); + return len + nlen; +} + /* generates a func with max supported P states */ int acpigen_write_PPC(u8 nr) { @@ -341,6 +394,27 @@ int acpigen_write_PPC(u8 nr) return len; } +int acpigen_write_TPC(const char *gnvs_tpc_limit) +{ +/* + // Sample _TPC method + Method (_TPC, 0, NotSerialized) + { + Return (\TLVL) + } + */ + int len; + + len = acpigen_emit_byte(0x14); /* MethodOp */ + len += acpigen_write_len_f(); /* PkgLength */ + len += acpigen_emit_namestring("_TPC"); + len += acpigen_emit_byte(0x00); /* No Arguments */ + len += acpigen_emit_byte(0xa4); /* ReturnOp */ + len += acpigen_emit_namestring(gnvs_tpc_limit); + acpigen_patch_len(len - 1); + return len; +} + int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status) { @@ -409,6 +483,57 @@ int acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) return len + lenh; } +int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) +{ +/* + Sample _TSS package with 100% and 50% duty cycles + Name (_TSS, Package (0x02) + { + Package(){100, 1000, 0, 0x00, 0) + Package(){50, 520, 0, 0x18, 0) + }) + */ + int i, len, plen, nlen; + acpi_tstate_t *tstate = tstate_list; + + nlen = acpigen_write_name("_TSS"); + plen = acpigen_write_package(entries); + + for (i = 0; i < entries; i++) { + len = acpigen_write_package(5); + len += acpigen_write_dword(tstate->percent); + len += acpigen_write_dword(tstate->power); + len += acpigen_write_dword(tstate->latency); + len += acpigen_write_dword(tstate->control); + len += acpigen_write_dword(tstate->status); + acpigen_patch_len(len - 1); + tstate++; + plen += len; + } + + acpigen_patch_len(plen - 1); + return plen + nlen; +} + +int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) +{ + int len, lenh, lenp; + lenh = acpigen_write_name("_TSD"); + lenp = acpigen_write_package(1); + len = acpigen_write_package(5); + len += acpigen_write_byte(5); // 5 values + len += acpigen_write_byte(0); // revision 0 + len += acpigen_write_dword(domain); + len += acpigen_write_dword(coordtype); + len += acpigen_write_dword(numprocs); + acpigen_patch_len(len - 1); + len += lenp; + acpigen_patch_len(len - 1); + return len + lenh; +} + + + int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) { /* diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index ea85d9f..587c484 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -418,6 +418,14 @@ typedef struct acpi_cstate { acpi_addr_t resource; } __attribute__ ((packed)) acpi_cstate_t; +typedef struct acpi_tstate { + u32 percent; + u32 power; + u32 latency; + u32 control; + u32 status; +} __attribute__ ((packed)) acpi_tstate_t; + /* These are implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 4d16040..335d1bc 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -42,12 +42,16 @@ int acpigen_write_name_byte(const char *name, uint8_t val); int acpigen_write_scope(const char *name); int acpigen_write_PPC(u8 nr); int acpigen_write_empty_PCT(void); +int acpigen_write_empty_PTC(void); +int acpigen_write_TPC(const char *gnvs_tpc_limit); int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status); typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); int acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); +int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); +int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); int acpigen_write_register(acpi_addr_t *addr);

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New patch to review for coreboot: fd84b0b Rework ACPI CST table generation
by Stefan Reinauer 27 Apr '12

27 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/943 -gerrit commit fd84b0b47bd1322029d311ba2582f893324e8bfe Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 21:34:16 2012 +0200 Rework ACPI CST table generation ... in order to unify the Sandybridge and Lenovo implementations currently used in the tree. - use acpi_addr_t in acpigen_write_register() - use acpi_cstate_t for cstate tables (and fix up the x60 and t60) - drop cst_entry from acpigen.h Change-Id: Icb87418d44d355f607c4a67300107b40f40b3b3f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/acpigen.c | 50 ++++++++++++++++----------------- src/arch/x86/include/arch/acpi.h | 7 +++++ src/arch/x86/include/arch/acpigen.h | 18 +++--------- src/cpu/intel/speedstep/acpi.c | 4 +- src/mainboard/lenovo/t60/mainboard.c | 10 +++--- src/mainboard/lenovo/x60/mainboard.c | 10 +++--- 6 files changed, 47 insertions(+), 52 deletions(-) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 7dc7fed..b44f9b9 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -374,7 +374,7 @@ int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) return len + lenh; } -static int acpigen_write_CST_package_entry(struct cst_entry *entry) +static int acpigen_write_CST_package_entry(acpi_cstate_t *cstate) { int len, len0; char *start, *end; @@ -382,19 +382,19 @@ static int acpigen_write_CST_package_entry(struct cst_entry *entry) len0 = acpigen_write_package(4); len = acpigen_write_resourcetemplate_header(); start = acpigen_get_current(); - acpigen_write_register(entry->type, entry->width, entry->offset, entry->addrsize, entry->address); + acpigen_write_register(&cstate->resource); end = acpigen_get_current(); - len += end-start; + len += end - start; len += acpigen_write_resourcetemplate_footer(len); len += len0; - len += acpigen_write_dword(entry->ctype); - len += acpigen_write_dword(entry->latency); - len += acpigen_write_dword(entry->power); + len += acpigen_write_dword(cstate->ctype); + len += acpigen_write_dword(cstate->latency); + len += acpigen_write_dword(cstate->power); acpigen_patch_len(len - 1); return len; } -int acpigen_write_CST_package(struct cst_entry *entry, int nentries) +int acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries) { int len, lenh, lenp, i; lenh = acpigen_write_name("_CST"); @@ -402,7 +402,7 @@ int acpigen_write_CST_package(struct cst_entry *entry, int nentries) len = acpigen_write_dword(nentries); for (i = 0; i < nentries; i++) - len += acpigen_write_CST_package_entry(entry + i); + len += acpigen_write_CST_package_entry(cstate + i); len += lenp; acpigen_patch_len(len - 1); @@ -434,25 +434,23 @@ int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) return 12; } -int acpigen_write_register(int type, int width, int offset, int addrsize, u64 address) +int acpigen_write_register(acpi_addr_t *addr) { - acpigen_emit_byte(0x82); - /* Byte 1+2: length (0x000c) */ - acpigen_emit_byte(0x0c); - acpigen_emit_byte(0x00); - /* bit1-7 are ignored */ - acpigen_emit_byte(type); /* FFixedHW */ - acpigen_emit_byte(width); /* register width */ - acpigen_emit_byte(offset); /* register offset */ - acpigen_emit_byte(addrsize); /* register address size */ - acpigen_emit_byte(address & 0xff); /* register address 0-7 */ - acpigen_emit_byte((address >> 8) & 0xff); /* register address 8-15 */ - acpigen_emit_byte((address >> 16) & 0xff); /* register address 16-23 */ - acpigen_emit_byte((address >> 24) & 0xff); /* register address 24-31 */ - acpigen_emit_byte((address >> 32) & 0xff); /* register address 32-39 */ - acpigen_emit_byte((address >> 40) & 0xff); /* register address 40-47 */ - acpigen_emit_byte((address >> 48) & 0xff); /* register address 48-55 */ - acpigen_emit_byte((address >> 56) & 0xff); /* register address 56-63 */ + acpigen_emit_byte(0x82); /* Register Descriptor */ + acpigen_emit_byte(0x0c); /* Register Length 7:0 */ + acpigen_emit_byte(0x00); /* Register Length 15:8 */ + acpigen_emit_byte(addr->space_id); /* Address Space ID */ + acpigen_emit_byte(addr->bit_width); /* Register Bit Width */ + acpigen_emit_byte(addr->bit_offset); /* Register Bit Offset */ + acpigen_emit_byte(addr->resv); /* Register Access Size */ + acpigen_emit_byte(addr->addrl & 0xff); /* Register Address Low */ + acpigen_emit_byte((addr->addrl >> 8) & 0xff); + acpigen_emit_byte((addr->addrl >> 16) & 0xff); + acpigen_emit_byte((addr->addrl >> 24) & 0xff); + acpigen_emit_byte(addr->addrh & 0xff); /* Register Address High */ + acpigen_emit_byte((addr->addrh >> 8) & 0xff); + acpigen_emit_byte((addr->addrh >> 16) & 0xff); + acpigen_emit_byte((addr->addrh >> 24) & 0xff); return 15; } diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index d46cbc2..ea85d9f 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -411,6 +411,13 @@ typedef struct acpi_hest_hen { u32 error_threshold_win; } __attribute__ ((packed)) acpi_hest_hen_t; +typedef struct acpi_cstate { + u8 ctype; + u16 latency; + u32 power; + acpi_addr_t resource; +} __attribute__ ((packed)) acpi_cstate_t; + /* These are implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 9dc9675..4d16040 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -23,17 +23,7 @@ #include <assert.h> #include <stdlib.h> #include <stdint.h> - -struct cst_entry { - int type; - int width; - int offset; - int addrsize; - u64 address; - int ctype; - int latency; - int power; -}; +#include <arch/acpi.h> void acpigen_patch_len(int len); void acpigen_set_current(char *curr); @@ -56,16 +46,16 @@ int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat u32 control, u32 status); typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); -int acpigen_write_CST_package(struct cst_entry *entry, int nentries); +int acpigen_write_CST_package(acpi_cstate_t *entry, int nentries); int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); -int acpigen_write_register(int type, int width, int offset, int addrsize, u64 address); +int acpigen_write_register(acpi_addr_t *addr); int acpigen_write_resourcetemplate_header(void); int acpigen_write_resourcetemplate_footer(int len); int acpigen_write_mainboard_resource_template(void); int acpigen_write_mainboard_resources(const char *scope, const char *name); -int get_cst_entries(struct cst_entry **); +int get_cst_entries(acpi_cstate_t **); #endif diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 00c4ae9..5cc4c1d 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -62,7 +62,7 @@ static int get_fsb(void) return 200; } -int __attribute__((weak)) get_cst_entries(struct cst_entry **entries __attribute__((unused))) +int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries __attribute__((unused))) { return 0; } @@ -76,7 +76,7 @@ void generate_cpu_entries(void) int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout int count; - struct cst_entry *cst_entries; + acpi_cstate_t *cst_entries; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 1817b4b..a9f4117 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -37,13 +37,13 @@ #include <pc80/mc146818rtc.h> #include <arch/x86/include/arch/acpigen.h> -static struct cst_entry cst_entries[] = { - { 0x7f, 1, 2, 0, 1, 1, 1, 1000 }, - { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 }, - { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 }, +static acpi_cstate_t cst_entries[] = { + { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, + { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } }, + { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, }; -int get_cst_entries(struct cst_entry **entries) +int get_cst_entries(acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 89ac489..b45342a 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -38,13 +38,13 @@ #include "dock.h" #include <arch/x86/include/arch/acpigen.h> -static struct cst_entry cst_entries[] = { - { 0x7f, 1, 2, 0, 1, 1, 1, 1000 }, - { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 }, - { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 }, +static acpi_cstate_t cst_entries[] = { + { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, + { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } }, + { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, }; -int get_cst_entries(struct cst_entry **entries) +int get_cst_entries(acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries);

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coreboot April 2012