Raymond Danks (ray.danks(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/941
-gerrit
commit 652dcc6f7dcf8ca32dd1d8cd50e3845c1cf09fa3
Author: Raymond Danks <ray.danks(a)se-eng.com>
Date: Fri Apr 27 08:51:02 2012 -0600
ectool: Allow build under Cygwin
To build under Cygwin, ectool depends upon the package ioperm:
http://openwince.sourceforge.net/ioperm/
for sys/io.h and sys/perm.h. This change causes the ectool make to correctly include and link against these headers and libraries.
Change-Id: I7d54ab5110c2bb1fd21dfa48d56031f3f29cd54e
Signed-off-by: Raymond Danks <ray.danks(a)se-eng.com>
---
util/ectool/Makefile | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/util/ectool/Makefile b/util/ectool/Makefile
index c817395..16a1ce9 100644
--- a/util/ectool/Makefile
+++ b/util/ectool/Makefile
@@ -24,10 +24,15 @@ PROGRAM = ectool
INSTALL = /usr/bin/install
PREFIX = /usr/local
+OS_ARCH = $(shell uname -o)
+ifeq ($(OS_ARCH), Cygwin)
+LDFLAGS = -lioperm
+endif
+
all: $(PROGRAM)
$(PROGRAM): ec.o ectool.o
- $(CC) $(CFLAGS) -o $@ $^
+ $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS)
install: $(PROGRAM)
$(INSTALL) $(PROGRAM) $(PREFIX)/sbin
the following patch was just integrated into master:
commit e9eb5cf237734e291b037b4224449cce336409e0
Author: Martin Roth <martin(a)se-eng.com>
Date: Thu Apr 26 15:54:15 2012 -0600
Updates to x86/include/arch/acpi.h for use in fadt.c
- Added a union to identify the byte that was reserved in the
Generic Address Structure from ACPI 2.0 to ACPI 2.0b as the
Access Size byte for ACPI 2.0c to ACPI 5.0
- Added various #defines for use in the FADT
- Added a couple of comments for the #endifs
Change-Id: I294ddfd89fcb0ad88bb6e52d911f807d84671e82
Signed-off-by: Martin L Roth <martin(a)se-eng.com>
Build-Tested: build bot (Jenkins) at Fri Apr 27 01:34:24 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Apr 27 01:16:35 2012, giving +2
See http://review.coreboot.org/930 for details.
-gerrit
Martin Roth (martin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/938
-gerrit
commit ba41dbb09f89e022168c8c497b57528a99072349
Author: Martin Roth <martin(a)se-eng.com>
Date: Thu Apr 26 16:04:18 2012 -0600
Reverse Vendor ID & Device ID for map_oprom_vendev()
- When calling map_oprom_vendev() the vendor ID and device ID
are joined into a 32 bit value. They were reversed from the
order that I would have expected - Device ID as the high 16 bits
and the Vendor ID as the low 16. This patch reverses them so
so that the the dword comparison in map_oprom_vendev() matches
what's entered into Kconfig for vendor,device.
Change-Id: I5b84db3cb1a359a7533409fde7d05fbc6ba3fcc4
Signed-off-by: Martin L Roth <martin(a)se-eng.com>
---
src/devices/pci_rom.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c
index 800776e..e7933eb 100644
--- a/src/devices/pci_rom.c
+++ b/src/devices/pci_rom.c
@@ -37,7 +37,7 @@ struct rom_header *pci_rom_probe(struct device *dev)
/* If it's in FLASH, then don't check device for ROM. */
rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
- u32 vendev = dev->vendor | (dev->device << 16);
+ u32 vendev = (dev->vendor << 16) | dev->device;
u32 mapped_vendev = vendev;
if (map_oprom_vendev)
@@ -45,8 +45,8 @@ struct rom_header *pci_rom_probe(struct device *dev)
if (!rom_header) {
if (vendev != mapped_vendev) {
- rom_header = cbfs_load_optionrom(mapped_vendev &
- 0xffff, mapped_vendev >> 16, NULL);
+ rom_header = cbfs_load_optionrom(mapped_vendev >> 16,
+ mapped_vendev & 0xffff , NULL);
}
}
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/937
-gerrit
commit 7f88aa1f2b39f0486f6cbee69df2cff0def4fee9
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Fri Apr 27 01:05:11 2012 +0200
SMM: Add udelay on Sandybridge systems
Cougar Point southbridge does udelay in SMM, hence add it on Sandybridge
systems.
Change-Id: I6e5520ca27e7c6eaae632992fb68612067bc1e30
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
---
src/northbridge/intel/sandybridge/Makefile.inc | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 9e7568c..b72e9fa 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -27,6 +27,7 @@ romstage-y += raminit.c
romstage-y += early_init.c
romstage-y += ../../../arch/x86/lib/walkcbfs.S
+smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
# We don't ship that, but booting without it is bound to fail
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/936
-gerrit
commit f98635bb077d263d279216f107fd130201c1ccd1
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Fri Apr 27 01:02:26 2012 +0200
Cougar Point southbridge: Add includes and drop post_code()
post_code() was added in our internal tree by duplicating code. It's not of
much use at this point, since the code is quite well tested, so avoid bloating
the bootblock (since compiled with ROMCC).
Also add some missing include files that didn't seem to be needed with an
older version of coreboot.
Change-Id: Id62b838728a247e8bcadb4f1db17269be0d4f3f4
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
---
src/southbridge/intel/bd82x6x/bootblock.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 686e820..d6cba5f 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/tsc.h>
#include "pch.h"
static void store_initial_timestamp(void)
@@ -59,7 +62,6 @@ static void enable_port80_on_lpc(void)
u32 reg32 = *gcs;
reg32 = reg32 & ~0x04;
*gcs = reg32;
- post_code(0x01);
#endif
}