coreboot April 2012

coreboot@coreboot.org

39 participants
459 discussions

Patch set updated for coreboot: 411f98e Replace cache control magic numbers with symbols
by Patrick Georgi 25 Apr '12

25 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/833 -gerrit commit 411f98e044309c532df5c514b839d1a91c11ddd1 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 31 12:52:21 2012 +0200 Replace cache control magic numbers with symbols Instead of opaque numbers like (1<<29), use symbols like CR0_NoWriteThrough. Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/amd/agesa/cache_as_ram.inc | 3 ++- src/cpu/amd/car/cache_as_ram.inc | 3 ++- src/cpu/amd/car/disable_cache_as_ram.c | 4 +++- src/cpu/intel/car/cache_as_ram.inc | 7 ++++--- src/cpu/intel/car/cache_as_ram_ht.inc | 17 +++++++++-------- src/cpu/intel/model_106cx/cache_as_ram.inc | 15 ++++++++------- src/cpu/intel/model_206ax/cache_as_ram.inc | 15 ++++++++------- src/cpu/intel/model_6ex/cache_as_ram.inc | 15 ++++++++------- src/cpu/intel/model_6fx/cache_as_ram.inc | 15 ++++++++------- src/cpu/via/car/cache_as_ram.inc | 9 +++++---- src/include/cpu/x86/cache.h | 6 ++++++ 11 files changed, 63 insertions(+), 46 deletions(-) diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index 2124bf3..389f7ec 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -28,6 +28,7 @@ */ #include "gcccar.inc" +#include <cpu/x86/cache.h> /* * XMM map: @@ -88,7 +89,7 @@ disable_cache_as_ram: /* Disable cache */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 invd diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 4625da1..18a19fc 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -19,6 +19,7 @@ */ #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/amd/mtrr.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE @@ -320,7 +321,7 @@ wbcache_post_fam10_setup: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 jmp_if_k8(fam10_end_part1) diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 0f91154..a48a39c 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -21,12 +21,14 @@ * be warned, this file will be used other cores and core 0 / node 0 */ +#include <cpu/x86/cache.h> + static inline __attribute__((always_inline)) void disable_cache_as_ram(void) { msr_t msr; /* disable cache */ - write_cr0(read_cr0() | (1 << 30)); + write_cr0(read_cr0() | CR0_CacheDisable); msr.lo = 0; msr.hi = 0; diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 7742a68..6e642f6 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -23,6 +23,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h> @@ -254,7 +255,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -328,7 +329,7 @@ lout: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Clear sth. */ @@ -353,7 +354,7 @@ lout: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Clear boot_complete flag. */ diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index ca107c4..4e0f391 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -22,6 +22,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #include <cpu/x86/lapic_def.h> @@ -188,7 +189,7 @@ ap_init: /* Do not disable cache (so BSP can enable it). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 post_code(0x28) @@ -271,7 +272,7 @@ no_msr_11e: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -284,7 +285,7 @@ no_msr_11e: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x2d) @@ -310,7 +311,7 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 post_code(0x2e) @@ -338,7 +339,7 @@ no_msr_11e: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x34) @@ -357,14 +358,14 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x37) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -393,7 +394,7 @@ no_msr_11e: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index caf5d03..e74e24c 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #define CPU_MAXPHYADDR 32 @@ -84,7 +85,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +123,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +151,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +182,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -207,7 +208,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index c4d3701..7d402e4 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #include <cbmem.h> @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -126,7 +127,7 @@ clear_mtrrs: post_code(0x26) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Enable cache for our code in Flash because we do XIP here */ @@ -162,7 +163,7 @@ clear_mtrrs: post_code(0x28) /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer below MRC variable space. */ @@ -195,7 +196,7 @@ before_romstage: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -235,14 +236,14 @@ before_romstage: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -275,7 +276,7 @@ before_romstage: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 08f5b11..92337c8 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #define CPU_MAXPHYADDR 36 @@ -84,7 +85,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +123,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +151,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +182,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -217,7 +218,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 25d8de2..61feb1d 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #define CPU_MAXPHYADDR 36 @@ -91,7 +92,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -105,7 +106,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -129,7 +130,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -157,7 +158,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -188,14 +189,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -214,7 +215,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 90e6d2b..bfad528 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -27,6 +27,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <console/post_codes.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE @@ -39,7 +40,7 @@ CacheAsRam: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 invd @@ -139,7 +140,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -219,7 +220,7 @@ testok: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Set the default memory type and enable variable MTRRs. */ @@ -259,7 +260,7 @@ testok: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 invd diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index c2de073..a448228 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -20,6 +20,11 @@ #ifndef CPU_X86_CACHE #define CPU_X86_CACHE +#define CR0_CacheDisable (1 << 30) +#define CR0_NoWriteThrough (1 << 29) + +#if !defined(__ASSEMBLER__) + /* * Need two versions because ROMCC chokes on certain clobbers: * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: @@ -107,4 +112,5 @@ static inline __attribute__((always_inline)) void disable_cache(void) void x86_enable_cache(void); #endif +#endif /* !__ASSEMBLER__ */ #endif /* CPU_X86_CACHE */

1 0

Patch set updated for coreboot: 251a0f4 Replace cache control magic numbers with symbols
by Patrick Georgi 24 Apr '12

24 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/833 -gerrit commit 251a0f4fa40c23a286bbb08a7a2cd68c709205ed Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 31 12:52:21 2012 +0200 Replace cache control magic numbers with symbols Instead of opaque numbers like (1<<29), use symbols like CR0_NoWriteThrough. Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/amd/car/cache_as_ram.inc | 3 ++- src/cpu/amd/car/disable_cache_as_ram.c | 4 +++- src/cpu/intel/car/cache_as_ram.inc | 7 ++++--- src/cpu/intel/car/cache_as_ram_ht.inc | 17 +++++++++-------- src/cpu/intel/model_106cx/cache_as_ram.inc | 15 ++++++++------- src/cpu/intel/model_6ex/cache_as_ram.inc | 15 ++++++++------- src/cpu/intel/model_6fx/cache_as_ram.inc | 15 ++++++++------- src/cpu/via/car/cache_as_ram.inc | 9 +++++---- src/include/cpu/x86/cache.h | 6 ++++++ 9 files changed, 53 insertions(+), 38 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 4625da1..18a19fc 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -19,6 +19,7 @@ */ #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/amd/mtrr.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE @@ -320,7 +321,7 @@ wbcache_post_fam10_setup: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 jmp_if_k8(fam10_end_part1) diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 0f91154..a48a39c 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -21,12 +21,14 @@ * be warned, this file will be used other cores and core 0 / node 0 */ +#include <cpu/x86/cache.h> + static inline __attribute__((always_inline)) void disable_cache_as_ram(void) { msr_t msr; /* disable cache */ - write_cr0(read_cr0() | (1 << 30)); + write_cr0(read_cr0() | CR0_CacheDisable); msr.lo = 0; msr.hi = 0; diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 7742a68..6e642f6 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -23,6 +23,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h> @@ -254,7 +255,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -328,7 +329,7 @@ lout: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Clear sth. */ @@ -353,7 +354,7 @@ lout: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Clear boot_complete flag. */ diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index ca107c4..4e0f391 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -22,6 +22,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #include <cpu/x86/lapic_def.h> @@ -188,7 +189,7 @@ ap_init: /* Do not disable cache (so BSP can enable it). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 post_code(0x28) @@ -271,7 +272,7 @@ no_msr_11e: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -284,7 +285,7 @@ no_msr_11e: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x2d) @@ -310,7 +311,7 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 post_code(0x2e) @@ -338,7 +339,7 @@ no_msr_11e: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x34) @@ -357,14 +358,14 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x37) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -393,7 +394,7 @@ no_msr_11e: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index caf5d03..e74e24c 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #define CPU_MAXPHYADDR 32 @@ -84,7 +85,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +123,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +151,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +182,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -207,7 +208,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 08f5b11..92337c8 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #define CPU_MAXPHYADDR 36 @@ -84,7 +85,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +99,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +123,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +151,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +182,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -217,7 +218,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 25d8de2..61feb1d 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> #define CPU_MAXPHYADDR 36 @@ -91,7 +92,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax invd movl %eax, %cr0 @@ -105,7 +106,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -129,7 +130,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -157,7 +158,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -188,14 +189,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -214,7 +215,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 90e6d2b..bfad528 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -27,6 +27,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> #include <console/post_codes.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE @@ -39,7 +40,7 @@ CacheAsRam: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 invd @@ -139,7 +140,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -219,7 +220,7 @@ testok: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $CR0_CacheDisable, %eax movl %eax, %cr0 /* Set the default memory type and enable variable MTRRs. */ @@ -259,7 +260,7 @@ testok: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 invd diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index c2de073..a448228 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -20,6 +20,11 @@ #ifndef CPU_X86_CACHE #define CPU_X86_CACHE +#define CR0_CacheDisable (1 << 30) +#define CR0_NoWriteThrough (1 << 29) + +#if !defined(__ASSEMBLER__) + /* * Need two versions because ROMCC chokes on certain clobbers: * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: @@ -107,4 +112,5 @@ static inline __attribute__((always_inline)) void disable_cache(void) void x86_enable_cache(void); #endif +#endif /* !__ASSEMBLER__ */ #endif /* CPU_X86_CACHE */

1 0

Re: [coreboot] SUCCESS: MX25L1605 on Thinkpad X60s [was: FAILED]
by Peter Stuge 24 Apr '12

24 Apr '12

Moving over to the coreboot mailing list. Motiejus Jakštys wrote: > Yes, it flashed fine. There is still a minor disturbance, though: > tp_smapi does not recognize my TP. But whatever, I can live with that. Could you send some logs showing this failure? I don't recall seeing it, but I also haven't actively tried to use tp_smapi on my machine. > > idle=halt. > > Slightly off-topic, but please forgive us. This worked for me: > processor.max_cstate=2 in kernel boot line (Squeeze). From [1]. Yes, that also works, but I found that I could still hear noise with that setting, so I went with idle=halt. > > Now, there is also a possibility that coreboot can do something to > > work around this situation, similarly to what the factory BIOS > > obviously does, since the noise is not present there, but this has > > not been researched. > > Probably power saving was disabled in original BIOS. I got this computer > used and somehow didn't check it, was too hurry to flash to coreboot. I somehow think the power saving has too big impact on battery life to have been disabled, but oh well. > > I'm glad to hear that it works for you! > > Thanks a lot for your help. :) You're welcome, but thank Sven instead, he did the port and pointed out the flashrom trick! :) //Peter

2 1

Patch merged into coreboot/master: 390ae3f Makefile: rename romstage linking filenames
by gerrit＠coreboot.org 24 Apr '12

24 Apr '12

the following patch was just integrated into master: commit 390ae3fd5a950a8126dd961a7808a328c10638fd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Apr 19 14:43:47 2012 +0300 Makefile: rename romstage linking filenames Move final build results under $(objcbfs). Move intermediate files under $(objgenerated). Remove use of sed -i. Change-Id: Ie035a1544848b26514a197c340f470201065b8d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Apr 19 15:47:02 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Apr 24 23:25:21 2012, giving +2 See http://review.coreboot.org/859 for details. -gerrit

1 0

Patch merged into coreboot/master: 6c1129d Makefile: rename coreboot_ap linking filenames
by gerrit＠coreboot.org 24 Apr '12

24 Apr '12

the following patch was just integrated into master: commit 6c1129df5afbf578a4173fac9bea3c2f6ed83ac8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Apr 19 14:22:43 2012 +0300 Makefile: rename coreboot_ap linking filenames $(obj)/coreboot_ap -> $(objcbfs)/coreboot_ap.elf It is really a ramstage for AP CPU and not a romstage, it is not enabled for any mainboard by default, and it doesn't compile even if enabled. Change-Id: Ifb9c5cb6df65309660b000876cf6a9a3da9b6839 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Apr 19 16:11:35 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Apr 24 23:16:26 2012, giving +2 See http://review.coreboot.org/840 for details. -gerrit

1 0

Patch merged into coreboot/master: 755e2c0 Makefile: rename ramstage linking filenames
by gerrit＠coreboot.org 24 Apr '12

24 Apr '12

the following patch was just integrated into master: commit 755e2c0f394f31648db35fd42f60e2174e1cf6a0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Apr 19 12:21:36 2012 +0300 Makefile: rename ramstage linking filenames Move final build results under $(objcbfs). Move intermediate files under $(objgenerated). Change-Id: I0046f68938be81b8efa525aa50b39328ca02ecb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Apr 19 15:33:41 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Apr 24 23:13:00 2012, giving +2 See http://review.coreboot.org/839 for details. -gerrit

1 0

Patch merged into coreboot/master: cecd82c Makefile: rename bootblock linking filenames
by gerrit＠coreboot.org 24 Apr '12

24 Apr '12

the following patch was just integrated into master: commit cecd82c55af49bb8e7f1838258c6b389fb787d3d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Apr 19 12:14:53 2012 +0300 Makefile: rename bootblock linking filenames Move final build results under $(objcbfs). Move intermediate files under $(objgenerated). Change-Id: I0365304e1b0ed02a5a3ec720b0cf3e303eaefa7c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Apr 19 15:20:03 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Apr 24 23:12:18 2012, giving +2 See http://review.coreboot.org/838 for details. -gerrit

1 0

Patch merged into coreboot/master: 32b3e00 rk886: Add ACPI support for LID switch
by gerrit＠coreboot.org 24 Apr '12

24 Apr '12

the following patch was just integrated into master: commit 32b3e0095d7ff432732ddb08e24390454f41e7e3 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Apr 20 15:31:16 2012 +0200 rk886: Add ACPI support for LID switch Change-Id: Ib5a34491531228db9a9232322bd573fded27ee67 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Apr 24 11:47:30 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Apr 24 23:09:24 2012, giving +2 See http://review.coreboot.org/924 for details. -gerrit

1 0

Re: [coreboot] timestamping broke 486 board
by Peter Stuge 24 Apr '12

24 Apr '12

ron minnich wrote: > Any chance we can make a config variable called CONFIG_TSC and then > #error if somebody tries to use a machine that doesn't have it? There was already a CONFIG_ option for this feature but the code performing timestamping simply ignored that. The committed fix solves the problem well. I think your idea is great in order to protect against similar problems in the future, if TSC are expected to be used more and more. All boards except bifferos/bifferboard and emulation/qemu-x86 have select CPU_ in their Kconfig, so select TSC could be done in the CPU Kconfig files. //Peter

2 1

Patch merged into coreboot/master: 1896e2a Make timestamp collection conditional in hardwaremain.c
by gerrit＠coreboot.org 24 Apr '12

24 Apr '12

the following patch was just integrated into master: commit 1896e2a19c848725a30833eabe0f12b10a714527 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue Apr 24 16:01:24 2012 +0200 Make timestamp collection conditional in hardwaremain.c Otherwise it breaks 486 boards without RDTSC, ending with exception 6. It ends like this on bifferboard: Jumping to image. Unexpected Exception: 6 @ 10:001007e3 - Halting Code: 0 eflags: 00000016 eax: 001001fe ebx: 00100118 ecx: 00000000 edx: 00108e00 edi: 0010aaf8 esi: 00000000 ebp: 00117ff4 esp: 00117fd8 Please keep in mind 486, dont use rdtsc/cpuid in generic code, or if you do make sure make it non-default option. Change that broke it: http://review.coreboot.org/#/c/749/7/src/boot/hardwaremain.c Change-Id: I974b25377c20a11430b35b24dcc275d8cbfd2b9a Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Apr 24 18:19:54 2012, giving +2 See http://review.coreboot.org/925 for details. -gerrit

1 0

← Newer
1
...
11
12
13
14
15
16
17
...
46
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2012