coreboot April 2012

coreboot@coreboot.org

39 participants
459 discussions

timestamping broke 486 board
by Rudolf Marek 24 Apr '12

24 Apr '12

Hi Recent addition of timestamping stuff broke the only 486 board supported by coreboot, the bifferboard. It ends like this: Jumping to image. Unexpected Exception: 6 @ 10:001007e3 - Halting Code: 0 eflags: 00000016 eax: 001001fe ebx: 00100118 ecx: 00000000 edx: 00108e00 edi: 0010aaf8 esi: 00000000 ebp: 00117ff4 esp: 00117fd8 Please keep in mind 486, dont use rdtsc/cpuid in generic code, or if you do make sure make it non-default option. I fixed that with simple #if stuff http://review.coreboot.org/#/c/925/ Please have a look to patch as soon as possible I wanted to announce the bifferboard stuff and this is kind of show stopper. Thanks Rudolf

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Patch set updated for coreboot: 1896e2a Make timestamp collection conditional in hardwaremain.c
by Rudolf Marek 24 Apr '12

24 Apr '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/925 -gerrit commit 1896e2a19c848725a30833eabe0f12b10a714527 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue Apr 24 16:01:24 2012 +0200 Make timestamp collection conditional in hardwaremain.c Otherwise it breaks 486 boards without RDTSC, ending with exception 6. It ends like this on bifferboard: Jumping to image. Unexpected Exception: 6 @ 10:001007e3 - Halting Code: 0 eflags: 00000016 eax: 001001fe ebx: 00100118 ecx: 00000000 edx: 00108e00 edi: 0010aaf8 esi: 00000000 ebp: 00117ff4 esp: 00117fd8 Please keep in mind 486, dont use rdtsc/cpuid in generic code, or if you do make sure make it non-default option. Change that broke it: http://review.coreboot.org/#/c/749/7/src/boot/hardwaremain.c Change-Id: I974b25377c20a11430b35b24dcc275d8cbfd2b9a Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/boot/hardwaremain.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 489caa3..532135f 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -57,9 +57,10 @@ void hardwaremain(int boot_complete); void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; +#if CONFIG_COLLECT_TIMESTAMPS tsc_t timestamps[6]; - timestamps[0] = rdtsc(); +#endif post_code(POST_ENTRY_RAMSTAGE); /* console_init() MUST PRECEDE ALL printk()! */ @@ -81,26 +82,37 @@ void hardwaremain(int boot_complete) /* FIXME: Is there a better way to handle this? */ init_timer(); +#if CONFIG_COLLECT_TIMESTAMPS timestamps[1] = rdtsc(); +#endif /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); post_code(POST_DEVICE_ENUMERATION_COMPLETE); +#if CONFIG_COLLECT_TIMESTAMPS timestamps[2] = rdtsc(); +#endif /* Now compute and assign the bus resources. */ dev_configure(); post_code(POST_DEVICE_CONFIGURATION_COMPLETE); +#if CONFIG_COLLECT_TIMESTAMPS timestamps[3] = rdtsc(); +#endif /* Now actually enable devices on the bus */ dev_enable(); +#if CONFIG_COLLECT_TIMESTAMPS timestamps[4] = rdtsc(); +#endif /* And of course initialize devices on the bus */ dev_initialize(); post_code(POST_DEVICES_ENABLED); +#if CONFIG_COLLECT_TIMESTAMPS timestamps[5] = rdtsc(); +#endif + #if CONFIG_WRITE_HIGH_TABLES == 1 cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM

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New patch to review for coreboot: 2b7ed8b Make timestamp collection conditional in hardwaremain.c
by Rudolf Marek 24 Apr '12

24 Apr '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/925 -gerrit commit 2b7ed8b0b48be0c12280eaa08b11626fcca598d8 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue Apr 24 16:01:24 2012 +0200 Make timestamp collection conditional in hardwaremain.c Otherwise it breaks 486 boards without RDTSC, ending with exception 6. Change-Id: I974b25377c20a11430b35b24dcc275d8cbfd2b9a Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/boot/hardwaremain.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 489caa3..532135f 100644 --- a/src/boot/hardwaremain.c +++ b/src/boot/hardwaremain.c @@ -57,9 +57,10 @@ void hardwaremain(int boot_complete); void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; +#if CONFIG_COLLECT_TIMESTAMPS tsc_t timestamps[6]; - timestamps[0] = rdtsc(); +#endif post_code(POST_ENTRY_RAMSTAGE); /* console_init() MUST PRECEDE ALL printk()! */ @@ -81,26 +82,37 @@ void hardwaremain(int boot_complete) /* FIXME: Is there a better way to handle this? */ init_timer(); +#if CONFIG_COLLECT_TIMESTAMPS timestamps[1] = rdtsc(); +#endif /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); post_code(POST_DEVICE_ENUMERATION_COMPLETE); +#if CONFIG_COLLECT_TIMESTAMPS timestamps[2] = rdtsc(); +#endif /* Now compute and assign the bus resources. */ dev_configure(); post_code(POST_DEVICE_CONFIGURATION_COMPLETE); +#if CONFIG_COLLECT_TIMESTAMPS timestamps[3] = rdtsc(); +#endif /* Now actually enable devices on the bus */ dev_enable(); +#if CONFIG_COLLECT_TIMESTAMPS timestamps[4] = rdtsc(); +#endif /* And of course initialize devices on the bus */ dev_initialize(); post_code(POST_DEVICES_ENABLED); +#if CONFIG_COLLECT_TIMESTAMPS timestamps[5] = rdtsc(); +#endif + #if CONFIG_WRITE_HIGH_TABLES == 1 cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM

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New patch to review for coreboot: 32b3e00 rk886: Add ACPI support for LID switch
by Patrick Georgi 24 Apr '12

24 Apr '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/924 -gerrit commit 32b3e0095d7ff432732ddb08e24390454f41e7e3 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Apr 20 15:31:16 2012 +0200 rk886: Add ACPI support for LID switch Change-Id: Ib5a34491531228db9a9232322bd573fded27ee67 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/mainboard/roda/rk886ex/acpi/mainboard.asl | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/roda/rk886ex/acpi/mainboard.asl b/src/mainboard/roda/rk886ex/acpi/mainboard.asl index 4be20c3..866a0b0 100644 --- a/src/mainboard/roda/rk886ex/acpi/mainboard.asl +++ b/src/mainboard/roda/rk886ex/acpi/mainboard.asl @@ -24,7 +24,7 @@ Device (LID0) Name(_HID, EisaId("PNP0C0D")) Method(_LID, 0) { - Return (1) + Return (\_SB.PCI0.LPCB.EC0.P61S) } }

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Regarding patch review of 707
by manasa gv 24 Apr '12

24 Apr '12

Hi, I am using Fedora16.. How to compile and test the assemebly program of patch 707 that is '.inc file' ?? Specially entry16.inc file in coreboot.. Below given is the File path. src/cpu/x86/16bit/entry16.inc I am new to this coreboot..please guide me ... Thanks, Manasa

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Patch merged into coreboot/master: 4fe7af0 Fix whitespace for ma785gm
by gerrit＠coreboot.org 24 Apr '12

24 Apr '12

the following patch was just integrated into master: commit 4fe7af04db174d448dc26b9db44f7872587ab533 Author: Alec Ari <neotheuser(a)ymail.com> Date: Mon Apr 23 20:24:24 2012 -0500 Fix whitespace for ma785gm Fix tabs and whitespace for ma785gm mainboard.c file. Change-Id: I8c94bf428bc4e78871da8c64f89221af4151e16d Signed-off-by: Alec Ari <neotheuser(a)ymail.com> Build-Tested: build bot (Jenkins) at Tue Apr 24 03:50:57 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue Apr 24 03:58:17 2012, giving +2 See http://review.coreboot.org/923 for details. -gerrit

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Patch merged into coreboot/master: f54b484 Update MA785GM code
by gerrit＠coreboot.org 24 Apr '12

24 Apr '12

the following patch was just integrated into master: commit f54b4841a182a7418de5f54b05df8c6bdab1cc51 Author: Alec Ari <neotheuser(a)ymail.com> Date: Mon Apr 23 20:12:30 2012 -0500 Update MA785GM code This commit adds the following to MA785GM: Refactor some alignment handling Unify Local APIC address definitions ACPI: More ../../.. removal Remove old AMD fam10 fixme comment amd/sb700: Move HAVE_HARD_RESET to southbridge Change-Id: I85a95bb641375dd61d1f58a2f2f972771d1d9ad9 Signed-off-by: Alec Ari <neotheuser(a)ymail.com> Build-Tested: build bot (Jenkins) at Tue Apr 24 03:39:32 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue Apr 24 03:57:45 2012, giving +2 See http://review.coreboot.org/922 for details. -gerrit

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New patch to review for coreboot: 4fe7af0 Fix whitespace for ma785gm
by Alec Ari 24 Apr '12

24 Apr '12

Alec Ari (neotheuser(a)ymail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/923 -gerrit commit 4fe7af04db174d448dc26b9db44f7872587ab533 Author: Alec Ari <neotheuser(a)ymail.com> Date: Mon Apr 23 20:24:24 2012 -0500 Fix whitespace for ma785gm Fix tabs and whitespace for ma785gm mainboard.c file. Change-Id: I8c94bf428bc4e78871da8c64f89221af4151e16d Signed-off-by: Alec Ari <neotheuser(a)ymail.com> --- src/mainboard/gigabyte/ma785gm/mainboard.c | 22 +++++++++++----------- 1 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index 97a86f6..989dfb5 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -91,7 +91,7 @@ void set_pcie_reset() */ int is_dev3_present(void) { - return 0; + return 0; } /* @@ -122,16 +122,16 @@ static void set_gpio40_gfx(void) sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); /* set the gfx to 1x16 lanes */ - printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); - /* when the gpio40 is configured as GPIO, this will enable the output */ - pci_write_config32(sm_dev, 0xf8, 0x4); - dword = pci_read_config32(sm_dev, 0xfc); - dword &= ~(1 << 10); - - /* When the gpio40 is configured as GPIO, this will represent the output value*/ - /* 1 :enable two x8 , 0 : master slot enable only */ - dword &= ~(1 << 26); - pci_write_config32(sm_dev, 0xfc, dword); + printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); + /* when the gpio40 is configured as GPIO, this will enable the output */ + pci_write_config32(sm_dev, 0xf8, 0x4); + dword = pci_read_config32(sm_dev, 0xfc); + dword &= ~(1 << 10); + + /* When the gpio40 is configured as GPIO, this will represent the output value*/ + /* 1 :enable two x8 , 0 : master slot enable only */ + dword &= ~(1 << 26); + pci_write_config32(sm_dev, 0xfc, dword); } /*************************************************

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New patch to review for coreboot: f54b484 Update MA785GM code
by Alec Ari 24 Apr '12

24 Apr '12

Alec Ari (neotheuser(a)ymail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/922 -gerrit commit f54b4841a182a7418de5f54b05df8c6bdab1cc51 Author: Alec Ari <neotheuser(a)ymail.com> Date: Mon Apr 23 20:12:30 2012 -0500 Update MA785GM code This commit adds the following to MA785GM: Refactor some alignment handling Unify Local APIC address definitions ACPI: More ../../.. removal Remove old AMD fam10 fixme comment amd/sb700: Move HAVE_HARD_RESET to southbridge Change-Id: I85a95bb641375dd61d1f58a2f2f972771d1d9ad9 Signed-off-by: Alec Ari <neotheuser(a)ymail.com> --- src/mainboard/gigabyte/ma785gm/Kconfig | 1 - src/mainboard/gigabyte/ma785gm/acpi_tables.c | 20 ++++++++++---------- src/mainboard/gigabyte/ma785gm/dsdt.asl | 4 ++-- src/mainboard/gigabyte/ma785gm/mptable.c | 2 +- src/mainboard/gigabyte/ma785gm/romstage.c | 1 - 5 files changed, 13 insertions(+), 15 deletions(-) diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig index 1357104..0e8011b 100644 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ b/src/mainboard/gigabyte/ma785gm/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/gigabyte/ma785gm/acpi_tables.c b/src/mainboard/gigabyte/ma785gm/acpi_tables.c index 1b2ea6e..09d1e42 100644 --- a/src/mainboard/gigabyte/ma785gm/acpi_tables.c +++ b/src/mainboard/gigabyte/ma785gm/acpi_tables.c @@ -110,7 +110,7 @@ unsigned long write_acpi_tables(unsigned long start) get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* Align ACPI tables to 16 bytes */ - start = (start + 0x0f) & -0x10; + start = ALIGN(start, 16); current = start; printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); @@ -130,7 +130,7 @@ unsigned long write_acpi_tables(unsigned long start) /* * We explicitly add these tables later on: */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); hpet = (acpi_hpet_t *) current; current += sizeof(acpi_hpet_t); @@ -138,7 +138,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, hpet); /* If we want to use HPET Timers Linux wants an MADT */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); madt = (acpi_madt_t *) current; acpi_create_madt(madt); @@ -146,7 +146,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, madt); /* SRAT */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); srat = (acpi_srat_t *) current; acpi_create_srat(srat); @@ -154,7 +154,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, srat); /* SLIT */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); slit = (acpi_slit_t *) current; acpi_create_slit(slit); @@ -162,7 +162,7 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; + current = ALIGN(current, 16); printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); ssdt = (acpi_header_t *)current; memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); @@ -191,7 +191,7 @@ unsigned long write_acpi_tables(unsigned long start) } else { c = (u8) ('A' + i - 1 - 6); } - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt ssdtx = (acpi_header_t *)current; switch (sysconf.hcid[i]) { @@ -220,7 +220,7 @@ unsigned long write_acpi_tables(unsigned long start) #endif /* DSDT */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); dsdt = (acpi_header_t *)current; // it will used by fadt memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); @@ -229,14 +229,14 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); /* FACS */ // it needs 64 bit alignment - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current); facs = (acpi_facs_t *) current; // it will be used by fadt current += sizeof(acpi_facs_t); acpi_create_facs(facs); /* FADT */ - current = ( current + 0x07) & -0x08; + current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl index 58352a8..727b32e 100644 --- a/src/mainboard/gigabyte/ma785gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c index 4bf3480..4a276fb 100644 --- a/src/mainboard/gigabyte/ma785gm/mptable.c +++ b/src/mainboard/gigabyte/ma785gm/mptable.c @@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, LAPIC_ADDR); + mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 4572169..68f3dcc 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }

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Patch merged into coreboot/master: bf9d8a4 Intel 82801dx: compile early_smbus as separate object
by gerrit＠coreboot.org 24 Apr '12

24 Apr '12

the following patch was just integrated into master: commit bf9d8a4a9e91db3483353d568cf176d817b283e5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 20 17:11:31 2012 +0300 Intel 82801dx: compile early_smbus as separate object Add early_smbus.c for romstage-y list and remove respective include on mainboard romstage.c files. Tested on AOpen board. Change-Id: I1c7e6cb32e3a9d7cc9b6037dc27e59149d492001 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Apr 20 16:32:30 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Apr 20 21:26:44 2012, giving +2 See http://review.coreboot.org/909 for details. -gerrit

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coreboot April 2012