coreboot April 2012

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Patch merged into coreboot/master: 9bf9535 Add Google ChromeOS vendor support
by gerrit＠coreboot.org 02 Apr '12

02 Apr '12

the following patch was just integrated into master: commit 9bf95351c917904deb99425c738cfb3386f57c35 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 12:01:06 2012 -0700 Add Google ChromeOS vendor support Google's ChromeOS can be booted super fast and safely using coreboot. This adds the ChromeOS specific code that is required by all ChromeBooks to do this. Change-Id: Ic03ff090a569a27acbd798ce1e5f89a34897a2f2 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sat Mar 31 00:38:27 2012, giving +1 See http://review.coreboot.org/817 for details. -gerrit

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Patch merged into coreboot/master: 051b64d Force coreboot mconf to create temp files in the output directory
by gerrit＠coreboot.org 02 Apr '12

02 Apr '12

the following patch was just integrated into master: commit 051b64d6dda2a829454e5df752134dcbb0a35ba1 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Oct 24 14:06:23 2011 -0700 Force coreboot mconf to create temp files in the output directory This change partially addresses the problem with attempting to generate coreboot image out of tree. The configuration step fails when in cheroot, if the destination directory is placed in /tmp. The problem is that the mconf package tries renaming the temporary file created in the local directory into the destination config file. If the destination root and the local directory are located on different file systems, the rename operation fails. The proper fix (still upcoming) would be to identify all places where mconf creates temp files, and make sure that all temp files get created in the destination tree. This change modifies just one location, which prevents building out of tree in the most common case. Test: run the following in the coreboot directory in chroot: (coreboot) cp config.lumpy .config (coreboot) /bin/rm -rf /tmp/cb (coreboot) CROSS_COMPILE=i686-pc-linux-gnu- make obj=/tmp/cb oldconfig (coreboot) CROSS_COMPILE=i686-pc-linux-gnu- make obj=/tmp/cb Observe the build succeed (it was failing during the config phase before this change) Change-Id: If4506e984b8afc192a1689c7b0aa956dd35f66c6 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Build-Tested: build bot (Jenkins) at Fri Mar 30 21:57:40 2012, giving +1 See http://review.coreboot.org/815 for details. -gerrit

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Patch merged into coreboot/master: 41c6065 Add a "remove" command to cbfstool
by gerrit＠coreboot.org 02 Apr '12

02 Apr '12

the following patch was just integrated into master: commit 41c6065a48ad409b8d2dbf9d54e42df263c2939f Author: Gabe Black <gabeblack(a)google.com> Date: Fri Jan 27 00:33:47 2012 -0800 Add a "remove" command to cbfstool This command removes the first file it finds with the given name by changing its type to CBFS_COMPONENT_NULL and setting the first character of its name to a null terminator. If the "files" immediately before or after the target file are already marked as empty, they're all merged together into one large file. Change-Id: Idc6b2a4c355c3f039c2ccae81866e3ed6035539b Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-by: Ronald G. Minnich <rminnich(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 30 21:44:41 2012, giving +1 See http://review.coreboot.org/814 for details. -gerrit

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Trac reminder: list of new ticket(s)
by coreboot tracker 02 Apr '12

02 Apr '12

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New patch to review for coreboot: 0c24725 Makefile: rename coreboot_ap linking filenames
by Kyösti Mälkki 02 Apr '12

02 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/840 -gerrit commit 0c2472511c3f90db69e224d267ebedbe9a2f033c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 2 11:03:49 2012 +0300 Makefile: rename coreboot_ap linking filenames $(obj)/coreboot_ap -> $(obj)/ramstage/ramstage_ap.elf It is really a ramstage for AP CPU and not a romstage, it is not enabled for any mainboard by default, and it doesn't compile even if enabled. Change-Id: Ifb9c5cb6df65309660b000876cf6a9a3da9b6839 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 18 +++++++----------- 1 files changed, 7 insertions(+), 11 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6b60db0..a878a60 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -47,7 +47,7 @@ ifeq ($(CONFIG_PAYLOAD_FILO),y) COREBOOT_ROM_DEPENDENCIES+=filo endif ifeq ($(CONFIG_AP_CODE_IN_CAR),y) -COREBOOT_ROM_DEPENDENCIES+=$(obj)/coreboot_ap +COREBOOT_ROM_DEPENDENCIES+=$(obj)/ramstage/ramstage_ap.elf endif ifeq ($(CONFIG_GEODE_VSA_FILE),y) COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_VSA_FILENAME) @@ -76,9 +76,9 @@ endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/ramstage/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp - if [ -f $(obj)/coreboot_ap ]; \ + if [ -f $(obj)/ramstage/ramstage_ap.elf ]; \ then \ - $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ap $(CONFIG_CBFS_PREFIX)/coreboot_ap $(CBFS_COMPRESS_FLAG); \ + $(CBFSTOOL) $@.tmp add-stage $(obj)/ramstage/ramstage_ap.elf $(CONFIG_CBFS_PREFIX)/coreboot_ap $(CBFS_COMPRESS_FLAG); \ fi $(CBFSTOOL) $@.tmp add-stage $(obj)/ramstage/ramstage.elf $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @@ -164,21 +164,17 @@ $(obj)/ramstage/coreboot.a: $$(ramstage-objs) $(AR) cr $@ $^ ####################################################################### -# coreboot_ap.rom +# Ramstage for AP CPU (AMD K8, obsolete?) -ifeq ($(CONFIG_AP_CODE_IN_CAR),y) - -$(obj)/coreboot_ap: $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o +$(obj)/ramstage/ramstage_ap.elf: $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(src)/arch/x86/init/ldscript_apc.lb $^ - $(OBJCOPY) --only-keep-debug $@.tmp $@.debug + $(OBJCOPY) --only-keep-debug $@.tmp $(basename $(a)).debug $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$@.debug $@.tmp + $(OBJCOPY) --add-gnu-debuglink=$(basename $(a)).debug $@.tmp $(NM) -n $@.tmp | sort > $@.map mv $@.tmp $@ -endif - ####################################################################### # done

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New patch to review for coreboot: 64762db Makefile: rename ramstage linking filenames
by Kyösti Mälkki 02 Apr '12

02 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/839 -gerrit commit 64762db28b9275373877a83ca6e6079c45b8e3f4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 2 10:53:22 2012 +0300 Makefile: rename ramstage linking filenames $(obj)/coreboot_ram -> $(obj)/ramstage/ramstage.elf $(obj)/coreboot_ram.map -> $(obj)/ramstage/ramstage.map $(obj)/coreboot_ram.debug -> $(obj)/ramstage/ramstage.debug $(obj)/coreboot_ram.o -> $(obj)/ramstage/coreboot_ram.o $(obj)/coreboot.a -> $(obj)/ramstage/coreboot.a Change-Id: I0046f68938be81b8efa525aa50b39328ca02ecb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 25 +++++++++++++------------ 1 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a245749..6b60db0 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -73,14 +73,14 @@ $(obj)/coreboot.pre1: $(CBFSTOOL) mv $(obj)/coreboot.rom $@ endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/coreboot_ram $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/ramstage/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp if [ -f $(obj)/coreboot_ap ]; \ then \ $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ap $(CONFIG_CBFS_PREFIX)/coreboot_ap $(CBFS_COMPRESS_FLAG); \ fi - $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) + $(CBFSTOOL) $@.tmp add-stage $(obj)/ramstage/ramstage.elf $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @printf " PAYLOAD \e[1;31mnone (as specified by user)\e[0m\n" endif @@ -144,23 +144,24 @@ $(objutil)/options/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src ####################################################################### # Build the coreboot_ram (stage 2) -$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld #ldoptions +$(obj)/ramstage/ramstage.elf: $(obj)/ramstage/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $(obj)/coreboot_ram.o - $(NM) -n $@.tmp | sort > $@.map - $(OBJCOPY) --only-keep-debug $@.tmp $@.debug + $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $< + $(NM) -n $@.tmp | sort > $(basename $(a)).map + $(OBJCOPY) --only-keep-debug $@.tmp $(basename $(a)).debug $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$@.debug $@.tmp + $(OBJCOPY) --add-gnu-debuglink=$(basename $(a)).debug $@.tmp mv $@.tmp $@ -$(obj)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(obj)/coreboot.a $(LIBGCC_FILE_NAME) +$(obj)/ramstage/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(obj)/ramstage/coreboot.a $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(obj)/ramstage/coreboot.a $(LIBGCC_FILE_NAME) -Wl,--end-group -$(obj)/coreboot.a: $$(ramstage-objs) +$(obj)/ramstage/coreboot.a: $$(ramstage-objs) @printf " AR $(subst $(obj)/,,$(@))\n" - rm -f $(obj)/coreboot.a - $(AR) cr $(obj)/coreboot.a $^ + mkdir -p $(dir $@) + rm -f $@ + $(AR) cr $@ $^ ####################################################################### # coreboot_ap.rom

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New patch to review for coreboot: 0decc56 Makefile: rename bootblock linking filenames
by Kyösti Mälkki 02 Apr '12

02 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/838 -gerrit commit 0decc56167e52d65a7729d6fe6b93a8ce7f34214 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 2 10:50:01 2012 +0300 Makefile: rename bootblock linking filenames $(obj)/coreboot.bootblock -> $(obj)/bootblock/bootblock.bin $(obj)/bootblock.elf -> $(obj)/bootblock/bootblock.elf $(obj)/bootblock.map -> $(obj)/bootblock/bootblock.map $(obj)/bootblock.debug -> $(obj)/bootblock/bootblock.debug Change-Id: I0365304e1b0ed02a5a3ec720b0cf3e303eaefa7c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 00e7b86..a245749 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -63,8 +63,8 @@ prebuild-files = \ $(call extract_nth,4,$(file)) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL) - $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock +$(obj)/coreboot.pre1: $(obj)/bootblock/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) + $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/bootblock/bootblock.bin $(prebuild-files) true mv $@.tmp $@ else @@ -280,7 +280,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) ####################################################################### # Build the bootblock -$(obj)/coreboot.bootblock: $(obj)/bootblock.elf +$(obj)/bootblock/bootblock.bin: $(obj)/bootblock/bootblock.elf @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" $(OBJCOPY) -O binary $< $@ @@ -332,13 +332,13 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",, $< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ -$(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld +$(obj)/bootblock/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(obj)/bootblock/ldscript.ld $< - $(NM) -n $@.tmp | sort > $(obj)/bootblock.map - $(OBJCOPY) --only-keep-debug $@.tmp $(obj)/bootblock.debug + $(NM) -n $@.tmp | sort > $(basename $(a)).map + $(OBJCOPY) --only-keep-debug $@.tmp $(basename $(a)).debug $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@.tmp + $(OBJCOPY) --add-gnu-debuglink=$(basename $(a)).debug $@.tmp mv $@.tmp $@ #######################################################################

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PCI target burst mode
by Nathan Williams 01 Apr '12

01 Apr '12

Hi, On our Geos boards (AMD Geode LX) we have an FPGA on the PCI bus that currently only behaves as a PCI Target without burst mode. Rather than convert the FPGA design to a PCI Initiator with DMA, we are hoping to make some minor changes to support burst reads from the FPGA. However, while testing an FPGA design that should support burst reads we noticed with a logic analyser that the Geode LX continues to only do single target transfers. Does anyone have any suggestions for what we could try to find out what's going on? Are there some MSRs that need to be set to enable burst mode? Regards, Nathan

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New patch to review for coreboot: 1d6bf8b x86, oprom: ensure DF is always cleared
by Mathias Krause 01 Apr '12

01 Apr '12

Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/837 -gerrit commit 1d6bf8be4ee126217544fabe1c39fe22317ddda0 Author: Mathias Krause <minipli(a)googlemail.com> Date: Sun Apr 1 11:32:09 2012 +0200 x86, oprom: ensure DF is always cleared The Option ROM might mess with the EFLAGS register and break assumptions the C part of coreboot implicitly has, e.g. the state of the direction flag. Prevent Option ROMs from confusing coreboot by restoring the old EFLAGS value after the Option ROMs has finished and always clear the direction flag before calling the C part of the interrupt handler. Change-Id: I84663be6681b17f95f48d93f0b730e443336b4a8 Signed-off-by: Mathias Krause <minipli(a)googlemail.com> --- src/devices/oprom/x86_asm.S | 65 ++++++++++++++++++++++++------------------ 1 files changed, 37 insertions(+), 28 deletions(-) diff --git a/src/devices/oprom/x86_asm.S b/src/devices/oprom/x86_asm.S index 488bfa6..56ebb3a 100644 --- a/src/devices/oprom/x86_asm.S +++ b/src/devices/oprom/x86_asm.S @@ -75,35 +75,36 @@ __buffer = RELOCATED(.) .globl __realmode_call __realmode_call = RELOCATED(.) /* save all registers to the stack */ - pushal + pusha + pushf - /* Move the protected mode stack to a safe place */ + /* Move the protected mode stack pointer to a safe place */ movl %esp, __stack - movl %esp, %ebp + movl %esp, %ebp - /* This function is called with regparm=0 and we have - * to skip the 32 byte from pushal. Hence start at 36. + /* This function is called with regparm=0 and we have to + * skip the 36 byte from pushf+pusha. Hence start at 40. */ /* entry point */ - movl 36(%ebp), %eax + movl 40(%ebp), %eax mov %ax, __lcall_instr + 1 andl $0xffff0000, %eax shrl $4, %eax mov %ax, __lcall_instr + 3 /* initial register values */ - movl 40(%ebp), %eax - movl %eax, __registers + 0 /* eax */ movl 44(%ebp), %eax - movl %eax, __registers + 4 /* ebx */ + movl %eax, __registers + 0 /* eax */ movl 48(%ebp), %eax - movl %eax, __registers + 8 /* ecx */ + movl %eax, __registers + 4 /* ebx */ movl 52(%ebp), %eax - movl %eax, __registers + 12 /* edx */ + movl %eax, __registers + 8 /* ecx */ movl 56(%ebp), %eax - movl %eax, __registers + 16 /* esi */ + movl %eax, __registers + 12 /* edx */ movl 60(%ebp), %eax + movl %eax, __registers + 16 /* esi */ + movl 64(%ebp), %eax movl %eax, __registers + 20 /* edi */ /* Activate the right segment descriptor real mode. */ @@ -193,41 +194,45 @@ __lcall_instr = RELOCATED(.) /* restore proper idt */ lidt idtarg - /* and exit */ + /* restore stack pointer, eflags and register values */ movl __stack, %esp - popal + popf + popa + /* and exit */ // TODO return AX from OPROM call ret .globl __realmode_interrupt __realmode_interrupt = RELOCATED(.) /* save all registers to the stack */ - pushal - /* save the stack */ + pusha + pushf + + /* save the stack pointer */ movl %esp, __stack - movl %esp, %ebp + movl %esp, %ebp - /* This function is called with regparm=0 and we have - * to skip the 32 byte from pushal. Hence start at 36. + /* This function is called with regparm=0 and we have to + * skip the 36 byte from pushf+pusha. Hence start at 40. */ /* prepare interrupt calling code */ - movl 36(%ebp), %eax + movl 40(%ebp), %eax movb %al, __intXX_instr + 1 /* intno */ /* initial register values */ - movl 40(%ebp), %eax - movl %eax, __registers + 0 /* eax */ movl 44(%ebp), %eax - movl %eax, __registers + 4 /* ebx */ + movl %eax, __registers + 0 /* eax */ movl 48(%ebp), %eax - movl %eax, __registers + 8 /* ecx */ + movl %eax, __registers + 4 /* ebx */ movl 52(%ebp), %eax - movl %eax, __registers + 12 /* edx */ + movl %eax, __registers + 8 /* ecx */ movl 56(%ebp), %eax - movl %eax, __registers + 16 /* esi */ + movl %eax, __registers + 12 /* edx */ movl 60(%ebp), %eax + movl %eax, __registers + 16 /* esi */ + movl 64(%ebp), %eax movl %eax, __registers + 20 /* edi */ /* This configures CS properly for real mode. */ @@ -309,9 +314,10 @@ __intXX_instr = RELOCATED(.) /* restore coreboot's 32-bit IDT */ lidt idtarg - /* Exit */ + /* restore stack pointer, eflags and register values and exit */ movl __stack, %esp - popal + popf + popa ret /* This is the 16-bit interrupt entry point called by the IDT stub code. @@ -327,6 +333,9 @@ __interrupt_handler_16bit = RELOCATED(.) push %fs push %gs + /* Clear DF to not break ABI assumptions */ + cld + /* Clean up the interrupt number. We could have done this in the stub, * but it would have cost 2 more bytes per stub entry. */

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coreboot April 2012