April 2012 - coreboot - mail.coreboot.org

Patch merged into coreboot/master: 6555dcc Add preprocessing capabilities to the cbfs-files mechanism
by gerrit＠coreboot.org April 3, 2012

April 3, 2012

the following patch was just integrated into master: commit 6555dcc1828a30615b98652cccd80f707550a7fe Author: Patrick Georgi <Patrick.Georgi(a)secunet.com> Date: Fri Mar 9 12:30:07 2012 +0100 Add preprocessing capabilities to the cbfs-files mechanism It's now possible to generate files that are about to be added to CBFS by specifying "sourcefile:method" as real file name. This makes the build system use the cbfs-files-preprocessor-$(method) function to create a file from sourcefile. That generated file is then added to CBFS. The first method to be defined is "nvramtool". It expects a plain text specification of the CMOS configuration and emits the binary format suitable for cmos.default. Change-Id: I33a142718fc7238eaf5317b0ed62b4726d9b48f2 Signed-off-by: Patrick Georgi <Patrick.Georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Apr 3 16:44:03 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Apr 3 18:33:22 2012, giving +2 See http://review.coreboot.org/847 for details. -gerrit

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Patch merged into coreboot/master: aa1c0e6 Add nvramtool to coreboot build system
by gerrit＠coreboot.org April 3, 2012

April 3, 2012

the following patch was just integrated into master: commit aa1c0e6a1ba943f011cdf84354c3811b7111bac0 Author: Patrick Georgi <Patrick.Georgi(a)secunet.com> Date: Fri Mar 9 10:53:52 2012 +0100 Add nvramtool to coreboot build system This way we can depend on it during build. Change-Id: I7e773c6a029e376e3d70d0a8c9e96ffe0c2cf82e Signed-off-by: Patrick Georgi <Patrick.Georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Apr 3 16:16:36 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Apr 3 18:32:23 2012, giving +2 See http://review.coreboot.org/845 for details. -gerrit

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New patch to review for coreboot: 6555dcc Add preprocessing capabilities to the cbfs-files mechanism
by Patrick Georgi April 3, 2012

April 3, 2012

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/847 -gerrit commit 6555dcc1828a30615b98652cccd80f707550a7fe Author: Patrick Georgi <Patrick.Georgi(a)secunet.com> Date: Fri Mar 9 12:30:07 2012 +0100 Add preprocessing capabilities to the cbfs-files mechanism It's now possible to generate files that are about to be added to CBFS by specifying "sourcefile:method" as real file name. This makes the build system use the cbfs-files-preprocessor-$(method) function to create a file from sourcefile. That generated file is then added to CBFS. The first method to be defined is "nvramtool". It expects a plain text specification of the CMOS configuration and emits the binary format suitable for cmos.default. Change-Id: I33a142718fc7238eaf5317b0ed62b4726d9b48f2 Signed-off-by: Patrick Georgi <Patrick.Georgi(a)secunet.com> --- Makefile.inc | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 470077e..81d40df 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -79,12 +79,26 @@ $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h endef ####################################################################### +# Parse plaintext cmos defaults into binary format +# arg1: source file +# arg2: binary file name +cbfs-files-processor-nvramtool= \ + $(eval $(2): $(1) $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout | $(objutil)/nvramtool/nvramtool ; \ + printf " CREATE $(2) (from $(1))\n"; $(objutil)/nvramtool/nvramtool -y $(src)/mainboard/$(MAINBOARDDIR)/cmos.layout -D $(2).tmp -p $(1) && mv $(2).tmp $(2)) + +####################################################################### # Add handler for arbitrary files in CBFS $(call add-special-class,cbfs-files) cbfs-files-handler= \ + $(eval tmp-cbfs-method:=$(word 2, $(subst :, ,$($(2)-file)))) \ + $(eval $(2)-file:=$(word 1, $(subst :, ,$($(2)-file)))) \ $(if $(wildcard $(1)$($(2)-file)), \ $(eval tmp-cbfs-file:= $(wildcard $(1)$($(2)-file))), \ $(eval tmp-cbfs-file:= $($(2)-file))) \ + $(if $(tmp-cbfs-method), \ + $(eval tmp-old-cbfs-file:=$(tmp-cbfs-file)) \ + $(eval tmp-cbfs-file:=$(shell mktemp $(obj)/mainboard/$(MAINBOARDDIR)/cbfs-file.XXXXXX).out) \ + $(call cbfs-files-processor-$(tmp-cbfs-method),$(tmp-old-cbfs-file),$(tmp-cbfs-file))) \ $(eval cbfs-files += $(tmp-cbfs-file)|$(2)|$($(2)-type)|$($(2)-position)) \ $(eval $(2)-name:=) \ $(eval $(2)-type:=) \

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New patch to review for coreboot: aa1c0e6 Add nvramtool to coreboot build system
by Patrick Georgi April 3, 2012

April 3, 2012

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/845 -gerrit commit aa1c0e6a1ba943f011cdf84354c3811b7111bac0 Author: Patrick Georgi <Patrick.Georgi(a)secunet.com> Date: Fri Mar 9 10:53:52 2012 +0100 Add nvramtool to coreboot build system This way we can depend on it during build. Change-Id: I7e773c6a029e376e3d70d0a8c9e96ffe0c2cf82e Signed-off-by: Patrick Georgi <Patrick.Georgi(a)secunet.com> --- Makefile.inc | 2 +- util/nvramtool/Makefile.inc | 48 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 1 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 857ad16..470077e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -40,7 +40,7 @@ PHONY+= clean-abuild coreboot lint lint-stable # root source directories of coreboot subdirs-y := src/lib src/boot src/console src/devices src/ec src/southbridge subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode -subdirs-y += util/cbfstool util/sconfig +subdirs-y += util/cbfstool util/sconfig util/nvramtool subdirs-y += src/arch/$(ARCHDIR-y) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += src/vendorcode diff --git a/util/nvramtool/Makefile.inc b/util/nvramtool/Makefile.inc new file mode 100644 index 0000000..25d447d --- /dev/null +++ b/util/nvramtool/Makefile.inc @@ -0,0 +1,48 @@ +## +## Integration of nvramtool into the coreboot build system +## +## (C) 2005-2008 coresystems GmbH +## written by Stefan Reinauer <stepan(a)coresystems.de> +## (C) 2012 secunet Security Networks AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +OS_ARCH = $(shell uname) +NVRAMTOOLFLAGS := -I$(top)/util/nvramtool +ifeq ($(OS_ARCH), Darwin) +NVRAMTOOLFLAGS += -framework DirectHW +endif +ifeq ($(OS_ARCH), NetBSD) +NVRAMTOOLFLAGS += -l$(shell uname -p) +endif + +nvramtoolobj := +nvramtoolobj += cli/nvramtool.o cli/opts.o +nvramtoolobj += cmos_lowlevel.o cmos_ops.o common.o compute_ip_checksum.o +nvramtoolobj += hexdump.o input_file.o layout.o accessors/layout-text.o accessors/layout-bin.o lbtable.o +nvramtoolobj += reg_expr.o cbfs.o accessors/cmos-hw-unix.o accessors/cmos-mem.o + +$(objutil)/nvramtool $(objutil)/nvramtool/accessors $(objutil)/nvramtool/cli: + mkdir -p $@ + +$(objutil)/nvramtool/%.o: $(top)/util/nvramtool/%.c + printf " HOSTCC $(subst $(objutil)/,,$(@))\n" + $(HOSTCC) $(NVRAMTOOLFLAGS) $(HOSTCFLAGS) -c -o $@ $< + +$(objutil)/nvramtool/nvramtool: $(objutil)/nvramtool $(objutil)/nvramtool/accessors $(objutil)/nvramtool/cli $(addprefix $(objutil)/nvramtool/,$(nvramtoolobj)) + printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" + $(HOSTCC) $(NVRAMTOOLFLAGS) -o $@ $(addprefix $(objutil)/nvramtool/,$(nvramtoolobj)) + +

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New patch to review for coreboot: 14bade0 nvramtool: 64bit safe CBFS handling
by Patrick Georgi April 3, 2012

April 3, 2012

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/846 -gerrit commit 14bade0c228f1ccedca95a39a22d24486cadd16b Author: Patrick Georgi <Patrick.Georgi(a)secunet.com> Date: Fri Mar 9 12:54:03 2012 +0100 nvramtool: 64bit safe CBFS handling Change-Id: I4f23ee04cd6479e55e9467af1b0196936412deb1 Signed-off-by: Patrick Georgi <Patrick.Georgi(a)secunet.com> --- util/nvramtool/cbfs.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/util/nvramtool/cbfs.c b/util/nvramtool/cbfs.c index 8dc8b91..801ee58 100644 --- a/util/nvramtool/cbfs.c +++ b/util/nvramtool/cbfs.c @@ -33,10 +33,10 @@ #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) static void *cbfs_mapped; -static u32 cbfs_offset; +static void *cbfs_offset; static void* virt_to_phys(u32 virt) { - return (void*)(virt+cbfs_offset); + return cbfs_offset + virt; } #ifdef DEBUG @@ -71,11 +71,11 @@ static struct cbfs_header *cbfs_master_header(void) struct cbfs_file *cbfs_find(const char *name) { struct cbfs_header *header = cbfs_master_header(); - unsigned long offset; + void *offset; if (header == NULL) return NULL; - offset = (u32)virt_to_phys(0 - ntohl(header->romsize) + ntohl(header->offset)); + offset = virt_to_phys(0 - ntohl(header->romsize) + ntohl(header->offset)); int align= ntohl(header->align); @@ -88,14 +88,14 @@ struct cbfs_file *cbfs_find(const char *name) int flen = ntohl(file->len); int foffset = ntohl(file->offset); - debug("CBFS: follow chain: %p + %x + %x + align -> ", (void *)offset, foffset, flen); + debug("CBFS: follow chain: %p + %x + %x + align -> ", offset, foffset, flen); - unsigned long oldoffset = offset; - offset = ALIGN(offset + foffset + flen, align); + void *oldoffset = offset; + offset = (void*)ALIGN((uintptr_t)(offset + foffset + flen), align); debug("%p\n", (void *)offset); if (offset <= oldoffset) return NULL; - if (offset < (u32)virt_to_phys(0xFFFFFFFF - ntohl(header->romsize))) + if (offset < virt_to_phys(0xFFFFFFFF - ntohl(header->romsize))) return NULL; } } @@ -141,6 +141,6 @@ void open_cbfs(const char *filename) printf("Couldn't map '%s'\n", filename); exit(-1); } - cbfs_offset = (uint32_t)cbfs_mapped-(0xffffffff-cbfs_stat.st_size+1); + cbfs_offset = cbfs_mapped-(0xffffffff-cbfs_stat.st_size+1); }

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New patch to review for coreboot: 77a6780 Add support for Intel Turbo feature
by Stefan Reinauer April 3, 2012

April 3, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/844 -gerrit commit 77a6780c39fbea5ccd89663cb65e80f95bde7310 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:35:09 2012 -0700 Add support for Intel Turbo feature Change-Id: I166ead7c219083006c2b05859eb18749c6fbe832 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/turbo/Makefile.inc | 1 + src/cpu/intel/turbo/turbo.c | 90 ++++++++++++++++++++++++++++++++++++++ src/include/cpu/intel/turbo.h | 44 ++++++++++++++++++ 3 files changed, 135 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/turbo/Makefile.inc b/src/cpu/intel/turbo/Makefile.inc new file mode 100644 index 0000000..48ec55d --- /dev/null +++ b/src/cpu/intel/turbo/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += turbo.c diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c new file mode 100644 index 0000000..779550e --- /dev/null +++ b/src/cpu/intel/turbo/turbo.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> +#include <arch/cpu.h> + +static int turbo_state = TURBO_UNKNOWN; + +static const char *turbo_state_desc[] = { + [TURBO_UNKNOWN] = "unknown", + [TURBO_UNAVAILABLE] = "unavailable", + [TURBO_DISABLED] = "available but hidden", + [TURBO_ENABLED] = "available and visible" +}; + +/* + * Determine the current state of Turbo and cache it for later. + * Turbo is a package level config so it does not need to be + * enabled on every core. + */ +int get_turbo_state(void) +{ + struct cpuid_result cpuid_regs; + int turbo_en, turbo_cap; + msr_t msr; + + /* Return cached state if available */ + if (turbo_state != TURBO_UNKNOWN) + return turbo_state; + + cpuid_regs = cpuid(CPUID_LEAF_PM); + turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); + + msr = rdmsr(MSR_IA32_MISC_ENABLES); + turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); + + if (!turbo_cap && turbo_en) { + /* Unavailable */ + turbo_state = TURBO_UNAVAILABLE; + } else if (!turbo_cap && !turbo_en) { + /* Available but disabled */ + turbo_state = TURBO_DISABLED; + } else if (turbo_cap && turbo_en) { + /* Available */ + turbo_state = TURBO_ENABLED; + } + + printk(BIOS_INFO, "Turbo is %s\n", turbo_state_desc[turbo_state]); + return turbo_state; +} + +/* + * Try to enable Turbo mode. + */ +void enable_turbo(void) +{ + msr_t msr; + + /* Only possible if turbo is available but hidden */ + if (get_turbo_state() == TURBO_DISABLED) { + /* Clear Turbo Disable bit in Misc Enables */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.hi &= ~H_MISC_DISABLE_TURBO; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Update cached turbo state */ + turbo_state = TURBO_ENABLED; + printk(BIOS_INFO, "Turbo has been enabled\n"); + } +} diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h new file mode 100644 index 0000000..b60c8cf --- /dev/null +++ b/src/include/cpu/intel/turbo.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CPU_INTEL_TURBO_H +#define _CPU_INTEL_TURBO_H + +#define CPUID_LEAF_PM 6 +#define PM_CAP_TURBO_MODE (1 << 1) + +#define MSR_IA32_MISC_ENABLES 0x1a0 +#define H_MISC_DISABLE_TURBO (1 << 6) + +enum { + TURBO_UNKNOWN, + TURBO_UNAVAILABLE, + TURBO_DISABLED, + TURBO_ENABLED, +}; + +/* Return current turbo state */ +int get_turbo_state(void); + +/* Enable turbo */ +void enable_turbo(void); + +#endif

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Patch set updated for coreboot: d2dad4a Add support for Intel Turbo feature
by Stefan Reinauer April 3, 2012

April 3, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/844 -gerrit commit d2dad4a17955030a9632c41fd3a3e581667cd423 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:35:09 2012 -0700 Add support for Intel Turbo feature Change-Id: I166ead7c219083006c2b05859eb18749c6fbe832 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/turbo/Makefile.inc | 1 + src/cpu/intel/turbo/turbo.c | 90 ++++++++++++++++++++++++++++++++++++++ src/include/cpu/intel/turbo.h | 44 ++++++++++++++++++ 3 files changed, 135 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/turbo/Makefile.inc b/src/cpu/intel/turbo/Makefile.inc new file mode 100644 index 0000000..48ec55d --- /dev/null +++ b/src/cpu/intel/turbo/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += turbo.c diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c new file mode 100644 index 0000000..779550e --- /dev/null +++ b/src/cpu/intel/turbo/turbo.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> +#include <arch/cpu.h> + +static int turbo_state = TURBO_UNKNOWN; + +static const char *turbo_state_desc[] = { + [TURBO_UNKNOWN] = "unknown", + [TURBO_UNAVAILABLE] = "unavailable", + [TURBO_DISABLED] = "available but hidden", + [TURBO_ENABLED] = "available and visible" +}; + +/* + * Determine the current state of Turbo and cache it for later. + * Turbo is a package level config so it does not need to be + * enabled on every core. + */ +int get_turbo_state(void) +{ + struct cpuid_result cpuid_regs; + int turbo_en, turbo_cap; + msr_t msr; + + /* Return cached state if available */ + if (turbo_state != TURBO_UNKNOWN) + return turbo_state; + + cpuid_regs = cpuid(CPUID_LEAF_PM); + turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); + + msr = rdmsr(MSR_IA32_MISC_ENABLES); + turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); + + if (!turbo_cap && turbo_en) { + /* Unavailable */ + turbo_state = TURBO_UNAVAILABLE; + } else if (!turbo_cap && !turbo_en) { + /* Available but disabled */ + turbo_state = TURBO_DISABLED; + } else if (turbo_cap && turbo_en) { + /* Available */ + turbo_state = TURBO_ENABLED; + } + + printk(BIOS_INFO, "Turbo is %s\n", turbo_state_desc[turbo_state]); + return turbo_state; +} + +/* + * Try to enable Turbo mode. + */ +void enable_turbo(void) +{ + msr_t msr; + + /* Only possible if turbo is available but hidden */ + if (get_turbo_state() == TURBO_DISABLED) { + /* Clear Turbo Disable bit in Misc Enables */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.hi &= ~H_MISC_DISABLE_TURBO; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Update cached turbo state */ + turbo_state = TURBO_ENABLED; + printk(BIOS_INFO, "Turbo has been enabled\n"); + } +} diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h new file mode 100644 index 0000000..b60c8cf --- /dev/null +++ b/src/include/cpu/intel/turbo.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CPU_INTEL_TURBO_H +#define _CPU_INTEL_TURBO_H + +#define CPUID_LEAF_PM 6 +#define PM_CAP_TURBO_MODE (1 << 1) + +#define MSR_IA32_MISC_ENABLES 0x1a0 +#define H_MISC_DISABLE_TURBO (1 << 6) + +enum { + TURBO_UNKNOWN, + TURBO_UNAVAILABLE, + TURBO_DISABLED, + TURBO_ENABLED, +}; + +/* Return current turbo state */ +int get_turbo_state(void); + +/* Enable turbo */ +void enable_turbo(void); + +#endif

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Patch set updated for coreboot: 5ba6dbc Add support to run SMM handler in TSEG instead of ASEG
by Stefan Reinauer April 3, 2012

April 3, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/842 -gerrit commit 5ba6dbcb1df71478d561a3e12f29a840ae53cbd1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:24:04 2012 -0700 Add support to run SMM handler in TSEG instead of ASEG Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It limits the possible size of the SMM handler (and the number of CPUs supported in a system) - It's not considered a supported path anymore in newer CPUs. Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Acked-by: Stefan Reinauer <reinauer(a)google.com> --- Makefile.inc | 5 + src/console/vtxprintf.c | 6 + src/cpu/x86/smm/Makefile.inc | 14 ++- src/cpu/x86/smm/smihandler.c | 17 ++- src/cpu/x86/smm/smm_tseg.ld | 58 +++++++ src/cpu/x86/smm/smmhandler.S | 3 - src/cpu/x86/smm/smmhandler_tseg.S | 300 +++++++++++++++++++++++++++++++++++++ src/cpu/x86/smm/smmrelocate.S | 57 +++++++ src/include/cpu/x86/smm.h | 1 - 9 files changed, 448 insertions(+), 13 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 857ad16..92d0749 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -62,6 +62,11 @@ endif smm-c-ccopts:=-D__SMM__ smm-S-ccopts:=-D__SMM__ +# SMM TSEG base is dynamic +ifeq ($(CONFIG_SMM_TSEG),y) +smm-c-ccopts += -fpic +endif + ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 4053023..a370e5f 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -6,6 +6,7 @@ #include <string.h> #include <div64.h> +#include <console/console.h> #include <console/vtxprintf.h> /* haha, don't need ctype.c */ @@ -115,6 +116,11 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args int count; +#if defined(__SMM__) && CONFIG_SMM_TSEG + /* Fix pointer in TSEG */ + tx_byte = console_tx_byte; +#endif + for (count=0; *fmt ; ++fmt) { if (*fmt != '%') { tx_byte(*fmt), count++; diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 85bb454..108f8f9 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -22,15 +22,25 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm_wrap endif +# Use TSEG specific entry point and linker script +ifeq ($(CONFIG_SMM_TSEG),y) +smm-y += smmhandler_tseg.S +SMM_LDFLAGS := $(LDFLAGS) -pie +SMM_LDSCRIPT := smm_tseg.ld +else smm-y += smmhandler.S +SMM_LDFLAGS := $(LDFLAGFS) +SMM_LDSCRIPT := smm.ld +endif + smm-y += smihandler.c smm-y += smiutil.c $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ -$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld $(obj)/ldoptions - $(CC) $(LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o +$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/ldoptions + $(CC) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o $(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map $(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index a6ab87f..a971d81 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -25,10 +25,11 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> +#if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */ typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; /* SMI multiprocessing semaphore */ -static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED; +static volatile smi_semaphore smi_handler_status = SMI_UNLOCKED; static int smi_obtain_lock(void) { @@ -46,7 +47,7 @@ static int smi_obtain_lock(void) return (ret == SMI_UNLOCKED); } -void smi_release_lock(void) +static void smi_release_lock(void) { asm volatile ( "movb %1, %%al\n" @@ -56,6 +57,7 @@ void smi_release_lock(void) : "eax" ); } +#endif #define LAPIC_ID 0xfee00020 static inline __attribute__((always_inline)) unsigned long nodeid(void) @@ -116,18 +118,16 @@ void smi_handler(u32 smm_revision) unsigned int node; smm_state_save_area_t state_save; +#if !CONFIG_SMM_TSEG /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { /* For security reasons we don't release the other CPUs * until the CPU with the lock is actually done */ - while (smi_handler_status == SMI_LOCKED) { - asm volatile ( - ".byte 0xf3, 0x90\n" /* hint a CPU we are in spinlock (PAUSE instruction, REP NOP) */ - ); - } + while (smi_handler_status == SMI_LOCKED) /* wait */ ; return; } +#endif smi_backup_pci_address(); @@ -145,6 +145,7 @@ void smi_handler(u32 smm_revision) (0xa8000 + 0x7e00 - (node * 0x400)); break; case 0x00030100: + case 0x00030101: /* SandyBridge */ state_save.type = EM64T; state_save.em64t_state_save = (em64t_smm_state_save_area_t *) (0xa8000 + 0x7d00 - (node * 0x400)); @@ -173,7 +174,9 @@ void smi_handler(u32 smm_revision) smi_restore_pci_address(); +#if !CONFIG_SMM_TSEG smi_release_lock(); +#endif /* De-assert SMI# signal to allow another SMI */ smi_set_eos(); diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld new file mode 100644 index 0000000..016b5a0 --- /dev/null +++ b/src/cpu/x86/smm/smm_tseg.ld @@ -0,0 +1,58 @@ +/* Maximum number of CPUs/cores */ +CPUS = 16; + +SECTIONS +{ + /* This is the actual SMM handler. + * + * We just put code, rodata, data and bss all in a row. + */ + .handler (.): { + /* Assembler stub */ + *(.handler) + + /* C code of the SMM handler */ + *(.text); + *(.text.*); + + /* C read-only data of the SMM handler */ + . = ALIGN(16); + *(.rodata) + *(.rodata.*) + *(.data.rel.ro.*) + + /* C read-write data of the SMM handler */ + . = ALIGN(4); + *(.data) + + /* C uninitialized data of the SMM handler */ + . = ALIGN(4); + *(.bss) + *(.sbss) + + /* What is this? */ + *(COMMON) + . = ALIGN(4); + } + + /* We are using the TSEG interleaved to stuff the SMM handlers + * for all CPU cores in there. The jump table redirects the execution + * to the actual SMM handler + */ + . = 0x8000 - (( CPUS - 1) * 0x400); + .jumptable : { + *(.jumptable) + } + + /* Data used in early SMM TSEG handler. */ + . = 0x8400; + .earlydata : { + *(.earlydata) + } + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 774088e..3dd0b14 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -89,9 +89,6 @@ smm_handler_start: .code32 1: - /* flush the cache after disabling it */ - wbinvd - /* Use flat data segment */ movw $0x10, %ax movw %ax, %ds diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S new file mode 100644 index 0000000..d3e4d21 --- /dev/null +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * +--------------------------------+ 0xffff + * | Save State Map Node 0 | + * | Save State Map Node 1 | + * | Save State Map Node 2 | + * | Save State Map Node 3 | + * | ... | + * +--------------------------------+ 0xf000 + * | | + * | | + * | EARLY DATA (lock, vectors) | + * +--------------------------------+ 0x8400 + * | SMM Entry Node 0 (+ stack) | + * +--------------------------------+ 0x8000 + * | SMM Entry Node 1 (+ stack) | + * | SMM Entry Node 2 (+ stack) | + * | SMM Entry Node 3 (+ stack) | + * | ... | + * +--------------------------------+ 0x7400 + * | | + * | SMM Handler | + * | | + * +--------------------------------+ TSEG + * + */ + +#define LAPIC_ID 0xfee00020 +#define SMM_STACK_SIZE (0x400 - 0x10) + +/* Values for the xchg lock */ +#define SMI_LOCKED 0 +#define SMI_UNLOCKED 1 + +#define __PRE_RAM__ +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#include <northbridge/intel/sandybridge/sandybridge.h> +#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#else +#error "Northbridge must define TSEG_BAR." +#endif + +/* initially SMM is some sort of real mode. Let gcc know + * how to treat the SMM handler stub + */ + +.section ".handler", "a", @progbits + +.code16 + +/** + * SMM code to enable protected mode and jump to the + * C-written function void smi_handler(u32 smm_revision) + * + * All the bad magic is not all that bad after all. + */ +smm_handler_start: + movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ + addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */ + andl $~1, %edx /* Remove lock bit */ + + /* Obtain lock */ + movl %edx, %ebx + addl $(smm_lock), %ebx + movw $SMI_LOCKED, %ax + addr32 xchg %ax, (%ebx) + cmpw $SMI_UNLOCKED, %ax + + /* Proceed if we got the lock */ + je smm_check_prot_vector + + /* If we did not get the lock, wait for release */ +wait_for_unlock: + addr32 movw (%ebx), %ax + cmpw $SMI_LOCKED, %ax + je wait_for_unlock + rsm + +smm_check_prot_vector: + /* See if we need to adjust protected vector */ + movl %edx, %eax + addl $(smm_prot_vector), %eax + addr32 movl (%eax), %ebx + cmpl $(smm_prot_start), %ebx + jne smm_check_gdt_vector + + /* Adjust vector with TSEG offset */ + addl %edx, %ebx + addr32 movl %ebx, (%eax) + +smm_check_gdt_vector: + /* See if we need to adjust GDT vector */ + movl %edx, %eax + addl $(smm_gdt_vector + 2), %eax + addr32 movl (%eax), %ebx + cmpl $(smm_gdt - smm_handler_start), %ebx + jne smm_load_gdt + + /* Adjust vector with TSEG offset */ + addl %edx, %ebx + addr32 movl %ebx, (%eax) + +smm_load_gdt: + movl $(smm_gdt_vector), %ebx + addl %edx, %ebx /* TSEG base in %edx */ + data32 lgdt (%ebx) + + movl %cr0, %eax + andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x1, %eax /* PE = 1 */ + movl %eax, %cr0 + + /* Enable protected mode */ + movl $(smm_prot_vector), %eax + addl %edx, %eax + data32 ljmp *(%eax) + +.code32 +smm_prot_start: + /* Use flat data segment */ + movw $0x10, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* Get this CPU's LAPIC ID */ + movl $LAPIC_ID, %esi + movl (%esi), %ecx + shr $24, %ecx + + /* calculate stack offset by multiplying the APIC ID + * by 1024 (0x400), and save that offset in ebp. + */ + shl $10, %ecx + movl %ecx, %ebp + + /* We put the stack for each core right above + * its SMM entry point. Core 0 starts at SMM_BASE + 0x8000, + * we spare 0x10 bytes for the jump to be sure. + */ + movl $0x8010, %eax /* core 0 address */ + addl %edx, %eax /* addjust for TSEG */ + subl %ecx, %eax /* subtract offset, see above */ + movl %eax, %ebx /* Save bottom of stack in ebx */ + + /* clear stack */ + cld + movl %eax, %edi + movl $(SMM_STACK_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + + /* set new stack */ + addl $SMM_STACK_SIZE, %ebx + movl %ebx, %esp + + /* Get SMM revision */ + movl $0xfefc, %ebx /* core 0 address */ + addl %edx, %ebx /* addjust for TSEG */ + subl %ebp, %ebx /* subtract core X offset */ + movl (%ebx), %eax + pushl %eax + + /* Call 32bit C handler */ + call smi_handler + + /* Release lock */ + movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ + movl (%eax), %ebx /* Save TSEG_BAR in %ebx */ + andl $~1, %ebx /* Remove lock bit */ + addl $(smm_lock), %ebx + movw $SMI_UNLOCKED, %ax + xchg %ax, (%ebx) + + /* To return, just do rsm. It will "clean up" protected mode */ + rsm + +smm_gdt: + /* The first GDT entry can not be used. Keep it zero */ + .long 0x00000000, 0x00000000 + + /* gdt selector 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ + + /* gdt selector 0x10, flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + +smm_gdt_end: + +.section ".earlydata", "a", @progbits + +.code16 + +.align 4, 0xff + +smm_lock: + .word SMI_UNLOCKED + +.align 4, 0xff + +smm_prot_vector: + .long smm_prot_start + .short 8 + +.align 4, 0xff + +smm_gdt_vector: + .word smm_gdt_end - smm_gdt - 1 + .long smm_gdt - smm_handler_start + +.section ".jumptable", "a", @progbits + +/* This is the SMM jump table. All cores use the same SMM handler + * for simplicity. But SMM Entry needs to be different due to the + * save state area. The jump table makes sure all CPUs jump into the + * real handler on SMM entry. + */ + +/* This code currently supports up to 4 CPU cores. If more than 16 CPU cores + * shall be used, below table has to be updated, as well as smm_tseg.ld + */ + +/* When using TSEG do a relative jump and fix up the CS later since we + * do not know what our TSEG base is yet. + */ + +.code16 +jumptable: + /* core 15 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 14 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 13 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 12 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 11 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 10 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 9 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 8 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 7 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 6 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 5 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 4 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 3 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 2 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 1 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 0 */ + jmp smm_handler_start +.align 1024, 0x00 diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 7b38348..93786a0 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -35,10 +35,24 @@ #include "../../../southbridge/intel/i82801dx/i82801dx.h" #elif CONFIG_SOUTHBRIDGE_INTEL_SCH #include "../../../southbridge/intel/sch/sch.h" +#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 +#include "../../../southbridge/intel/bd82x6x/pch.h" #else #error "Southbridge needs SMM handler support." #endif +#if CONFIG_SMM_TSEG + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#include <northbridge/intel/sandybridge/sandybridge.h> +#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#else +#error "Northbridge must define TSEG_BAR." +#endif +#include <cpu/x86/mtrr.h> + +#endif /* CONFIG_SMM_TSEG */ + #define LAPIC_ID 0xfee00020 .global smm_relocation_start @@ -100,6 +114,7 @@ smm_relocation_start: /* Check revision to see if AMD64 style SMM_BASE * Intel Core Solo/Duo: 0x30007 * Intel Core2 Solo/Duo: 0x30100 + * Intel SandyBridge: 0x30101 * AMD64: 0x3XX64 * This check does not make much sense, unless someone ports * SMI handling to AMD64 CPUs. @@ -127,11 +142,53 @@ smm_relocate: movl %ecx, %edx shl $10, %edx +#if CONFIG_SMM_TSEG + movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + andl $~1, %eax /* Remove lock bit */ +#else movl $0xa0000, %eax +#endif subl %edx, %eax /* subtract offset, see above */ addr32 movl %eax, (%ebx) +#if CONFIG_SMM_TSEG + /* Check for SMRR capability in MTRRCAP[11] */ + movl $MTRRcap_MSR, %ecx + rdmsr + bt $11, %eax + jnc skip_smrr + + /* TSEG base */ + movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + andl $~1, %eax /* Remove lock bit */ + movl %eax, %ebx + + /* Set SMRR base address. */ + movl $SMRRphysBase_MSR, %ecx + orl $MTRR_TYPE_WRBACK, %eax + xorl %edx, %edx + wrmsr + + /* Set SMRR mask. */ + movl $SMRRphysMask_MSR, %ecx + movl $(~(CONFIG_SMM_TSEG_SIZE - 1) | MTRRphysMaskValid), %eax + xorl %edx, %edx + wrmsr + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE + /* + * IED base is top 4M of TSEG + */ + addl $(CONFIG_SMM_TSEG_SIZE - IED_SIZE), %ebx + movl $(0x30000 + 0x8000 + 0x7eec), %eax + addr32 movl %ebx, (%eax) +#endif + +skip_smrr: +#endif /* The next section of code is potentially southbridge specific */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index c314c39..dee9a70 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -280,6 +280,5 @@ void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_ void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); int __attribute__((weak)) mainboard_apm_cnt(u8 data); -void smi_release_lock(void); #endif

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Patch set updated for coreboot: 3c99fb3 smbios: add support for onboard devices extended information
by Stefan Reinauer April 3, 2012

April 3, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/843 -gerrit commit 3c99fb3150ed394534cb989f4a641c2f029715cb Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:30:10 2012 -0700 smbios: add support for onboard devices extended information Add support for type 41 smbios tables (to be used by board specific smbios handlers) Change-Id: Id6af5e4b1f5c5c78c63759d24fdc7cf8537ae5e6 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/smbios.h | 29 +++++++++++++++++++++++++++++ 1 files changed, 29 insertions(+), 0 deletions(-) diff --git a/src/include/smbios.h b/src/include/smbios.h index f13d621..1210f0f 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -32,6 +32,7 @@ typedef enum { SMBIOS_MEMORY_DEVICE=17, SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS=19, SMBIOS_SYSTEM_BOOT_INFORMATION=32, + SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION=41, SMBIOS_END_OF_TABLE=127, } smbios_struct_type_t; @@ -187,6 +188,34 @@ struct smbios_type32 { u8 eos[2]; } __attribute__((packed)); +typedef enum { + SMBIOS_DEVICE_TYPE_OTHER = 0x01, + SMBIOS_DEVICE_TYPE_UNKNOWN, + SMBIOS_DEVICE_TYPE_VIDEO, + SMBIOS_DEVICE_TYPE_SCSI, + SMBIOS_DEVICE_TYPE_ETHERNET, + SMBIOS_DEVICE_TYPE_TOKEN_RING, + SMBIOS_DEVICE_TYPE_SOUND, + SMBIOS_DEVICE_TYPE_PATA, + SMBIOS_DEVICE_TYPE_SATA, + SMBIOS_DEVICE_TYPE_SAS, +} smbios_onboard_device_type; + +struct smbios_type41 { + u8 type; + u8 length; + u16 handle; + u8 reference_designation; + u8 device_type: 7; + u8 device_status: 1; + u8 device_type_instance; + u16 segment_group_number; + u8 bus_number; + u8 function_number: 3; + u8 device_number: 5; + char eos[2]; +} __attribute__((packed)); + struct smbios_type127 { u8 type; u8 length;

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New patch to review for coreboot: 84e18ba smbios: add support for onboard devices extended information
by Stefan Reinauer April 2, 2012

April 2, 2012

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/843 -gerrit commit 84e18baf842af103996365d501bc8e7f81154718 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:30:10 2012 -0700 smbios: add support for onboard devices extended information Add support for type 41 smbios tables (to be used by board specific smbios handlers) Change-Id: Id6af5e4b1f5c5c78c63759d24fdc7cf8537ae5e6 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/smbios.h | 29 +++++++++++++++++++++++++++++ 1 files changed, 29 insertions(+), 0 deletions(-) diff --git a/src/include/smbios.h b/src/include/smbios.h index f13d621..1210f0f 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -32,6 +32,7 @@ typedef enum { SMBIOS_MEMORY_DEVICE=17, SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS=19, SMBIOS_SYSTEM_BOOT_INFORMATION=32, + SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION=41, SMBIOS_END_OF_TABLE=127, } smbios_struct_type_t; @@ -187,6 +188,34 @@ struct smbios_type32 { u8 eos[2]; } __attribute__((packed)); +typedef enum { + SMBIOS_DEVICE_TYPE_OTHER = 0x01, + SMBIOS_DEVICE_TYPE_UNKNOWN, + SMBIOS_DEVICE_TYPE_VIDEO, + SMBIOS_DEVICE_TYPE_SCSI, + SMBIOS_DEVICE_TYPE_ETHERNET, + SMBIOS_DEVICE_TYPE_TOKEN_RING, + SMBIOS_DEVICE_TYPE_SOUND, + SMBIOS_DEVICE_TYPE_PATA, + SMBIOS_DEVICE_TYPE_SATA, + SMBIOS_DEVICE_TYPE_SAS, +} smbios_onboard_device_type; + +struct smbios_type41 { + u8 type; + u8 length; + u16 handle; + u8 reference_designation; + u8 device_type: 7; + u8 device_status: 1; + u8 device_type_instance; + u16 segment_group_number; + u8 bus_number; + u8 function_number: 3; + u8 device_number: 5; + char eos[2]; +} __attribute__((packed)); + struct smbios_type127 { u8 type; u8 length;

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