coreboot April 2012

coreboot@coreboot.org

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New patch to review for coreboot: 5cdbc2b libpayload: avoid excessive casts in printf.c
by Mathias Krause 03 Apr '12

03 Apr '12

Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/850 -gerrit commit 5cdbc2b9e1985c6943638011d0d77f02833878cb Author: Mathias Krause <minipli(a)googlemail.com> Date: Tue Apr 3 21:02:33 2012 +0200 libpayload: avoid excessive casts in printf.c struct printf_spec is a purely internal structure. Avoid excessive casts when using the write function pointer just to make the compiler happy by using the right types in the first place. Change-Id: Ia4f3c79a5283cb76c8aa5f9d1eee758676303382 Signed-off-by: Mathias Krause <minipli(a)googlemail.com> --- payloads/libpayload/libc/printf.c | 20 +++++++++----------- 1 files changed, 9 insertions(+), 11 deletions(-) diff --git a/payloads/libpayload/libc/printf.c b/payloads/libpayload/libc/printf.c index c9a6cca..ccb64fd 100644 --- a/payloads/libpayload/libc/printf.c +++ b/payloads/libpayload/libc/printf.c @@ -46,7 +46,7 @@ FILE *stderr = &_stderr; /** Structure for specifying output methods for different printf clones. */ struct printf_spec { /* Output function, returns count of printed characters or EOF. */ - int (*write) (void *, size_t, void *); + int (*write) (const char *, size_t, void *); /* Support data - output stream specification, its state, locks, ... */ void *data; }; @@ -99,7 +99,7 @@ static const char digits_big[] = "0123456789ABCDEF"; static int printf_putnchars(const char *buf, size_t count, struct printf_spec *ps) { - return ps->write((void *)buf, count, ps->data); + return ps->write(buf, count, ps->data); } /** @@ -123,9 +123,9 @@ static inline int printf_putstr(const char *str, struct printf_spec *ps) */ static int printf_putchar(int c, struct printf_spec *ps) { - unsigned char ch = c; + char ch = c; - return ps->write((void *)&ch, 1, ps->data); + return ps->write(&ch, 1, ps->data); } /** @@ -752,13 +752,13 @@ struct vsnprintf_data { * * @param str Source string to print. * @param count Size of source string. - * @param data Structure with destination string, counter of used space + * @param _data Structure with destination string, counter of used space * and total string size. * @return Number of characters to print (not characters really printed!). */ -static int vsnprintf_write(const char *str, size_t count, - struct vsnprintf_data *data) +static int vsnprintf_write(const char *str, size_t count, void *_data) { + struct vsnprintf_data *data = _data; size_t i; i = data->size - data->len; @@ -798,8 +798,7 @@ static int vsnprintf_write(const char *str, size_t count, int vsnprintf(char *str, size_t size, const char *fmt, va_list ap) { struct vsnprintf_data data = { size, 0, str }; - struct printf_spec ps = - { (int (*)(void *, size_t, void *))vsnprintf_write, &data }; + struct printf_spec ps = { vsnprintf_write, &data }; /* Print 0 at end of string - fix case that nothing will be printed. */ if (size > 0) @@ -838,8 +837,7 @@ static int vprintf_write(const char *str, size_t count, void *unused) int vprintf(const char *fmt, va_list ap) { - struct printf_spec ps = - { (int (*)(void *, size_t, void *))vprintf_write, NULL }; + struct printf_spec ps = { vprintf_write, NULL }; return printf_core(fmt, &ps, ap); }

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New patch to review for coreboot: 82eb56b libpayload: minor cleanups
by Mathias Krause 03 Apr '12

03 Apr '12

Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/849 -gerrit commit 82eb56b102aa2294961bb65a244b537d521b9d12 Author: Mathias Krause <minipli(a)googlemail.com> Date: Tue Apr 3 20:42:01 2012 +0200 libpayload: minor cleanups Apply some const correctness to const/non-const strings in libc and libpci (what an ugly cast that was). Remove duplicated NULL test in printf_putstr(), already done in print_string() - reduces size of libpayload by a few bytes. Change-Id: I13f479df13e39d79cab291e9d99d153e1ef43eae Signed-off-by: Mathias Krause <minipli(a)googlemail.com> --- payloads/libpayload/libc/printf.c | 19 +++++-------------- payloads/libpayload/libpci/libpci.c | 2 +- 2 files changed, 6 insertions(+), 15 deletions(-) diff --git a/payloads/libpayload/libc/printf.c b/payloads/libpayload/libc/printf.c index e3cf8bb..c9a6cca 100644 --- a/payloads/libpayload/libc/printf.c +++ b/payloads/libpayload/libc/printf.c @@ -85,8 +85,8 @@ typedef enum { PrintfQualifierPointer, } qualifier_t; -static char digits_small[] = "0123456789abcdef"; -static char digits_big[] = "0123456789ABCDEF"; +static const char digits_small[] = "0123456789abcdef"; +static const char digits_big[] = "0123456789ABCDEF"; /** * Print one or more characters without adding newline. @@ -109,18 +109,9 @@ static int printf_putnchars(const char *buf, size_t count, * @param ps Write function specification and support data. * @return Number of characters printed. */ -static int printf_putstr(const char *str, struct printf_spec *ps) +static inline int printf_putstr(const char *str, struct printf_spec *ps) { - size_t count; - - if (str == NULL) { - const char *nullstr = "(NULL)"; - return printf_putnchars(nullstr, strlen(nullstr), ps); - } - - count = strlen(str); - - return ps->write((void *)str, count, ps->data); + return printf_putnchars(str, strlen(str), ps); } /** @@ -228,7 +219,7 @@ static int print_string(char *s, int width, unsigned int precision, static int print_number(uint64_t num, int width, int precision, int base, uint64_t flags, struct printf_spec *ps) { - char *digits = digits_small; + const char *digits = digits_small; char d[PRINT_NUMBER_BUFFER_SIZE]; char *ptr = &d[PRINT_NUMBER_BUFFER_SIZE - 1]; int size = 0; /* Size of number with all prefixes and signs. */ diff --git a/payloads/libpayload/libpci/libpci.c b/payloads/libpayload/libpci/libpci.c index ecc2b25..e9df10c 100644 --- a/payloads/libpayload/libpci/libpci.c +++ b/payloads/libpayload/libpci/libpci.c @@ -96,7 +96,7 @@ void pci_filter_init(struct pci_access* pacc, struct pci_filter* pf) pf->device = -1; } -static char *invalid_pci_device_string = (char *)"invalid pci device string"; +static char invalid_pci_device_string[] = "invalid pci device string"; /* parse domain:bus:dev.func (with all components but "dev" optional) * into filter.

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Patch merged into coreboot/master: 2292346 Add support for Intel Turbo Boost feature
by gerrit＠coreboot.org 03 Apr '12

03 Apr '12

the following patch was just integrated into master: commit 22923466739d22c9ca74ee00fc882a321975e155 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:35:09 2012 -0700 Add support for Intel Turbo Boost feature From wikipedia: Intel Turbo Boost is a technology implemented by Intel in certain versions of their Nehalem- and Sandy Bridge-based CPUs, including Core i5 and Core i7 that enables the processor to run above its base operating frequency via dynamic control of the CPU's "clock rate". It is activated when the operating system requests the highest performance state of the processor. Change-Id: I166ead7c219083006c2b05859eb18749c6fbe832 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Tue Apr 3 19:33:34 2012, giving +1 See http://review.coreboot.org/844 for details. -gerrit

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Patch set updated for coreboot: 89b0a39 Don't unconditionally show ChromeOS options
by Stefan Reinauer 03 Apr '12

03 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/848 -gerrit commit 89b0a39450aa1e4d7d91f2bad7d2802833789e55 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Apr 3 11:22:15 2012 -0700 Don't unconditionally show ChromeOS options Google ChromeOS specific options were shown in the main menu unconditionally, even on non-ChromeOS devices. Instead, hide these options unless CONFIG_CHROMEOS is set, and also put them in a separate menu. Change-Id: I75f533ed5046d6df4f7d959a0ca4c2441340ef2f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/vendorcode/google/chromeos/Kconfig | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 207431d..179bbb1 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -26,6 +26,9 @@ config CHROMEOS the coreboot table. NOTE: Enabling this option on an unsupported board will most likely break your build. +menu "ChromeOS" + depends on CHROMEOS + config VBNV_OFFSET hex default 0x26 @@ -53,3 +56,5 @@ config CHROMEOS_RAMOOPS_RAM_SIZE hex "Size of preserved RAM" default 0x00100000 depends on CHROMEOS_RAMOOPS + +endmenu

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New patch to review for coreboot: 68e2755 Don't unconditionally show ChromeOS options
by Stefan Reinauer 03 Apr '12

03 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/848 -gerrit commit 68e275572a3242d611c306a501a9bf22f974c424 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Apr 3 11:22:15 2012 -0700 Don't unconditionally show ChromeOS options Google ChromeOS specific options were shown in the main menu unconditionally, even on non-ChromeOS devices. Instead, hide these options unless CONFIG_CHROMEOS is set, and also put them in a separate menu. Change-Id: I75f533ed5046d6df4f7d959a0ca4c2441340ef2f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/vendorcode/google/chromeos/Kconfig | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 207431d..14cb333 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -26,6 +26,9 @@ config CHROMEOS the coreboot table. NOTE: Enabling this option on an unsupported board will most likely break your build. +menu "ChromeOS" + depends on ChromeOS + config VBNV_OFFSET hex default 0x26 @@ -53,3 +56,5 @@ config CHROMEOS_RAMOOPS_RAM_SIZE hex "Size of preserved RAM" default 0x00100000 depends on CHROMEOS_RAMOOPS + +endmenu

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Patch merged into coreboot/master: 1e9896c smbios: add support for onboard devices extended information
by gerrit＠coreboot.org 03 Apr '12

03 Apr '12

the following patch was just integrated into master: commit 1e9896c3036bb228c15e7e9654864bd982291254 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:30:10 2012 -0700 smbios: add support for onboard devices extended information Add support for type 41 smbios tables (to be used by board specific smbios handlers) Change-Id: Id6af5e4b1f5c5c78c63759d24fdc7cf8537ae5e6 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Apr 3 19:35:26 2012, giving +2 See http://review.coreboot.org/843 for details. -gerrit

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Patch set updated for coreboot: 2292346 Add support for Intel Turbo Boost feature
by Stefan Reinauer 03 Apr '12

03 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/844 -gerrit commit 22923466739d22c9ca74ee00fc882a321975e155 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:35:09 2012 -0700 Add support for Intel Turbo Boost feature From wikipedia: Intel Turbo Boost is a technology implemented by Intel in certain versions of their Nehalem- and Sandy Bridge-based CPUs, including Core i5 and Core i7 that enables the processor to run above its base operating frequency via dynamic control of the CPU's "clock rate". It is activated when the operating system requests the highest performance state of the processor. Change-Id: I166ead7c219083006c2b05859eb18749c6fbe832 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/turbo/Makefile.inc | 1 + src/cpu/intel/turbo/turbo.c | 90 ++++++++++++++++++++++++++++++++++++++ src/include/cpu/intel/turbo.h | 44 ++++++++++++++++++ 3 files changed, 135 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/turbo/Makefile.inc b/src/cpu/intel/turbo/Makefile.inc new file mode 100644 index 0000000..48ec55d --- /dev/null +++ b/src/cpu/intel/turbo/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += turbo.c diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c new file mode 100644 index 0000000..779550e --- /dev/null +++ b/src/cpu/intel/turbo/turbo.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> +#include <arch/cpu.h> + +static int turbo_state = TURBO_UNKNOWN; + +static const char *turbo_state_desc[] = { + [TURBO_UNKNOWN] = "unknown", + [TURBO_UNAVAILABLE] = "unavailable", + [TURBO_DISABLED] = "available but hidden", + [TURBO_ENABLED] = "available and visible" +}; + +/* + * Determine the current state of Turbo and cache it for later. + * Turbo is a package level config so it does not need to be + * enabled on every core. + */ +int get_turbo_state(void) +{ + struct cpuid_result cpuid_regs; + int turbo_en, turbo_cap; + msr_t msr; + + /* Return cached state if available */ + if (turbo_state != TURBO_UNKNOWN) + return turbo_state; + + cpuid_regs = cpuid(CPUID_LEAF_PM); + turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); + + msr = rdmsr(MSR_IA32_MISC_ENABLES); + turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); + + if (!turbo_cap && turbo_en) { + /* Unavailable */ + turbo_state = TURBO_UNAVAILABLE; + } else if (!turbo_cap && !turbo_en) { + /* Available but disabled */ + turbo_state = TURBO_DISABLED; + } else if (turbo_cap && turbo_en) { + /* Available */ + turbo_state = TURBO_ENABLED; + } + + printk(BIOS_INFO, "Turbo is %s\n", turbo_state_desc[turbo_state]); + return turbo_state; +} + +/* + * Try to enable Turbo mode. + */ +void enable_turbo(void) +{ + msr_t msr; + + /* Only possible if turbo is available but hidden */ + if (get_turbo_state() == TURBO_DISABLED) { + /* Clear Turbo Disable bit in Misc Enables */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.hi &= ~H_MISC_DISABLE_TURBO; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Update cached turbo state */ + turbo_state = TURBO_ENABLED; + printk(BIOS_INFO, "Turbo has been enabled\n"); + } +} diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h new file mode 100644 index 0000000..b60c8cf --- /dev/null +++ b/src/include/cpu/intel/turbo.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CPU_INTEL_TURBO_H +#define _CPU_INTEL_TURBO_H + +#define CPUID_LEAF_PM 6 +#define PM_CAP_TURBO_MODE (1 << 1) + +#define MSR_IA32_MISC_ENABLES 0x1a0 +#define H_MISC_DISABLE_TURBO (1 << 6) + +enum { + TURBO_UNKNOWN, + TURBO_UNAVAILABLE, + TURBO_DISABLED, + TURBO_ENABLED, +}; + +/* Return current turbo state */ +int get_turbo_state(void); + +/* Enable turbo */ +void enable_turbo(void); + +#endif

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Patch set updated for coreboot: 1e9896c smbios: add support for onboard devices extended information
by Stefan Reinauer 03 Apr '12

03 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/843 -gerrit commit 1e9896c3036bb228c15e7e9654864bd982291254 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:30:10 2012 -0700 smbios: add support for onboard devices extended information Add support for type 41 smbios tables (to be used by board specific smbios handlers) Change-Id: Id6af5e4b1f5c5c78c63759d24fdc7cf8537ae5e6 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/smbios.h | 29 +++++++++++++++++++++++++++++ 1 files changed, 29 insertions(+), 0 deletions(-) diff --git a/src/include/smbios.h b/src/include/smbios.h index f13d621..1210f0f 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -32,6 +32,7 @@ typedef enum { SMBIOS_MEMORY_DEVICE=17, SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS=19, SMBIOS_SYSTEM_BOOT_INFORMATION=32, + SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION=41, SMBIOS_END_OF_TABLE=127, } smbios_struct_type_t; @@ -187,6 +188,34 @@ struct smbios_type32 { u8 eos[2]; } __attribute__((packed)); +typedef enum { + SMBIOS_DEVICE_TYPE_OTHER = 0x01, + SMBIOS_DEVICE_TYPE_UNKNOWN, + SMBIOS_DEVICE_TYPE_VIDEO, + SMBIOS_DEVICE_TYPE_SCSI, + SMBIOS_DEVICE_TYPE_ETHERNET, + SMBIOS_DEVICE_TYPE_TOKEN_RING, + SMBIOS_DEVICE_TYPE_SOUND, + SMBIOS_DEVICE_TYPE_PATA, + SMBIOS_DEVICE_TYPE_SATA, + SMBIOS_DEVICE_TYPE_SAS, +} smbios_onboard_device_type; + +struct smbios_type41 { + u8 type; + u8 length; + u16 handle; + u8 reference_designation; + u8 device_type: 7; + u8 device_status: 1; + u8 device_type_instance; + u16 segment_group_number; + u8 bus_number; + u8 function_number: 3; + u8 device_number: 5; + char eos[2]; +} __attribute__((packed)); + struct smbios_type127 { u8 type; u8 length;

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Patch set updated for coreboot: ea903fa Add support to run SMM handler in TSEG instead of ASEG
by Stefan Reinauer 03 Apr '12

03 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/842 -gerrit commit ea903fa902f708001fe1511162f754747b1f17a3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:24:04 2012 -0700 Add support to run SMM handler in TSEG instead of ASEG Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It limits the possible size of the SMM handler (and the number of CPUs supported in a system) - It's not considered a supported path anymore in newer CPUs. Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Acked-by: Stefan Reinauer <reinauer(a)google.com> --- Makefile.inc | 5 + src/console/vtxprintf.c | 6 + src/cpu/x86/smm/Makefile.inc | 14 ++- src/cpu/x86/smm/smihandler.c | 15 +- src/cpu/x86/smm/smm_tseg.ld | 58 +++++++ src/cpu/x86/smm/smmhandler.S | 3 - src/cpu/x86/smm/smmhandler_tseg.S | 300 +++++++++++++++++++++++++++++++++++++ src/cpu/x86/smm/smmrelocate.S | 57 +++++++ src/include/cpu/x86/smm.h | 2 + 9 files changed, 449 insertions(+), 11 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 81d40df..9b67496 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -62,6 +62,11 @@ endif smm-c-ccopts:=-D__SMM__ smm-S-ccopts:=-D__SMM__ +# SMM TSEG base is dynamic +ifeq ($(CONFIG_SMM_TSEG),y) +smm-c-ccopts += -fpic +endif + ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 4053023..a370e5f 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -6,6 +6,7 @@ #include <string.h> #include <div64.h> +#include <console/console.h> #include <console/vtxprintf.h> /* haha, don't need ctype.c */ @@ -115,6 +116,11 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args int count; +#if defined(__SMM__) && CONFIG_SMM_TSEG + /* Fix pointer in TSEG */ + tx_byte = console_tx_byte; +#endif + for (count=0; *fmt ; ++fmt) { if (*fmt != '%') { tx_byte(*fmt), count++; diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 85bb454..108f8f9 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -22,15 +22,25 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm_wrap endif +# Use TSEG specific entry point and linker script +ifeq ($(CONFIG_SMM_TSEG),y) +smm-y += smmhandler_tseg.S +SMM_LDFLAGS := $(LDFLAGS) -pie +SMM_LDSCRIPT := smm_tseg.ld +else smm-y += smmhandler.S +SMM_LDFLAGS := $(LDFLAGFS) +SMM_LDSCRIPT := smm.ld +endif + smm-y += smihandler.c smm-y += smiutil.c $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ -$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld $(obj)/ldoptions - $(CC) $(LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o +$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/ldoptions + $(CC) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o $(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map $(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index a6ab87f..5824f78 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -25,10 +25,11 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> +#if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */ typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; /* SMI multiprocessing semaphore */ -static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED; +static volatile smi_semaphore smi_handler_status = SMI_UNLOCKED; static int smi_obtain_lock(void) { @@ -56,6 +57,7 @@ void smi_release_lock(void) : "eax" ); } +#endif #define LAPIC_ID 0xfee00020 static inline __attribute__((always_inline)) unsigned long nodeid(void) @@ -116,18 +118,16 @@ void smi_handler(u32 smm_revision) unsigned int node; smm_state_save_area_t state_save; +#if !CONFIG_SMM_TSEG /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { /* For security reasons we don't release the other CPUs * until the CPU with the lock is actually done */ - while (smi_handler_status == SMI_LOCKED) { - asm volatile ( - ".byte 0xf3, 0x90\n" /* hint a CPU we are in spinlock (PAUSE instruction, REP NOP) */ - ); - } + while (smi_handler_status == SMI_LOCKED) /* wait */ ; return; } +#endif smi_backup_pci_address(); @@ -145,6 +145,7 @@ void smi_handler(u32 smm_revision) (0xa8000 + 0x7e00 - (node * 0x400)); break; case 0x00030100: + case 0x00030101: /* SandyBridge */ state_save.type = EM64T; state_save.em64t_state_save = (em64t_smm_state_save_area_t *) (0xa8000 + 0x7d00 - (node * 0x400)); @@ -173,7 +174,9 @@ void smi_handler(u32 smm_revision) smi_restore_pci_address(); +#if !CONFIG_SMM_TSEG smi_release_lock(); +#endif /* De-assert SMI# signal to allow another SMI */ smi_set_eos(); diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld new file mode 100644 index 0000000..016b5a0 --- /dev/null +++ b/src/cpu/x86/smm/smm_tseg.ld @@ -0,0 +1,58 @@ +/* Maximum number of CPUs/cores */ +CPUS = 16; + +SECTIONS +{ + /* This is the actual SMM handler. + * + * We just put code, rodata, data and bss all in a row. + */ + .handler (.): { + /* Assembler stub */ + *(.handler) + + /* C code of the SMM handler */ + *(.text); + *(.text.*); + + /* C read-only data of the SMM handler */ + . = ALIGN(16); + *(.rodata) + *(.rodata.*) + *(.data.rel.ro.*) + + /* C read-write data of the SMM handler */ + . = ALIGN(4); + *(.data) + + /* C uninitialized data of the SMM handler */ + . = ALIGN(4); + *(.bss) + *(.sbss) + + /* What is this? */ + *(COMMON) + . = ALIGN(4); + } + + /* We are using the TSEG interleaved to stuff the SMM handlers + * for all CPU cores in there. The jump table redirects the execution + * to the actual SMM handler + */ + . = 0x8000 - (( CPUS - 1) * 0x400); + .jumptable : { + *(.jumptable) + } + + /* Data used in early SMM TSEG handler. */ + . = 0x8400; + .earlydata : { + *(.earlydata) + } + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 774088e..3dd0b14 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -89,9 +89,6 @@ smm_handler_start: .code32 1: - /* flush the cache after disabling it */ - wbinvd - /* Use flat data segment */ movw $0x10, %ax movw %ax, %ds diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S new file mode 100644 index 0000000..d3e4d21 --- /dev/null +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * +--------------------------------+ 0xffff + * | Save State Map Node 0 | + * | Save State Map Node 1 | + * | Save State Map Node 2 | + * | Save State Map Node 3 | + * | ... | + * +--------------------------------+ 0xf000 + * | | + * | | + * | EARLY DATA (lock, vectors) | + * +--------------------------------+ 0x8400 + * | SMM Entry Node 0 (+ stack) | + * +--------------------------------+ 0x8000 + * | SMM Entry Node 1 (+ stack) | + * | SMM Entry Node 2 (+ stack) | + * | SMM Entry Node 3 (+ stack) | + * | ... | + * +--------------------------------+ 0x7400 + * | | + * | SMM Handler | + * | | + * +--------------------------------+ TSEG + * + */ + +#define LAPIC_ID 0xfee00020 +#define SMM_STACK_SIZE (0x400 - 0x10) + +/* Values for the xchg lock */ +#define SMI_LOCKED 0 +#define SMI_UNLOCKED 1 + +#define __PRE_RAM__ +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#include <northbridge/intel/sandybridge/sandybridge.h> +#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#else +#error "Northbridge must define TSEG_BAR." +#endif + +/* initially SMM is some sort of real mode. Let gcc know + * how to treat the SMM handler stub + */ + +.section ".handler", "a", @progbits + +.code16 + +/** + * SMM code to enable protected mode and jump to the + * C-written function void smi_handler(u32 smm_revision) + * + * All the bad magic is not all that bad after all. + */ +smm_handler_start: + movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ + addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */ + andl $~1, %edx /* Remove lock bit */ + + /* Obtain lock */ + movl %edx, %ebx + addl $(smm_lock), %ebx + movw $SMI_LOCKED, %ax + addr32 xchg %ax, (%ebx) + cmpw $SMI_UNLOCKED, %ax + + /* Proceed if we got the lock */ + je smm_check_prot_vector + + /* If we did not get the lock, wait for release */ +wait_for_unlock: + addr32 movw (%ebx), %ax + cmpw $SMI_LOCKED, %ax + je wait_for_unlock + rsm + +smm_check_prot_vector: + /* See if we need to adjust protected vector */ + movl %edx, %eax + addl $(smm_prot_vector), %eax + addr32 movl (%eax), %ebx + cmpl $(smm_prot_start), %ebx + jne smm_check_gdt_vector + + /* Adjust vector with TSEG offset */ + addl %edx, %ebx + addr32 movl %ebx, (%eax) + +smm_check_gdt_vector: + /* See if we need to adjust GDT vector */ + movl %edx, %eax + addl $(smm_gdt_vector + 2), %eax + addr32 movl (%eax), %ebx + cmpl $(smm_gdt - smm_handler_start), %ebx + jne smm_load_gdt + + /* Adjust vector with TSEG offset */ + addl %edx, %ebx + addr32 movl %ebx, (%eax) + +smm_load_gdt: + movl $(smm_gdt_vector), %ebx + addl %edx, %ebx /* TSEG base in %edx */ + data32 lgdt (%ebx) + + movl %cr0, %eax + andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x1, %eax /* PE = 1 */ + movl %eax, %cr0 + + /* Enable protected mode */ + movl $(smm_prot_vector), %eax + addl %edx, %eax + data32 ljmp *(%eax) + +.code32 +smm_prot_start: + /* Use flat data segment */ + movw $0x10, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* Get this CPU's LAPIC ID */ + movl $LAPIC_ID, %esi + movl (%esi), %ecx + shr $24, %ecx + + /* calculate stack offset by multiplying the APIC ID + * by 1024 (0x400), and save that offset in ebp. + */ + shl $10, %ecx + movl %ecx, %ebp + + /* We put the stack for each core right above + * its SMM entry point. Core 0 starts at SMM_BASE + 0x8000, + * we spare 0x10 bytes for the jump to be sure. + */ + movl $0x8010, %eax /* core 0 address */ + addl %edx, %eax /* addjust for TSEG */ + subl %ecx, %eax /* subtract offset, see above */ + movl %eax, %ebx /* Save bottom of stack in ebx */ + + /* clear stack */ + cld + movl %eax, %edi + movl $(SMM_STACK_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + + /* set new stack */ + addl $SMM_STACK_SIZE, %ebx + movl %ebx, %esp + + /* Get SMM revision */ + movl $0xfefc, %ebx /* core 0 address */ + addl %edx, %ebx /* addjust for TSEG */ + subl %ebp, %ebx /* subtract core X offset */ + movl (%ebx), %eax + pushl %eax + + /* Call 32bit C handler */ + call smi_handler + + /* Release lock */ + movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ + movl (%eax), %ebx /* Save TSEG_BAR in %ebx */ + andl $~1, %ebx /* Remove lock bit */ + addl $(smm_lock), %ebx + movw $SMI_UNLOCKED, %ax + xchg %ax, (%ebx) + + /* To return, just do rsm. It will "clean up" protected mode */ + rsm + +smm_gdt: + /* The first GDT entry can not be used. Keep it zero */ + .long 0x00000000, 0x00000000 + + /* gdt selector 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ + + /* gdt selector 0x10, flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + +smm_gdt_end: + +.section ".earlydata", "a", @progbits + +.code16 + +.align 4, 0xff + +smm_lock: + .word SMI_UNLOCKED + +.align 4, 0xff + +smm_prot_vector: + .long smm_prot_start + .short 8 + +.align 4, 0xff + +smm_gdt_vector: + .word smm_gdt_end - smm_gdt - 1 + .long smm_gdt - smm_handler_start + +.section ".jumptable", "a", @progbits + +/* This is the SMM jump table. All cores use the same SMM handler + * for simplicity. But SMM Entry needs to be different due to the + * save state area. The jump table makes sure all CPUs jump into the + * real handler on SMM entry. + */ + +/* This code currently supports up to 4 CPU cores. If more than 16 CPU cores + * shall be used, below table has to be updated, as well as smm_tseg.ld + */ + +/* When using TSEG do a relative jump and fix up the CS later since we + * do not know what our TSEG base is yet. + */ + +.code16 +jumptable: + /* core 15 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 14 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 13 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 12 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 11 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 10 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 9 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 8 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 7 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 6 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 5 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 4 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 3 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 2 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 1 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 0 */ + jmp smm_handler_start +.align 1024, 0x00 diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 7b38348..93786a0 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -35,10 +35,24 @@ #include "../../../southbridge/intel/i82801dx/i82801dx.h" #elif CONFIG_SOUTHBRIDGE_INTEL_SCH #include "../../../southbridge/intel/sch/sch.h" +#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 +#include "../../../southbridge/intel/bd82x6x/pch.h" #else #error "Southbridge needs SMM handler support." #endif +#if CONFIG_SMM_TSEG + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#include <northbridge/intel/sandybridge/sandybridge.h> +#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#else +#error "Northbridge must define TSEG_BAR." +#endif +#include <cpu/x86/mtrr.h> + +#endif /* CONFIG_SMM_TSEG */ + #define LAPIC_ID 0xfee00020 .global smm_relocation_start @@ -100,6 +114,7 @@ smm_relocation_start: /* Check revision to see if AMD64 style SMM_BASE * Intel Core Solo/Duo: 0x30007 * Intel Core2 Solo/Duo: 0x30100 + * Intel SandyBridge: 0x30101 * AMD64: 0x3XX64 * This check does not make much sense, unless someone ports * SMI handling to AMD64 CPUs. @@ -127,11 +142,53 @@ smm_relocate: movl %ecx, %edx shl $10, %edx +#if CONFIG_SMM_TSEG + movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + andl $~1, %eax /* Remove lock bit */ +#else movl $0xa0000, %eax +#endif subl %edx, %eax /* subtract offset, see above */ addr32 movl %eax, (%ebx) +#if CONFIG_SMM_TSEG + /* Check for SMRR capability in MTRRCAP[11] */ + movl $MTRRcap_MSR, %ecx + rdmsr + bt $11, %eax + jnc skip_smrr + + /* TSEG base */ + movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + andl $~1, %eax /* Remove lock bit */ + movl %eax, %ebx + + /* Set SMRR base address. */ + movl $SMRRphysBase_MSR, %ecx + orl $MTRR_TYPE_WRBACK, %eax + xorl %edx, %edx + wrmsr + + /* Set SMRR mask. */ + movl $SMRRphysMask_MSR, %ecx + movl $(~(CONFIG_SMM_TSEG_SIZE - 1) | MTRRphysMaskValid), %eax + xorl %edx, %edx + wrmsr + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE + /* + * IED base is top 4M of TSEG + */ + addl $(CONFIG_SMM_TSEG_SIZE - IED_SIZE), %ebx + movl $(0x30000 + 0x8000 + 0x7eec), %eax + addr32 movl %ebx, (%eax) +#endif + +skip_smrr: +#endif /* The next section of code is potentially southbridge specific */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index c314c39..60959f5 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -280,6 +280,8 @@ void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_ void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); int __attribute__((weak)) mainboard_apm_cnt(u8 data); +#if !CONFIG_SMM_TSEG void smi_release_lock(void); +#endif #endif

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Patch merged into coreboot/master: 14bade0 nvramtool: 64bit safe CBFS handling
by gerrit＠coreboot.org 03 Apr '12

03 Apr '12

the following patch was just integrated into master: commit 14bade0c228f1ccedca95a39a22d24486cadd16b Author: Patrick Georgi <Patrick.Georgi(a)secunet.com> Date: Fri Mar 9 12:54:03 2012 +0100 nvramtool: 64bit safe CBFS handling Change-Id: I4f23ee04cd6479e55e9467af1b0196936412deb1 Signed-off-by: Patrick Georgi <Patrick.Georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Apr 3 16:29:50 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Apr 3 18:33:45 2012, giving +2 See http://review.coreboot.org/846 for details. -gerrit

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coreboot April 2012