coreboot April 2012

coreboot@coreboot.org

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459 discussions

Patch merged into coreboot/master: c5d7b59 Drop duplicate inclusion of src/vendorcode
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit c5d7b59f41b0e12b5b27c6351fbf12b3126d9006 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:31:14 2012 +0200 Drop duplicate inclusion of src/vendorcode Change-Id: I95908bdca51c5ee959ae9f2307d4b6e0e002d04a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/857 for details. -gerrit

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Re: [coreboot] GSoC project ideas
by Paul Geraedts 03 Apr '12

03 Apr '12

On Tue Mar 13 05:21:11 CET 2012, Peter Stuge wrote: >> we could easily attach a fast (66+ MHz) SPI flash chip to it. > > The OLS as SPI master mux for having an easy way to flash a real chip > used by a mainboard when booting is fine. But the chip should be able > to reside on the mainboard, and the OLS should drive the mainboard > reset while flashing. Having the OLS connect via wires means that the > SPI flash can not be driven quite so fast. The shorter wires the > better. The OLS is a big board with exposed contacts on the bottom. I much prefer a separate wire-connected development board. Signals of ~30MHz over ~30cm cable should not pose a real problem I think and it enables a much cleaner hardware setup. Not sure if asserting the reset signal of an embedded controller will always be sufficient to make its SPI bus tri-state. Possibly, but not strictly neccesary on such a non-shared bus. The underdefined or even nonexistent documentation in combination with dedicated ISP pins on them make me not too confident about it. Anyhow, these reset signals are often not easily accessible. During most part of the coreboot porting I do not intend to touch the internal SPI flash anyway, not even reading it. I will just deactivate it with its hold_n signal and use one of two external flash chips instead. When I eventually do want to touch the internal flash I will first write some embedded controller bootstrap code that makes it go into a tri-state, interrupt-masked, in-chip loop if it detects a specific (externally applied) SPI signal state at startup. If possible I will prefer using existing functionality here. More generally, my plan is to focus on 3 separate use cases, lets denote them as: users, hackers and developers. No physical hardware access should be necessary for users, only reliable flashrom access. Hackers may want physical hardware access. Easy access by means of something like a SOP test clip and mini-PCIe card, preferably without even soldering an SPI and LPC pin header. Developers / automatic test setups may want full physical hardware access. Nevertheless, I prefer to avoid invasive hardware access as much as possible. (I would go as far as applying a computer-controlled power socket in combination with a mechanical finger: much more elegant. : ) > The OLS is not a good fit for installation into e.g. a laptop. This > is one of the use cases for a QiProg; it's intended to be soldered > into the target system, on top of, or very near, the flash chip. Can you please post a reference to this QiProg device? I would like to read more about it and Google does not seem to know it. > I don't know that LPC is usually available, but even so it is a nice > start, and VHDL already exists. Although not part of the official standard, many non-WWAN mini-PCIe slots carry the 7 mandatory LPC signals instead of the official 7 UIM signals. I have added the typical signal mapping below. Unfortunately, the SERIRQ signal is not part of the 7 mandatory LPC signals. It may be available on a separate LPC pin header. Regards, Paul mini-PCIe pin | offical signal | LPC signal 08 | UIM_PWR | LFRAME# 10 | UIM_DATA | LAD3 12 | UIM_CLK | LAD2 14 | UIM_RESET | LAD1 16 | UIM_VPP | LAD0 17 | UIM_C8 | LRESET# 19 | UIM_C4 | LCLK

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Re: [coreboot] GSoC project ideas
by Paul Geraedts 03 Apr '12

03 Apr '12

On Sat Mar 10 21:27:41 CET 2012, Carl-Daniel Hailfinger wrote: > given the lack of affordable and available hardware tools for coreboot > development, I propose to look for a different set of projects this > year: Tools which would help developers, and which are usable especially > with current hardware. A list of ideas follows. > > - Flash ICE device with SPI support. > - Flash ICE device with LPC/FWH support. > - Serial emulation for LPC buses on a configurable I/O port with USB > output on the other side. > - Dual serial emulation for two LPC buses either on the same device or > with two identical devices and a fast bus in between. > - Serial emulation for PCI buses (i.e. PCI/serial card). Currently I am working towards items 1 and 3 of your list. Eventually I want to use this hardware to replace the flash content of my MSI Wind U100 netbook with free software (openec, coreboot, seabios, ipxe, grub2, etc). I want to keep my implementation sufficiently generic to allow for extensions like items 2, 4 and 5 of your list. > As a basis for all those ideas I'd propose the Openbench logic sniffer. > It has a fast FPGA, enough gates and roughly 32 kByte RAM. The FPGA is > fast enough and big enough to accommodate the necessary logic, and we > could easily attach a fast (66+ MHz) SPI flash chip to it. And with $50 > incl. shipping the OLS is not extremely cheap, but worth its price and > easily available. Fast flash chips are also available for reasonable prices. My hardware target is the Papilio platform in general [1]; basically the FPGA variant of the Arduino platform. All current Papilio implementations (to which I count the OLS) rely on UART over USB. Future boards are being developed that implement more high-speed USB access, e.g. the OLS successor Benchy [2]. I will try to make my VHDL cores so they will be compatible with both types of boards. I plan to start with UART over USB support for the currently available Papilio boards. Basically flashrom SPI access, POST code access and serial console access. This 'playground' should eventually give me enough insight in an optimal implementation when targeting future boards. At the moment I'm working towards a prototype of the hardware. When that is finished I will post the details as a constructive basis for feedback and comments. Regards, Paul [1] http://papilio.cc/ [2] http://www.gadgetfactory.net/gadgetforum/index.php?topic=427.0

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Re: [coreboot] Asus M5A88-v evo
by HighlyCaffeinated 03 Apr '12

03 Apr '12

>I bought an M5A88-v Motherboard ( >http://www.newegg.com/Product/Product.aspx?Item=N82E16813131733&Tpk=m5a88-v >) and an amd FX-4170 ( >http://www.newegg.com/Product/Product.aspx?Item=N82E16819106009 ) > >I use Fedora 16 on this machine. Compiled coreboot with a vga bios >from my board, flashed it, and in doing managed to brick the board. I >have another computer I was able to use to flash a vendor bios onto >the rom chip. Compiled again without video bios, and used a >pci-express graphics card. Still no luck. I'm running the machine with >stock firmware, but I'd love to be able to try out coreboot and >seabios. > >With Coreboot on it, The machine powered on and the fans spun up. >That's about it. No HD activity beyond power being applied. Ethernet >port never powered, screen never came out of power save. Seems to have >been bricked. > >Any ideas? > >Jonathan Bennett Jonathan- I'm very new to Coreboot myself, but high on the list of things to acquire I'd put a second flash chip and a serial crossover cable. I'm playing with one of the E350M1 boards with an 8-pin DIP SPI ROM onboard, and I have a laptop next to it running Windows. By running a header cable from the E350M1 to a serial Null Modem cable, then into a serial-to-USB adapter plugged into the Windows machine you can monitor the full progress of the Coreboot load. This makes it significantly easier to understand what is (or is not) happening during the boot process. Highly recommended. Before messing with the BIOS I got Linux up and running on the E350M1. Booting the board to the factory 4MB ROM allows me to build and flash the replacement 8MB ROM. The nice thing about using a ROM chip that is larger than factory is that flashrom -w verifies the coreboot.rom will fit on the chip so you don't accidentally try to flash the wrong ROM chip. It's saved me once already! Just a couple of pointers from someone in a similar situation. Mine boots now (yay!). One thing I have noticed - at least on my board - is that I cannot flash the ROM when I have booted from Coreboot. I MUST boot from the factory ROM to sucessfully flash the chip. I haven't yet looked into that, but plan to as time is available. Good luck -Todd

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Re: [coreboot] Asus M5A88-v evo
by Peter Stuge 03 Apr '12

03 Apr '12

Jonathan Bennett wrote: > cpuSetAMDMSR FIXME! CPU Version unknown or not supported! That's pretty clear. I suggest to boot with factory BIOS, check the exact parameters of the CPU, look at the code which is being run, and look for relevant documentation for your CPU in the scope of that code. If you are lucky you only need to add a few values from the documentation to tables in the code. //Peter

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Patch merged into coreboot/master: 8a57e1f Add support to run SMM handler in TSEG instead of ASEG
by gerrit＠coreboot.org 03 Apr '12

03 Apr '12

the following patch was just integrated into master: commit 8a57e1fab956b159a549e96274d550abce724d52 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:24:04 2012 -0700 Add support to run SMM handler in TSEG instead of ASEG Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It limits the possible size of the SMM handler (and the number of CPUs supported in a system) - It's not considered a supported path anymore in newer CPUs. Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Acked-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Apr 4 04:46:51 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Wed Apr 4 01:40:07 2012, giving +2 See http://review.coreboot.org/842 for details. -gerrit

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Patch set updated for coreboot: 8a57e1f Add support to run SMM handler in TSEG instead of ASEG
by Stefan Reinauer 03 Apr '12

03 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/842 -gerrit commit 8a57e1fab956b159a549e96274d550abce724d52 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 2 13:24:04 2012 -0700 Add support to run SMM handler in TSEG instead of ASEG Traditionally coreboot's SMM handler runs in ASEG (0xa0000), "behind" the graphics memory. This approach has two issues: - It limits the possible size of the SMM handler (and the number of CPUs supported in a system) - It's not considered a supported path anymore in newer CPUs. Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Acked-by: Stefan Reinauer <reinauer(a)google.com> --- Makefile.inc | 5 + src/console/vtxprintf.c | 6 + src/cpu/x86/smm/Makefile.inc | 14 ++- src/cpu/x86/smm/smihandler.c | 9 +- src/cpu/x86/smm/smm_tseg.ld | 58 +++++++ src/cpu/x86/smm/smmhandler_tseg.S | 300 +++++++++++++++++++++++++++++++++++++ src/cpu/x86/smm/smmrelocate.S | 49 ++++++ src/include/cpu/x86/smm.h | 2 + 8 files changed, 440 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 81d40df..9b67496 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -62,6 +62,11 @@ endif smm-c-ccopts:=-D__SMM__ smm-S-ccopts:=-D__SMM__ +# SMM TSEG base is dynamic +ifeq ($(CONFIG_SMM_TSEG),y) +smm-c-ccopts += -fpic +endif + ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 4053023..a370e5f 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -6,6 +6,7 @@ #include <string.h> #include <div64.h> +#include <console/console.h> #include <console/vtxprintf.h> /* haha, don't need ctype.c */ @@ -115,6 +116,11 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args int count; +#if defined(__SMM__) && CONFIG_SMM_TSEG + /* Fix pointer in TSEG */ + tx_byte = console_tx_byte; +#endif + for (count=0; *fmt ; ++fmt) { if (*fmt != '%') { tx_byte(*fmt), count++; diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 85bb454..108f8f9 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -22,15 +22,25 @@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm_wrap endif +# Use TSEG specific entry point and linker script +ifeq ($(CONFIG_SMM_TSEG),y) +smm-y += smmhandler_tseg.S +SMM_LDFLAGS := $(LDFLAGS) -pie +SMM_LDSCRIPT := smm_tseg.ld +else smm-y += smmhandler.S +SMM_LDFLAGS := $(LDFLAGFS) +SMM_LDSCRIPT := smm.ld +endif + smm-y += smihandler.c smm-y += smiutil.c $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(CC) $(LDFLAGS) -nostdlib -r -o $@ $^ -$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld $(obj)/ldoptions - $(CC) $(LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o +$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/ldoptions + $(CC) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o $(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map $(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index a6ab87f..bbed0f1 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -25,10 +25,11 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> +#if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */ typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; /* SMI multiprocessing semaphore */ -static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED; +static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4))) = SMI_UNLOCKED; static int smi_obtain_lock(void) { @@ -56,6 +57,7 @@ void smi_release_lock(void) : "eax" ); } +#endif #define LAPIC_ID 0xfee00020 static inline __attribute__((always_inline)) unsigned long nodeid(void) @@ -116,6 +118,7 @@ void smi_handler(u32 smm_revision) unsigned int node; smm_state_save_area_t state_save; +#if !CONFIG_SMM_TSEG /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { /* For security reasons we don't release the other CPUs @@ -128,6 +131,7 @@ void smi_handler(u32 smm_revision) } return; } +#endif smi_backup_pci_address(); @@ -145,6 +149,7 @@ void smi_handler(u32 smm_revision) (0xa8000 + 0x7e00 - (node * 0x400)); break; case 0x00030100: + case 0x00030101: /* SandyBridge */ state_save.type = EM64T; state_save.em64t_state_save = (em64t_smm_state_save_area_t *) (0xa8000 + 0x7d00 - (node * 0x400)); @@ -173,7 +178,9 @@ void smi_handler(u32 smm_revision) smi_restore_pci_address(); +#if !CONFIG_SMM_TSEG smi_release_lock(); +#endif /* De-assert SMI# signal to allow another SMI */ smi_set_eos(); diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld new file mode 100644 index 0000000..016b5a0 --- /dev/null +++ b/src/cpu/x86/smm/smm_tseg.ld @@ -0,0 +1,58 @@ +/* Maximum number of CPUs/cores */ +CPUS = 16; + +SECTIONS +{ + /* This is the actual SMM handler. + * + * We just put code, rodata, data and bss all in a row. + */ + .handler (.): { + /* Assembler stub */ + *(.handler) + + /* C code of the SMM handler */ + *(.text); + *(.text.*); + + /* C read-only data of the SMM handler */ + . = ALIGN(16); + *(.rodata) + *(.rodata.*) + *(.data.rel.ro.*) + + /* C read-write data of the SMM handler */ + . = ALIGN(4); + *(.data) + + /* C uninitialized data of the SMM handler */ + . = ALIGN(4); + *(.bss) + *(.sbss) + + /* What is this? */ + *(COMMON) + . = ALIGN(4); + } + + /* We are using the TSEG interleaved to stuff the SMM handlers + * for all CPU cores in there. The jump table redirects the execution + * to the actual SMM handler + */ + . = 0x8000 - (( CPUS - 1) * 0x400); + .jumptable : { + *(.jumptable) + } + + /* Data used in early SMM TSEG handler. */ + . = 0x8400; + .earlydata : { + *(.earlydata) + } + + /DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) + } +} diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S new file mode 100644 index 0000000..8fdd75f --- /dev/null +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -0,0 +1,300 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* + * +--------------------------------+ 0xffff + * | Save State Map Node 0 | + * | Save State Map Node 1 | + * | Save State Map Node 2 | + * | Save State Map Node 3 | + * | ... | + * +--------------------------------+ 0xf000 + * | | + * | | + * | EARLY DATA (lock, vectors) | + * +--------------------------------+ 0x8400 + * | SMM Entry Node 0 (+ stack) | + * +--------------------------------+ 0x8000 + * | SMM Entry Node 1 (+ stack) | + * | SMM Entry Node 2 (+ stack) | + * | SMM Entry Node 3 (+ stack) | + * | ... | + * +--------------------------------+ 0x7400 + * | | + * | SMM Handler | + * | | + * +--------------------------------+ TSEG + * + */ + +#define LAPIC_ID 0xfee00020 +#define SMM_STACK_SIZE (0x400 - 0x10) + +/* Values for the xchg lock */ +#define SMI_LOCKED 0 +#define SMI_UNLOCKED 1 + +#define __PRE_RAM__ +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE +#include <northbridge/intel/sandybridge/sandybridge.h> +#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#else +#error "Northbridge must define TSEG_BAR." +#endif + +/* initially SMM is some sort of real mode. Let gcc know + * how to treat the SMM handler stub + */ + +.section ".handler", "a", @progbits + +.code16 + +/** + * SMM code to enable protected mode and jump to the + * C-written function void smi_handler(u32 smm_revision) + * + * All the bad magic is not all that bad after all. + */ +smm_handler_start: + movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ + addr32 movl (%eax), %edx /* Save TSEG_BAR in %edx */ + andl $~1, %edx /* Remove lock bit */ + + /* Obtain lock */ + movl %edx, %ebx + addl $(smm_lock), %ebx + movw $SMI_LOCKED, %ax + addr32 xchg %ax, (%ebx) + cmpw $SMI_UNLOCKED, %ax + + /* Proceed if we got the lock */ + je smm_check_prot_vector + + /* If we did not get the lock, wait for release */ +wait_for_unlock: + addr32 movw (%ebx), %ax + cmpw $SMI_LOCKED, %ax + je wait_for_unlock + rsm + +smm_check_prot_vector: + /* See if we need to adjust protected vector */ + movl %edx, %eax + addl $(smm_prot_vector), %eax + addr32 movl (%eax), %ebx + cmpl $(smm_prot_start), %ebx + jne smm_check_gdt_vector + + /* Adjust vector with TSEG offset */ + addl %edx, %ebx + addr32 movl %ebx, (%eax) + +smm_check_gdt_vector: + /* See if we need to adjust GDT vector */ + movl %edx, %eax + addl $(smm_gdt_vector + 2), %eax + addr32 movl (%eax), %ebx + cmpl $(smm_gdt - smm_handler_start), %ebx + jne smm_load_gdt + + /* Adjust vector with TSEG offset */ + addl %edx, %ebx + addr32 movl %ebx, (%eax) + +smm_load_gdt: + movl $(smm_gdt_vector), %ebx + addl %edx, %ebx /* TSEG base in %edx */ + data32 lgdt (%ebx) + + movl %cr0, %eax + andl $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */ + orl $0x1, %eax /* PE = 1 */ + movl %eax, %cr0 + + /* Enable protected mode */ + movl $(smm_prot_vector), %eax + addl %edx, %eax + data32 ljmp *(%eax) + +.code32 +smm_prot_start: + /* Use flat data segment */ + movw $0x10, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* Get this CPU's LAPIC ID */ + movl $LAPIC_ID, %esi + movl (%esi), %ecx + shr $24, %ecx + + /* calculate stack offset by multiplying the APIC ID + * by 1024 (0x400), and save that offset in ebp. + */ + shl $10, %ecx + movl %ecx, %ebp + + /* We put the stack for each core right above + * its SMM entry point. Core 0 starts at SMM_BASE + 0x8000, + * we spare 0x10 bytes for the jump to be sure. + */ + movl $0x8010, %eax /* core 0 address */ + addl %edx, %eax /* addjust for TSEG */ + subl %ecx, %eax /* subtract offset, see above */ + movl %eax, %ebx /* Save bottom of stack in ebx */ + + /* clear stack */ + cld + movl %eax, %edi + movl $(SMM_STACK_SIZE >> 2), %ecx + xorl %eax, %eax + rep stosl + + /* set new stack */ + addl $SMM_STACK_SIZE, %ebx + movl %ebx, %esp + + /* Get SMM revision */ + movl $0xfefc, %ebx /* core 0 address */ + addl %edx, %ebx /* addjust for TSEG */ + subl %ebp, %ebx /* subtract core X offset */ + movl (%ebx), %eax + pushl %eax + + /* Call 32bit C handler */ + call smi_handler + + /* Release lock */ + movl $(TSEG_BAR), %eax /* Get TSEG base from PCIE */ + movl (%eax), %ebx /* Save TSEG_BAR in %ebx */ + andl $~1, %ebx /* Remove lock bit */ + addl $(smm_lock), %ebx + movw $SMI_UNLOCKED, %ax + xchg %ax, (%ebx) + + /* To return, just do rsm. It will "clean up" protected mode */ + rsm + +smm_gdt: + /* The first GDT entry can not be used. Keep it zero */ + .long 0x00000000, 0x00000000 + + /* gdt selector 0x08, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ + + /* gdt selector 0x10, flat data segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 + +smm_gdt_end: + +.section ".earlydata", "a", @progbits + +.code16 + +.align 4, 0xff + +smm_lock: + .word SMI_UNLOCKED + +.align 4, 0xff + +smm_prot_vector: + .long smm_prot_start + .short 8 + +.align 4, 0xff + +smm_gdt_vector: + .word smm_gdt_end - smm_gdt - 1 + .long smm_gdt - smm_handler_start + +.section ".jumptable", "a", @progbits + +/* This is the SMM jump table. All cores use the same SMM handler + * for simplicity. But SMM Entry needs to be different due to the + * save state area. The jump table makes sure all CPUs jump into the + * real handler on SMM entry. + */ + +/* This code currently supports up to 16 CPU cores. If more than 16 CPU cores + * shall be used, below table has to be updated, as well as smm_tseg.ld + */ + +/* When using TSEG do a relative jump and fix up the CS later since we + * do not know what our TSEG base is yet. + */ + +.code16 +jumptable: + /* core 15 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 14 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 13 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 12 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 11 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 10 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 9 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 8 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 7 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 6 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 5 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 4 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 3 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 2 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 1 */ + jmp smm_handler_start +.align 1024, 0x00 + /* core 0 */ + jmp smm_handler_start +.align 1024, 0x00 diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 7b38348..bc5b2da 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -39,6 +39,12 @@ #error "Southbridge needs SMM handler support." #endif +#if CONFIG_SMM_TSEG + +#include <cpu/x86/mtrr.h> + +#endif /* CONFIG_SMM_TSEG */ + #define LAPIC_ID 0xfee00020 .global smm_relocation_start @@ -100,6 +106,7 @@ smm_relocation_start: /* Check revision to see if AMD64 style SMM_BASE * Intel Core Solo/Duo: 0x30007 * Intel Core2 Solo/Duo: 0x30100 + * Intel SandyBridge: 0x30101 * AMD64: 0x3XX64 * This check does not make much sense, unless someone ports * SMI handling to AMD64 CPUs. @@ -127,11 +134,53 @@ smm_relocate: movl %ecx, %edx shl $10, %edx +#if CONFIG_SMM_TSEG + movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + andl $~1, %eax /* Remove lock bit */ +#else movl $0xa0000, %eax +#endif subl %edx, %eax /* subtract offset, see above */ addr32 movl %eax, (%ebx) +#if CONFIG_SMM_TSEG + /* Check for SMRR capability in MTRRCAP[11] */ + movl $MTRRcap_MSR, %ecx + rdmsr + bt $11, %eax + jnc skip_smrr + + /* TSEG base */ + movl $(TSEG_BAR), %ecx /* Get TSEG base from PCIE */ + addr32 movl (%ecx), %eax /* Save TSEG_BAR in %eax */ + andl $~1, %eax /* Remove lock bit */ + movl %eax, %ebx + + /* Set SMRR base address. */ + movl $SMRRphysBase_MSR, %ecx + orl $MTRR_TYPE_WRBACK, %eax + xorl %edx, %edx + wrmsr + + /* Set SMRR mask. */ + movl $SMRRphysMask_MSR, %ecx + movl $(~(CONFIG_SMM_TSEG_SIZE - 1) | MTRRphysMaskValid), %eax + xorl %edx, %edx + wrmsr + +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE + /* + * IED base is top 4M of TSEG + */ + addl $(CONFIG_SMM_TSEG_SIZE - IED_SIZE), %ebx + movl $(0x30000 + 0x8000 + 0x7eec), %eax + addr32 movl %ebx, (%eax) +#endif + +skip_smrr: +#endif /* The next section of code is potentially southbridge specific */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index c314c39..60959f5 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -280,6 +280,8 @@ void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_ void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); int __attribute__((weak)) mainboard_apm_cnt(u8 data); +#if !CONFIG_SMM_TSEG void smi_release_lock(void); +#endif #endif

1 0

Patch set updated for coreboot: 9bb029d Makefile: rename coreboot_ap linking filenames
by Kyösti Mälkki 03 Apr '12

03 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/840 -gerrit commit 9bb029d5839d4621649e361c420d40e29272a30f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 3 21:01:06 2012 +0300 Makefile: rename coreboot_ap linking filenames $(obj)/coreboot_ap -> $(objcbfs)/coreboot_ap.elf It is really a ramstage for AP CPU and not a romstage, it is not enabled for any mainboard by default, and it doesn't compile even if enabled. Change-Id: Ifb9c5cb6df65309660b000876cf6a9a3da9b6839 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 27 +++++++++------------------ 1 files changed, 9 insertions(+), 18 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8ab5fa8..b9b811f 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -47,7 +47,7 @@ ifeq ($(CONFIG_PAYLOAD_FILO),y) COREBOOT_ROM_DEPENDENCIES+=filo endif ifeq ($(CONFIG_AP_CODE_IN_CAR),y) -COREBOOT_ROM_DEPENDENCIES+=$(obj)/coreboot_ap +COREBOOT_ROM_DEPENDENCIES+=$(objcbfs)/coreboot_ap.elf endif ifeq ($(CONFIG_GEODE_VSA_FILE),y) COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_VSA_FILENAME) @@ -76,9 +76,9 @@ endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp - if [ -f $(obj)/coreboot_ap ]; \ + if [ -f $(objcbfs)/coreboot_ap.elf ]; \ then \ - $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ap $(CONFIG_CBFS_PREFIX)/coreboot_ap $(CBFS_COMPRESS_FLAG); \ + $(CBFSTOOL) $@.tmp add-stage $(objcbfs)/coreboot_ap.elf $(CONFIG_CBFS_PREFIX)/coreboot_ap $(CBFS_COMPRESS_FLAG); \ fi $(CBFSTOOL) $@.tmp add-stage $(objcbfs)/coreboot_ram.elf $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @@ -173,20 +173,15 @@ $(objsec)/coreboot_ram.a: $$(ramstage-objs) $(AR) cr $@ $^ ####################################################################### -# coreboot_ap.rom +# Ramstage for AP CPU (AMD K8, obsolete?) -ifeq ($(CONFIG_AP_CODE_IN_CAR),y) - -$(obj)/coreboot_ap: $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o +$(objcbfs)/coreboot_ap.debug: $(objsec)/ap_romstage.o $(src)/arch/x86/init/ldscript_apc.lb @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(src)/arch/x86/init/ldscript_apc.lb $^ - $(OBJCOPY) --only-keep-debug $@.tmp $@.debug - $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$@.debug $@.tmp - $(NM) -n $@.tmp | sort > $@.map - mv $@.tmp $@ + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/init/ldscript_apc.lb $< -endif +$(objsec)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ ####################################################################### # done @@ -223,10 +218,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/ $(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $< -o $@ else -$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ - $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@

1 0

Patch set updated for coreboot: 3f7b6dd Makefile: rename ramstage linking filenames
by Kyösti Mälkki 03 Apr '12

03 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/839 -gerrit commit 3f7b6ddaa8238dd806d378ebb77551620b441ae9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 3 20:39:51 2012 +0300 Makefile: rename ramstage linking filenames Move final build results under $(objcbfs). Move intermediate files under $(objsec). Change-Id: I0046f68938be81b8efa525aa50b39328ca02ecb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 23 +++++++++-------------- 1 files changed, 9 insertions(+), 14 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index db3fe0c..8ab5fa8 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -73,14 +73,14 @@ $(obj)/coreboot.pre1: $(CBFSTOOL) mv $(obj)/coreboot.rom $@ endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/coreboot_ram $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp if [ -f $(obj)/coreboot_ap ]; \ then \ $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ap $(CONFIG_CBFS_PREFIX)/coreboot_ap $(CBFS_COMPRESS_FLAG); \ fi - $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) + $(CBFSTOOL) $@.tmp add-stage $(objcbfs)/coreboot_ram.elf $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @printf " PAYLOAD \e[1;31mnone (as specified by user)\e[0m\n" endif @@ -159,23 +159,18 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug ####################################################################### # Build the coreboot_ram (stage 2) -$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld #ldoptions +$(objcbfs)/coreboot_ram.debug: $(objsec)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $(obj)/coreboot_ram.o - $(NM) -n $@.tmp | sort > $@.map - $(OBJCOPY) --only-keep-debug $@.tmp $@.debug - $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$@.debug $@.tmp - mv $@.tmp $@ + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $< -$(obj)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(obj)/coreboot.a $(LIBGCC_FILE_NAME) +$(objsec)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(objsec)/coreboot_ram.a $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(objsec)/coreboot_ram.a $(LIBGCC_FILE_NAME) -Wl,--end-group -$(obj)/coreboot.a: $$(ramstage-objs) +$(objsec)/coreboot_ram.a: $$(ramstage-objs) @printf " AR $(subst $(obj)/,,$(@))\n" - rm -f $(obj)/coreboot.a - $(AR) cr $(obj)/coreboot.a $^ + rm -f $@ + $(AR) cr $@ $^ ####################################################################### # coreboot_ap.rom

1 0

Patch set updated for coreboot: 5b6a904 Makefile: rename bootblock linking filenames
by Kyösti Mälkki 03 Apr '12

03 Apr '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/838 -gerrit commit 5b6a90434544d1acbf254c90ead7c0708ac81eeb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 3 20:21:51 2012 +0300 Makefile: rename bootblock linking filenames Move final build results under $(objcbfs). Move intermediate files under $(objsec). Replace $(obj)/mainboard/$(MAINBOARDDIR) with $(objsec). Change-Id: I0365304e1b0ed02a5a3ec720b0cf3e303eaefa7c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 39 ++++++++++++++------------------------- 1 files changed, 14 insertions(+), 25 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c5faf5b..db3fe0c 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -63,8 +63,8 @@ prebuild-files = \ $(call extract_nth,4,$(file)) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL) - $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock +$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) + $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(objcbfs)/bootblock.bin $(prebuild-files) true mv $@.tmp $@ else @@ -289,10 +289,6 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) ####################################################################### # Build the bootblock -$(obj)/coreboot.bootblock: $(obj)/bootblock.elf - @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - $(OBJCOPY) -O binary $< $@ - bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb bootblock_lds += $(src)/cpu/x86/16bit/entry16.lds bootblock_lds += $(src)/cpu/x86/16bit/reset16.lds @@ -309,7 +305,7 @@ bootblock_inc += $(chipset_bootblock_inc) ifeq ($(CONFIG_SSE),y) bootblock_inc += $(src)/cpu/x86/sse_enable.inc endif -bootblock_inc += $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc +bootblock_inc += $(objsec)/bootblock.inc bootblock_inc += $(src)/arch/x86/lib/walkcbfs.S bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ @@ -317,38 +313,31 @@ ifeq ($(CONFIG_SSE),y) bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ endif -$(obj)/bootblock/ldscript.ld: $$(bootblock_lds) $(obj)/ldoptions +$(objsec)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" - mkdir -p $(obj)/bootblock printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE "$(ldscript)"\n)' > $@ -$(obj)/bootblock/bootblock.S: $$(bootblock_inc) +$(objsec)/bootblock.S: $$(bootblock_inc) @printf " GEN $(subst $(obj)/,,$(@))\n" - mkdir -p $(obj)/bootblock printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s +$(objsec)/bootblock.o: $(objsec)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm + $(CC) -Wa,-acdlns -c -o $@ $< > $(basename $(a)).disasm -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S $(obj)/config.h $(obj)/build.h +$(objsec)/bootblock.s: $(objsec)/bootblock.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) +$(objsec)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" - $(CC) $(INCLUDES) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \ - $< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d + $(CC) $(INCLUDES) -MM -MT$(objsec)/bootblock.inc \ + $< > $(objsec)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ -$(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld +$(objcbfs)/bootblock.debug: $(objsec)/bootblock.o $(objsec)/bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(obj)/bootblock/ldscript.ld $< - $(NM) -n $@.tmp | sort > $(obj)/bootblock.map - $(OBJCOPY) --only-keep-debug $@.tmp $(obj)/bootblock.debug - $(OBJCOPY) --strip-debug $@.tmp - $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@.tmp - mv $@.tmp $@ + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objsec)/bootblock.ld $< ####################################################################### # Build the romstage

1 0

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coreboot April 2012