coreboot April 2012

coreboot@coreboot.org

39 participants
459 discussions

Re: [coreboot] Dual SPI Flash
by Oliver Schinagl 04 Apr '12

04 Apr '12

Well My electrical engineering knowledge does not reach as far that I would know where to connect what :) I can read a schematic and solder based on that, but those pictures from the wiki that I linked, http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash has a small PCB, with 2 flash chips on it, but I can't figure out where to connect what. I do think it's a great idea, and maybe it would be an idea to draw the PCB in kicad/geda or the like, and actually have small batches made. I know dangerousprototypes.com has loads of small PCB's made for a few bux. Having a few on hand of these, and be able to send them to people would be great! Stuff one in an envelope and mail it out for the price of a stamp. On 06-03-12 09:55, Peter Stuge wrote: > Oliver Schinagl wrote: >> Oh wow, that's some nice work there, unfortunatly I only have 1 bios >> socket on my motherboard(s) and would use have to 'stack' the bios >> chips. > It works fine if you keep the switch wires very short. > > Or you can build a transistor-based or IC-based switch circuit which > stays very close by, and then gets remote controlled by a switch on a > long cable. > > > //Peter

4 16

New patch to review for coreboot: c2e50ec Use fast memset in SMM mode, too
by Stefan Reinauer 04 Apr '12

04 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/827 -gerrit commit c2e50ece4dec0fbfdc714b171530a658b8d8d13a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 16:28:20 2012 -0700 Use fast memset in SMM mode, too ... and always include IP checksumming in romstage. It's generally useful and our upcoming port needs it. Change-Id: I248402d96a23e58354744e053b9d5cca6b74ad3a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/lib/Makefile.inc | 1 + src/lib/Makefile.inc | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 8f5fd5f..4375952 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += cbfs_and_run.c romstage-y += memset.c romstage-y += memcpy.c +smm-y += memset.c smm-y += memcpy.c $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8ce72b2..7c081ac 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -17,9 +17,10 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c -romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c +romstage-y += compute_ip_checksum.c +romstage-y += memmove.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) ramstage-y += memset.c @@ -51,10 +52,13 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c +ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) +smm-y += memset.c +endif ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) smm-y += memcpy.c endif -smm-y += cbfs.c memset.c memcmp.c +smm-y += cbfs.c memcmp.c smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c smm-$(CONFIG_USBDEBUG) += usbdebug.c

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Re: [coreboot] GSoC project ideas
by Svetoslav Trochev 04 Apr '12

04 Apr '12

Hi Paul, On Tue, Apr 3, 2012 at 11:19 PM, Paul Geraedts <p.f.j.geraedts(a)gmail.com> wrote: >> - Flash ICE device with SPI support. >> - Flash ICE device with LPC/FWH support. >> - Serial emulation for LPC buses on a configurable I/O port with USB >> output on the other side. >> - Dual serial emulation for two LPC buses either on the same device or >> with two identical devices and a fast bus in between. >> - Serial emulation for PCI buses (i.e. PCI/serial card). > > Currently I am working towards items 1 and 3 of your list. Eventually I > want to use this hardware to replace the flash content of my MSI Wind > U100 netbook with free software (openec, coreboot, seabios, ipxe, grub2, > etc). I want to keep my implementation sufficiently generic to allow for > extensions like items 2, 4 and 5 of your list. I am also interested in item 1. [1] But looks like you are far ahead of me. :) Currently I am waiting for my hardware to arrive. I ordered Open Workbench Logic Sniffer [2]. Do you think I can help you in your work? Best regards, Svetoslav [1] http://www.coreboot.org/pipermail/coreboot/2012-March/068993.html [2] http://www.seeedstudio.com/depot/open-workbench-logic-sniffer-p-612.html?cP…

1 0

Re: [coreboot] Asus M5A88-v evo
by Jonathan Bennett 04 Apr '12

04 Apr '12

I've done a bit of looking, and found the code in question. It looks like the code is trying to figure out what family10 proc it is. The only problem, it's running a bulldozer processor. cpuinfo lists it as a family 21. Are the fx family processors supported at all? ~Jonathan >That's pretty clear. I suggest to boot with factory BIOS, check the >exact parameters of the CPU, look at the code which is being run, and >look for relevant documentation for your CPU in the scope of that >code. >If you are lucky you only need to add a few values from the >documentation to tables in the code. >//Peter >On Tue, Apr 3, 2012 at 5:24 PM, Jonathan Bennett <jbscience87(a)gmail.com> wrote: >> On Tue, Mar 20, 2012 at 4:36 PM, Julian Shulika <hercares(a)gmail.com> wrote: >>> Could you please show log from serial,your board has com port. >> Finally got a couple spare flash chips and a way to capture the serial output. >> >> coreboot-4.0-2227-g4a2daf6 Tue Apr 3 15:29:40 CDT 2012 starting... >> >> BSP Family_Model: 00600f12 >> *sysinfo range: [000cc000,000cf360] >> bsp_apicid = 00 >> cpu_init_detectedx = 00000000 >> microcode: rev id not foung, Skipping microcode patch! >> POST: 0x33 >> cpuSetAMDMSR FIXME! CPU Version unknown or not supported! >> FIXME! CPU Version unknown or not supported! >> FIXME! CPU Version unknown or not supported! >> done >> POST: 0x34 >> Enter amd_ht_init()

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Patch merged into coreboot/master: c2e50ec Use fast memset in SMM mode, too
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit c2e50ece4dec0fbfdc714b171530a658b8d8d13a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Mar 30 16:28:20 2012 -0700 Use fast memset in SMM mode, too ... and always include IP checksumming in romstage. It's generally useful and our upcoming port needs it. Change-Id: I248402d96a23e58354744e053b9d5cca6b74ad3a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sat Mar 31 03:15:28 2012, giving +1 See http://review.coreboot.org/827 for details. -gerrit

1 0

New patch to review for coreboot: a18dc1a Update documentation in smmrelocate.S to mention TSEG
by Stefan Reinauer 04 Apr '12

04 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/861 -gerrit commit a18dc1a4fba4b2ceff70ce630fbe99979cf2863f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 10:38:05 2012 -0700 Update documentation in smmrelocate.S to mention TSEG Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/smm/smmrelocate.S | 19 +++++++++++-------- 1 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index bc5b2da..5a2dba5 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -54,13 +54,22 @@ .code16 /** - * This trampoline code relocates SMBASE to 0xa0000 - ( lapicid * 0x400 ) + * When starting up, x86 CPUs have their SMBASE set to 0x30000. However, + * this is not a good place for the SMM handler to live, so it needs to + * be relocated. + * Traditionally SMM handlers used to live in the A segment (0xa0000). + * With growing SMM handlers, more CPU cores, etc. CPU vendors started + * allowing to relocate the handler to the end of physical memory, which + * they refer to as TSEG. + * This trampoline code relocates SMBASE to base address - ( lapicid * 0x400 ) * * Why 0x400? It is a safe value to cover the save state area per CPU. On * current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel * Core 2 CPUs the _documented_ parts of the save state area is 48 bytes * bigger, effectively sizing our data structures 0x300 bytes. * + * Example (with SMM handler living at 0xa0000): + * * LAPICID SMBASE SMM Entry SAVE STATE * 0 0xa0000 0xa8000 0xafd00 * 1 0x9fc00 0xa7c00 0xaf900 @@ -88,13 +97,7 @@ * at 0xa8000-0xa8100 (example for core 0). That is not enough. * * This means we're basically limited to 16 cpu cores before - * we need to use the TSEG/HSEG for the actual SMM handler plus stack. - * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG. - * - * If we figure out the documented values above are safe to use, - * we could pack the structure above even more, so we could use the - * scheme to pack save state areas for 63 AMD CPUs or 58 Intel CPUs - * in the ASEG. + * we need to move the SMM handler to TSEG. * * Note: Some versions of Pentium M need their SMBASE aligned to 32k. * On those the above only works for up to 2 cores. But for now we only

1 0

Patch merged into coreboot/master: c276a74 Add support for Intel Panther Point PCH
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit c276a7462a7f1fdfb66ff7ba446c9c3138b0690f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:07:22 2012 +0200 Add support for Intel Panther Point PCH Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Apr 4 02:34:39 2012, giving +1 See http://review.coreboot.org/853 for details. -gerrit

1 0

Patch merged into coreboot/master: 460069f Add support for mainboard specific suspend/resume handler
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit 460069fb2ffab71a7e9dfd85a8a1020e74b47f07 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Apr 3 23:28:22 2012 +0200 Add support for mainboard specific suspend/resume handler Some mainboards (most likely laptops) will need mainboard specific functions called upon a resume from suspend. Change-Id: If1518a4b016bba776643adaef0ae64ff49f57e51 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Apr 4 00:31:23 2012, giving +1 See http://review.coreboot.org/852 for details. -gerrit

1 0

Patch merged into coreboot/master: d93b82f Move TPM code to romstage
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit d93b82ff774411f77f8d2760298cb75ffe3d0529 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:21:37 2012 +0200 Move TPM code to romstage We want to do TPM initialization as early as possible to keep the impact on boot time low. Therefore move it to romstage. Change-Id: I5f2e021e0b11bd70a78ad1f05ec09802d015dd9e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Apr 4 02:49:26 2012, giving +1 See http://review.coreboot.org/856 for details. -gerrit

1 0

Patch merged into coreboot/master: b11cee2 Drop verified boot code from acpi.c
by gerrit＠coreboot.org 04 Apr '12

04 Apr '12

the following patch was just integrated into master: commit b11cee23d99ffe5dcbfea2758bd1ee5cff19911b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Apr 3 18:53:48 2012 +0200 Drop verified boot code from acpi.c We changed our verified boot initialization to run from romstage, as that allows faster boot times and does not add as much ChromeOS specific code to generic files. Change-Id: Id4164c26d524ea0ffce34467cf91379a19a4b2f6 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/851 for details. -gerrit

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coreboot April 2012