coreboot April 2012

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459 discussions

New patch to review for coreboot: 06f59dd Fixes and Sandybridge support for lapic cpu init
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/871 -gerrit commit 06f59ddf04321026f9a6794f2eadba6cab3f4508 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:17:11 2012 -0700 Fixes and Sandybridge support for lapic cpu init - preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - skip some delays on Sandybridge systems - Count how long we're waiting for each AP to stop - Skip speedstep specific CPU entries Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/lapic/lapic_cpu_init.c | 13 ++++++++++--- 1 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ed9940c..61a0f87 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -14,6 +14,7 @@ #include <smp/atomic.h> #include <smp/spinlock.h> #include <cpu/cpu.h> +#include <cpu/intel/speedstep/chip.h> #if CONFIG_SMP == 1 /* This is a lot more paranoid now, since Linux can NOT handle @@ -108,7 +109,7 @@ static int lapic_start_cpu(unsigned long apicid) } return 0; } -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX && !CONFIG_CPU_INTEL_MODEL_206AX mdelay(10); #endif @@ -136,7 +137,7 @@ static int lapic_start_cpu(unsigned long apicid) start_eip = get_valid_start_eip((unsigned long)_secondary_start); -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX num_starts = 2; #else num_starts = 1; @@ -446,6 +447,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) { device_t cpu; int old_active_count, active_count; + long loopcount = 0; + /* Now loop until the other cpus have finished initializing */ old_active_count = 1; active_count = atomic_read(&active_cpus); @@ -456,17 +459,21 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } udelay(10); active_count = atomic_read(&active_cpus); + loopcount++; } for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } + if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { + continue; + } if (!cpu->initialized) { printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", cpu->path.apic.apic_id); } } - printk(BIOS_DEBUG, "All AP CPUs stopped\n"); + printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } #else /* CONFIG_SMP */

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New patch to review for coreboot: 1a50b63 Fix timer frequency detection on Sandybridge
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/870 -gerrit commit 1a50b63b220d62ad987e6c7882e8a83a8f3d680c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:11:02 2012 -0700 Fix timer frequency detection on Sandybridge Change-Id: Ide720bd91cde56a0afdd231d93500c371b1ffbe8 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/lapic/apic_timer.c | 48 ++++++++++++++++++++++++++++++---------- 1 files changed, 36 insertions(+), 12 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 826f5b6..bb6cca7 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <delay.h> +#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> @@ -27,14 +28,40 @@ * memory init. */ -#define FSB_CLOCK_STS 0xcd +static u32 timer_fsb = 0; -static u32 timer_fsb = 200; // default to 200MHz +static int set_timer_fsb(void) +{ + struct cpuinfo_x86 c; + int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; + int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 }; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return -1; + + switch (c.x86_model) { + case 0xe: /* Core Solo/Duo */ + case 0x1c: /* Atom */ + timer_fsb = core_fsb[rdmsr(0xcd).lo & 7]; + break; + case 0xf: /* Core 2*/ + case 0x17: /* Enhanced Core */ + timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; + break; + case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ + timer_fsb = 100; + break; + default: + timer_fsb = 200; + break; + } + + return 0; +} void init_timer(void) { - msr_t fsb_clock_sts; - /* Set the apic timer to no interrupts and periodic mode */ lapic_write(LAPIC_LVTT, (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)); @@ -45,19 +72,16 @@ void init_timer(void) lapic_write(LAPIC_TMICT, 0xffffffff); /* Set FSB frequency to a reasonable value */ - fsb_clock_sts = rdmsr(FSB_CLOCK_STS); - switch ((fsb_clock_sts.lo >> 4) & 0x07) { - case 0: timer_fsb = 266; break; - case 1: timer_fsb = 133; break; - case 2: timer_fsb = 200; break; - case 3: timer_fsb = 166; break; - case 5: timer_fsb = 100; break; - } + set_timer_fsb(); } void udelay(u32 usecs) { u32 start, value, ticks; + + if (!timer_fsb) + init_timer(); + /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */ ticks = usecs * timer_fsb; start = lapic_read(LAPIC_TMCCT);

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New patch to review for coreboot: c35c461 Invalidate cache before first jump
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/869 -gerrit commit c35c461bb2146ab949062f22e265406deef178d2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:09:46 2012 -0700 Invalidate cache before first jump Some CPUs (Sandybridge) seem to require this, and it does not hurt on other CPUs. Change-Id: I4fdb281b2b684ab5fea999aae28ca08dce24da4d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/16bit/reset16.inc | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/16bit/reset16.inc index 1be0e3a..8dba3c8 100644 --- a/src/cpu/x86/16bit/reset16.inc +++ b/src/cpu/x86/16bit/reset16.inc @@ -2,6 +2,7 @@ .code16 .globl reset_vector reset_vector: + wbinvd .byte 0xe9 .int _start - ( . + 2 ) /* Note: The above jump is hand coded to work around bugs in binutils.

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New patch to review for coreboot: 231c8fa Factor out function to find driver for a CPU
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/868 -gerrit commit 231c8fae7b5da973f70d9769e6076ea1885bc3e7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:07:56 2012 -0700 Factor out function to find driver for a CPU This function can be used outside of the normal CPU setup Change-Id: I810c63b8aff868a6f69d5b992bea1cfae5a5996b Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/lib/cpu.c | 18 +++++++++++------- 1 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index fac523f..98ede06 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -211,23 +211,27 @@ static void identify_cpu(struct device *cpu) } } -static void set_cpu_ops(struct device *cpu) +struct cpu_driver *find_cpu_driver(struct device *cpu) { struct cpu_driver *driver; - cpu->ops = 0; for (driver = cpu_drivers; driver < ecpu_drivers; driver++) { struct cpu_device_id *id; - for(id = driver->id_table; id->vendor != X86_VENDOR_INVALID; id++) { + for (id = driver->id_table; + id->vendor != X86_VENDOR_INVALID; id++) { if ((cpu->vendor == id->vendor) && (cpu->device == id->device)) { - goto found; + return driver; } } } - return; -found: - cpu->ops = driver->ops; + return NULL; +} + +static void set_cpu_ops(struct device *cpu) +{ + struct cpu_driver *driver = find_cpu_driver(cpu); + cpu->ops = driver ? driver->ops : NULL; } void cpu_initialize(void)

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New patch to review for coreboot: 6e6e012 smbios: Don't fill out firmware version on ChromeOS
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/867 -gerrit commit 6e6e0125ce79d04956ef818fcb247215aec04840 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:02:54 2012 -0700 smbios: Don't fill out firmware version on ChromeOS In ChromeOS we potentially have different payloads with different versions. Since the user land tools get information on which one of them is loaded, leave the string in smbios empty so we can fill it out in the payload. Also fill out system version number and serial number with some constant values. Change-Id: Id1fed5a54b511c730975fa83347452f1274b8504 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/boot/smbios.c | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 2bd00c4..f39bf04 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -29,6 +29,9 @@ #include <cpu/x86/name.h> #include <cbfs_core.h> #include <arch/byteorder.h> +#if CONFIG_CHROMEOS +#include <vendorcode/google/chromeos/gnvs.h> +#endif static u8 smbios_checksum(u8 *p, u32 length) { @@ -126,8 +129,18 @@ static int smbios_write_type0(unsigned long *current, int handle) t->length = len - 2; t->vendor = smbios_add_string(t->eos, "coreboot"); +#if !CONFIG_CHROMEOS t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE); t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION); +#else +#define SPACES \ + " " + t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE); + u32 version_offset = (u32)smbios_string_table_len(t->eos); + t->bios_version = smbios_add_string(t->eos, SPACES); + /* SMBIOS offsets start at 1 rather than 0 */ + vboot_data->vbt10 = (u32)t->eos + (version_offset - 1); +#endif if ((hdr = get_cbfs_header()) != (struct cbfs_header *)0xffffffff) t->bios_rom_size = (ntohl(hdr->romsize) / 65535) - 1; @@ -160,6 +173,8 @@ static int smbios_write_type1(unsigned long *current, int handle) t->length = len - 2; t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_PART_NUMBER); + t->serial_number = smbios_add_string(t->eos, "123456789"); + t->version = smbios_add_string(t->eos, "1.0"); len = t->length + smbios_string_table_len(t->eos); *current += len; return len;

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Patch set updated for coreboot: 5d5628a Update documentation in smmrelocate.S to mention TSEG
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/861 -gerrit commit 5d5628a869a1369bb9640ffc25384a3618373bac Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 10:38:05 2012 -0700 Update documentation in smmrelocate.S to mention TSEG Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/smm/smmrelocate.S | 19 +++++++++++-------- 1 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index bc5b2da..18d668c 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -54,13 +54,22 @@ .code16 /** - * This trampoline code relocates SMBASE to 0xa0000 - ( lapicid * 0x400 ) + * When starting up, x86 CPUs have their SMBASE set to 0x30000. However, + * this is not a good place for the SMM handler to live, so it needs to + * be relocated. + * Traditionally SMM handlers used to live in the A segment (0xa0000). + * With growing SMM handlers, more CPU cores, etc. CPU vendors started + * allowing to relocate the handler to the end of physical memory, which + * they refer to as TSEG. + * This trampoline code relocates SMBASE to base address - ( lapicid * 0x400 ) * * Why 0x400? It is a safe value to cover the save state area per CPU. On * current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel * Core 2 CPUs the _documented_ parts of the save state area is 48 bytes * bigger, effectively sizing our data structures 0x300 bytes. * + * Example (with SMM handler living at 0xa0000): + * * LAPICID SMBASE SMM Entry SAVE STATE * 0 0xa0000 0xa8000 0xafd00 * 1 0x9fc00 0xa7c00 0xaf900 @@ -88,13 +97,7 @@ * at 0xa8000-0xa8100 (example for core 0). That is not enough. * * This means we're basically limited to 16 cpu cores before - * we need to use the TSEG/HSEG for the actual SMM handler plus stack. - * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG. - * - * If we figure out the documented values above are safe to use, - * we could pack the structure above even more, so we could use the - * scheme to pack save state areas for 63 AMD CPUs or 58 Intel CPUs - * in the ASEG. + * we need to move the SMM handler to TSEG. * * Note: Some versions of Pentium M need their SMBASE aligned to 32k. * On those the above only works for up to 2 cores. But for now we only

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Patch merged into coreboot/master: 5cc6cb3 Add support for Intel Sandybridge CPU
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 5cc6cb3584fb6e662fcdf8a526ec2d289e248380 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:09:50 2012 +0200 Add support for Intel Sandybridge CPU Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Apr 4 02:01:17 2012, giving +1 See http://review.coreboot.org/855 for details. -gerrit

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Patch merged into coreboot/master: ff8097a Add support for Intel Sandybridge CPU (northbridge part)
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit ff8097ac89d47349ad72417959efcd8b47c70a69 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 00:08:51 2012 +0200 Add support for Intel Sandybridge CPU (northbridge part) Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Apr 4 02:17:33 2012, giving +1 See http://review.coreboot.org/854 for details. -gerrit

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Patch merged into coreboot/master: 4aeb1c8 Ignore .exe files in whitespace test
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 4aeb1c857b3819e115b39b67b1379fbd2c21892d Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 5 11:18:23 2012 +0200 Ignore .exe files in whitespace test On windows, we sometimes require getopt executables, which end up in the source tree. These shouldn't break the whitespace test. Change-Id: Iaf86e38b94605bebb69a317e00f932eefcf468b9 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See http://review.coreboot.org/863 for details. -gerrit

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Patch merged into coreboot/master: 5f92c27 Add getopt implementation to abuild
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 5f92c27db7619359919470fc43da1d5e1dd831f1 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Apr 5 11:17:01 2012 +0200 Add getopt implementation to abuild Similar to buildgcc, abuild requires getopt(1). Provide an implementation for platforms without it (Win32) Change-Id: I2ae4d84e06dd34135c97b18819da2b49a89706ce Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See http://review.coreboot.org/862 for details. -gerrit

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coreboot April 2012