coreboot April 2012

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Patch merged into coreboot/master: 5a596f7 Add constants for fast path resume copying
by gerrit＠coreboot.org 06 Apr '12

06 Apr '12

the following patch was just integrated into master: commit 5a596f7a8fb66d12c2888d8bb91ea883c2fceea0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:21:04 2012 -0700 Add constants for fast path resume copying cache as ram does not usually cache the ram before it is up. Hence, if romstage.c backs up resume memory, the involved memcpy is always uncached. This makes resume very slow. On Sandybridge we copy the memory later, after enabling caching, and that allows us to resume in as little as 250ms. Change-Id: I31a71ad4468679d39880cf9a8c4e497bb7addf8f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 6 00:28:19 2012, giving +1 See http://review.coreboot.org/872 for details. -gerrit

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Patch set updated for coreboot: ff29084 Fixes and Sandybridge support for lapic cpu init
by Stefan Reinauer 06 Apr '12

06 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/871 -gerrit commit ff290840a59fd26c3f4da4095344e0429d402866 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:17:11 2012 -0700 Fixes and Sandybridge support for lapic cpu init - preprocessor macros should not use defined(CONFIG_*) but just CONFIG_* - skip some delays on Sandybridge systems - Count how long we're waiting for each AP to stop - Skip speedstep specific CPU entries Change-Id: I13db384ba4e28acbe7f0f8c9cd169954b39f167d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/intel/speedstep/chip.h | 35 +++++++++++++++++++++++++++++++++++ src/cpu/x86/lapic/lapic_cpu_init.c | 13 ++++++++++--- 2 files changed, 45 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/speedstep/chip.h b/src/cpu/intel/speedstep/chip.h new file mode 100644 index 0000000..44f336a --- /dev/null +++ b/src/cpu/intel/speedstep/chip.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_intel_speedstep_ops; + +/* Magic value used to locate this chip in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + +struct cpu_intel_speedstep_config { + u8 pstate_coord_type; /* Processor Coordination Type */ + + int c1_battery; /* CPU C-state for ACPI C1 on Battery Power */ + int c2_battery; /* CPU C-state for ACPI C2 on Battery Power */ + int c3_battery; /* CPU C-state for ACPI C3 on Battery Power */ + + int c1_acpower; /* CPU C-state for ACPI C1 on AC Power */ + int c2_acpower; /* CPU C-state for ACPI C2 on AC Power */ + int c3_acpower; /* CPU C-state for ACPI C3 on AC Power */ +}; diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ed9940c..61a0f87 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -14,6 +14,7 @@ #include <smp/atomic.h> #include <smp/spinlock.h> #include <cpu/cpu.h> +#include <cpu/intel/speedstep/chip.h> #if CONFIG_SMP == 1 /* This is a lot more paranoid now, since Linux can NOT handle @@ -108,7 +109,7 @@ static int lapic_start_cpu(unsigned long apicid) } return 0; } -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX && !CONFIG_CPU_INTEL_MODEL_206AX mdelay(10); #endif @@ -136,7 +137,7 @@ static int lapic_start_cpu(unsigned long apicid) start_eip = get_valid_start_eip((unsigned long)_secondary_start); -#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) +#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_AMD_MODEL_14XXX num_starts = 2; #else num_starts = 1; @@ -446,6 +447,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) { device_t cpu; int old_active_count, active_count; + long loopcount = 0; + /* Now loop until the other cpus have finished initializing */ old_active_count = 1; active_count = atomic_read(&active_cpus); @@ -456,17 +459,21 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } udelay(10); active_count = atomic_read(&active_cpus); + loopcount++; } for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } + if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { + continue; + } if (!cpu->initialized) { printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", cpu->path.apic.apic_id); } } - printk(BIOS_DEBUG, "All AP CPUs stopped\n"); + printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } #else /* CONFIG_SMP */

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Patch set updated for coreboot: 2196604 Factor out function to find driver for a CPU
by Stefan Reinauer 06 Apr '12

06 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/868 -gerrit commit 21966043fe2519e1b48809a40bf407c7e653d094 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:07:56 2012 -0700 Factor out function to find driver for a CPU This function can be used outside of the normal CPU setup Change-Id: I810c63b8aff868a6f69d5b992bea1cfae5a5996b Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/cpu.h | 3 +++ src/arch/x86/lib/cpu.c | 18 +++++++++++------- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 891e62b..604abde 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -154,6 +154,9 @@ struct cpu_driver { struct cpu_device_id *id_table; }; +struct device; +struct cpu_driver *find_cpu_driver(struct device *cpu); + struct cpu_info { device_t cpu; unsigned long index; diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index fac523f..98ede06 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -211,23 +211,27 @@ static void identify_cpu(struct device *cpu) } } -static void set_cpu_ops(struct device *cpu) +struct cpu_driver *find_cpu_driver(struct device *cpu) { struct cpu_driver *driver; - cpu->ops = 0; for (driver = cpu_drivers; driver < ecpu_drivers; driver++) { struct cpu_device_id *id; - for(id = driver->id_table; id->vendor != X86_VENDOR_INVALID; id++) { + for (id = driver->id_table; + id->vendor != X86_VENDOR_INVALID; id++) { if ((cpu->vendor == id->vendor) && (cpu->device == id->device)) { - goto found; + return driver; } } } - return; -found: - cpu->ops = driver->ops; + return NULL; +} + +static void set_cpu_ops(struct device *cpu) +{ + struct cpu_driver *driver = find_cpu_driver(cpu); + cpu->ops = driver ? driver->ops : NULL; } void cpu_initialize(void)

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Patch merged into coreboot/master: 1a50b63 Fix timer frequency detection on Sandybridge
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 1a50b63b220d62ad987e6c7882e8a83a8f3d680c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:11:02 2012 -0700 Fix timer frequency detection on Sandybridge Change-Id: Ide720bd91cde56a0afdd231d93500c371b1ffbe8 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu Apr 5 23:31:19 2012, giving +1 See http://review.coreboot.org/870 for details. -gerrit

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Patch merged into coreboot/master: beca17b amdfam10: add phenom II as known cpu
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit beca17b9dc211fa2c8424083724c28c5f37d52bf Author: Bernhard Urban <lewurm(a)gmail.com> Date: Thu Apr 5 17:13:27 2012 +0200 amdfam10: add phenom II as known cpu Change-Id: I84a0f9e8e7a15c0aac8dc380de3ddf70b1decbd7 Signed-off-by: Bernhard Urban <lewurm(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Apr 5 17:28:37 2012, giving +1 See http://review.coreboot.org/864 for details. -gerrit

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Patch merged into coreboot/master: 6e6e012 smbios: Don't fill out firmware version on ChromeOS
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 6e6e0125ce79d04956ef818fcb247215aec04840 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:02:54 2012 -0700 smbios: Don't fill out firmware version on ChromeOS In ChromeOS we potentially have different payloads with different versions. Since the user land tools get information on which one of them is loaded, leave the string in smbios empty so we can fill it out in the payload. Also fill out system version number and serial number with some constant values. Change-Id: Id1fed5a54b511c730975fa83347452f1274b8504 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu Apr 5 22:38:21 2012, giving +1 See http://review.coreboot.org/867 for details. -gerrit

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Patch merged into coreboot/master: dc63ffb Fill out ChromeOS specific coreboot table extensions
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit dc63ffbd1863337c3b61dd0ea784b4fd7c475a3d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 5 21:22:02 2012 +0200 Fill out ChromeOS specific coreboot table extensions ChromeOS uses two extensions to the coreboot table: - ChromeOS specific GPIO description for onboard switches - position of verified boot area in nvram Change-Id: I8c389feec54c00faf2770aafbfd2223ac9da1362 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu Apr 5 22:08:56 2012, giving +1 See http://review.coreboot.org/866 for details. -gerrit

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Patch merged into coreboot/master: 5d5628a Update documentation in smmrelocate.S to mention TSEG
by gerrit＠coreboot.org 05 Apr '12

05 Apr '12

the following patch was just integrated into master: commit 5d5628a869a1369bb9640ffc25384a3618373bac Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Apr 4 10:38:05 2012 -0700 Update documentation in smmrelocate.S to mention TSEG Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Thu Apr 5 21:52:25 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Apr 5 22:01:15 2012, giving +2 See http://review.coreboot.org/861 for details. -gerrit

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New patch to review for coreboot: c72ad05 Cache 8MB flash instead of 4MB
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/873 -gerrit commit c72ad05e7b3e38f3366bf37f11adfcc6ce42c36f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:24:37 2012 -0700 Cache 8MB flash instead of 4MB Also fix the MTRR check to use the total_mtrrs variable instead of a hardcoded 8. Change-Id: I2c5ceb3910cd949f43ecf5b8aff857d6ffe0b1a5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 47 +++++++++++++++++++++-------------------------- 1 files changed, 21 insertions(+), 26 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index ed7d93b..faa0d93 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -37,7 +37,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> -#include <arch/cpu.h> #include <arch/acpi.h> #if CONFIG_GFXUMA @@ -50,6 +49,24 @@ static unsigned int mtrr_msr[] = { MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, }; +/* 2 MTRRS are reserved for the operating system */ +#define BIOS_MTRRS 6 +#define OS_MTRRS 2 +#define MTRRS (BIOS_MTRRS + OS_MTRRS) + +static int total_mtrrs = MTRRS; +static int bios_mtrrs = BIOS_MTRRS; + +static void detect_var_mtrrs(void) +{ + msr_t msr; + + msr = rdmsr(MTRRcap_MSR); + + total_mtrrs = msr.lo & 0xff; + bios_mtrrs = total_mtrrs - 2; +} + void enable_fixed_mtrr(void) { msr_t msr; @@ -76,8 +93,8 @@ static void set_var_mtrr( msr_t base, mask; unsigned address_mask_high; - if (reg >= 8) - return; + if (reg >= total_mtrrs) + return; // it is recommended that we disable and enable cache when we // do this. @@ -169,28 +186,6 @@ static inline unsigned int fls(unsigned int x) * or a 156MB (128MB + 32MB - 4MB SMA) example: * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB) */ -/* 2 MTRRS are reserved for the operating system */ -#if 1 -#define BIOS_MTRRS 6 -#define OS_MTRRS 2 -#else -#define BIOS_MTRRS 8 -#define OS_MTRRS 0 -#endif -#define MTRRS (BIOS_MTRRS + OS_MTRRS) - -static int total_mtrrs = MTRRS; -static int bios_mtrrs = BIOS_MTRRS; - -static void detect_var_mtrrs(void) -{ - msr_t msr; - - msr = rdmsr(MTRRcap_MSR); - - total_mtrrs = msr.lo & 0xff; - bios_mtrrs = total_mtrrs - 2; -} static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) { @@ -504,7 +499,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) * complete ROM now that we actually have RAM. */ if (boot_cpu() && (acpi_slp_type != 3)) { - set_var_mtrr(total_mtrrs-1, (4096-4)*1024, 4*1024, + set_var_mtrr(total_mtrrs-1, (4096-8)*1024, 8*1024, MTRR_TYPE_WRPROT, address_bits); } #endif

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New patch to review for coreboot: 5a596f7 Add constants for fast path resume copying
by Stefan Reinauer 05 Apr '12

05 Apr '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/872 -gerrit commit 5a596f7a8fb66d12c2888d8bb91ea883c2fceea0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Apr 3 16:21:04 2012 -0700 Add constants for fast path resume copying cache as ram does not usually cache the ram before it is up. Hence, if romstage.c backs up resume memory, the involved memcpy is always uncached. This makes resume very slow. On Sandybridge we copy the memory later, after enabling caching, and that allows us to resume in as little as 250ms. Change-Id: I31a71ad4468679d39880cf9a8c4e497bb7addf8f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/include/cbmem.h | 17 +++++++++++++---- 1 files changed, 13 insertions(+), 4 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 6a48dd2..c55a7ca 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -27,13 +27,15 @@ #define HIGH_MEMORY_DEF_SIZE ( 128 * 1024 ) #endif -#ifndef __PRE_RAM__ -extern uint64_t high_tables_base, high_tables_size; -#endif - #if CONFIG_HAVE_ACPI_RESUME #define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) #define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE ) + +/* Delegation of resume backup memory so we don't have to + * (slowly) handle backing up OS memory in romstage.c + */ +#define CBMEM_BOOT_MODE 0x610 +#define CBMEM_RESUME_BACKUP 0x614 #else #define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE #endif @@ -47,9 +49,15 @@ extern uint64_t high_tables_base, high_tables_size; #define CBMEM_ID_RESUME 0x5245534d #define CBMEM_ID_SMBIOS 0x534d4254 #define CBMEM_ID_TIMESTAMP 0x54494d45 +#define CBMEM_ID_MRCDATA 0x4d524344 #define CBMEM_ID_CONSOLE 0x434f4e53 #define CBMEM_ID_NONE 0x00000000 +#ifndef __ASSEMBLER__ +#ifndef __PRE_RAM__ +extern uint64_t high_tables_base, high_tables_size; +#endif + int cbmem_initialize(void); void cbmem_init(u64 baseaddr, u64 size); @@ -65,3 +73,4 @@ extern struct cbmem_entry *get_cbmem_toc(void); void set_cbmem_toc(struct cbmem_entry *); #endif #endif +#endif

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coreboot April 2012