coreboot April 2012

coreboot@coreboot.org

39 participants
459 discussions

Patch merged into coreboot/master: bbedf7e Add support for MA785GM-US2H
by gerrit＠coreboot.org 23 Apr '12

23 Apr '12

the following patch was just integrated into master: commit bbedf7e55f845e022e0149e9b7bf005f4c559cb1 Author: Alec Ari <neotheuser(a)ymail.com> Date: Sun Jan 8 14:49:44 2012 -0600 Add support for MA785GM-US2H This patch adds coreboot support for the GIGABYTE MA785GM-US2H board. This port now removes all dead code in the previous patch set, and also boots Fedora 16 on x86_64 (Phenom II X4 955 BE) On-board audio causes spurious interrupts and the kernel gets stuck in an infinite loop. AtomBIOS on RadeonHD video cards does not function and causes another infinite loop. radeon.modeset=0 must be set. acpi=off must also be set. With those kernel command line options set, Fedora 16 makes it to the login screen. USB mouse and keyboard don't work though. several USB error codes on boot-up. PS/2 should. Change-Id: I58a7083a023ebf7373b6ded2e9f0adda7ab76dea Signed-off-by: Alec Ari <neotheuser(a)ymail.com> Build-Tested: build bot (Jenkins) at Sun Jan 8 22:07:53 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 23 22:27:05 2012, giving +2 See http://review.coreboot.org/476 for details. -gerrit

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Patch merged into coreboot/master: 56d8552 alix2: add support for alix6
by gerrit＠coreboot.org 23 Apr '12

23 Apr '12

the following patch was just integrated into master: commit 56d8552a1bb3cd9aca669899e4d2e8a18534d006 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Fri Jan 6 11:54:23 2012 -0700 alix2: add support for alix6 The Alix6 is very similar to the alix2, differing in having 1 mini-PCIe slot (USB 2.0 only), an RFKILL GPIO line going to that slot, and 1 or 2 SIM sockets. Change-Id: I19e4e756966e60bb0310c19286654d3d579b8850 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> Build-Tested: build bot (Jenkins) at Mon Jan 9 05:00:37 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Apr 23 22:24:45 2012, giving +2 See http://review.coreboot.org/521 for details. -gerrit

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Trac reminder: list of new ticket(s)
by coreboot tracker 23 Apr '12

23 Apr '12

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Re: [coreboot] ASUS M2V problems
by G 23 Apr '12

23 Apr '12

On Mon, Apr 23, 2012 at 12:33 PM, ali hagigat <hagigatali(a)gmail.com> wrote: > You'd better buy a debug card and plug into the PCI slot and see what > numbers it will display. It has two seven segment components. > Besides you can disable coreboot post codes and insert your own post > codes to see how far the program runs. > I did the same for my motherboard... Thanks, but as I wrote on April 13th, I have managed to get some output over serial, but still nothing on VGA or any response to keyboard events. Details, and serial log and config file, can be found in my April 13th message. > On Wed, Apr 11, 2012 at 1:18 PM, G <tjmadwja(a)gmail.com> wrote: >> On Tue, Apr 10, 2012 at 5:26 PM, Marc Jones <marcj303(a)gmail.com> wrote: >>> On Tue, Apr 10, 2012 at 7:37 AM, G <tjmadwja(a)gmail.com> wrote: >>>> Hi, >>>> >>>> I'm trying to get coreboot onto my old ASUS M2V (rev. 1.01g) >>>> motherboard, but so far I've had no luck. I'm currently trying to >>>> get the coreinfo payload running, as that seems like the simplest >>>> test case (I've also tried seabios, and failed). >>>> >>>> After flashing, when I boot, nothing happens. No beeps, the >>>> monitor remains in power-save mode, the keyboard doesn't respond >>>> to any keypresses (not even holding down several keys for a long >>>> time generates any beeps), no blinking status LEDs, nothing on >>>> the serial port. Nothing. >>>> >>>> I've tried with two different revisions, one from 2010-11-24 (the >>>> one that adds S3 support for ASUS M2V), and one from 2012-02-21 >>>> (all later revisions fail to compile with lots of different CBMEM >>>> problems). >>>> >>>> In the 2010-11-24 revision, I've had to add >>>> reg++; reg--; >>>> in src/northbridge/amd/amdk8/raminit_f_dqs.c:setup_mtrr_dqs() and >>>> regm3++; regm3--; >>>> in src/southbridge/via/vt8237r/vt8237_ctrl.c:vt8237_cfg() to get >>>> rid of warnings about unused variables. >>>> >>>> Flashing is done by simply running: >>>> ./flashrom -V -w coreboot.rom -c W39V040C >>>> >>>> Does anyone here have any idea what might be wrong? Anyone got a >>>> working .config, tips to use a certain known working revision, a >>>> know working version of flashrom (although flashing two different >>>> versions of ASUS's BIOS using flashrom works well, so I'm >>>> guessing neither flashrom nor my usage of it is to blame), a >>>> working coreboot.rom they can share, or anything else that might >>>> help me move forward? >>>> >>>> Using Debian unstable to build, if that's any help. >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> http://www.coreboot.org/mailman/listinfo/coreboot >>> >>> >>> Hi, >>> >>> You will need to capture some output from coreboot to find where your >>> system is having problems. >>> >>> http://www.coreboot.org/FAQ#How_do_I_use_a_null-modem_cable_to_get_coreboot… >> >> Thanks for the reply, but unfortunately, as I wrote in my >> original mail, I get nothing on the serial port. >> >> When I boot the standard ASUS M2V BIOS, with a null-modem cable >> plugged in, then exactly as I power on the M2V system, minicom on >> the other end briefly (less than a second) switches from Offline >> to Online, and then back to Offline, and then the system >> continues to boot. >> >> Booting coreboot, minicom switches from Offline to Online exactly >> when I power on the M2V system, and then the minicom status on >> the other machine remains Online, but nothing ever arrives in the >> minicom terminal window, and nothing else happens (no beeps, not >> LEDs, nothing on the screen, just plain nothing). >> >> I have tested that the minicom connection over null-modem cable >> between my M2V computer and the other machine works after booting >> the standard ASUS M2V BIOS, although I then have HW flow control >> enabled, which is then disabled before trying to boot the >> coreboot BIOS. And yes, I have checked the serial port settings >> in the coreboot config and they are set to the correct values. >> >> So, anyone got a working .config and/or working coreboot.rom I >> can try? A known working coreboot revision I should download and >> compile? Or any other tips/pointers? >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] ASUS M2V problems
by ali hagigat 23 Apr '12

23 Apr '12

You'd better buy a debug card and plug into the PCI slot and see what numbers it will display. It has two seven segment components. Besides you can disable coreboot post codes and insert your own post codes to see how far the program runs. I did the same for my motherboard... On Wed, Apr 11, 2012 at 1:18 PM, G <tjmadwja(a)gmail.com> wrote: > On Tue, Apr 10, 2012 at 5:26 PM, Marc Jones <marcj303(a)gmail.com> wrote: >> On Tue, Apr 10, 2012 at 7:37 AM, G <tjmadwja(a)gmail.com> wrote: >>> Hi, >>> >>> I'm trying to get coreboot onto my old ASUS M2V (rev. 1.01g) >>> motherboard, but so far I've had no luck. I'm currently trying to >>> get the coreinfo payload running, as that seems like the simplest >>> test case (I've also tried seabios, and failed). >>> >>> After flashing, when I boot, nothing happens. No beeps, the >>> monitor remains in power-save mode, the keyboard doesn't respond >>> to any keypresses (not even holding down several keys for a long >>> time generates any beeps), no blinking status LEDs, nothing on >>> the serial port. Nothing. >>> >>> I've tried with two different revisions, one from 2010-11-24 (the >>> one that adds S3 support for ASUS M2V), and one from 2012-02-21 >>> (all later revisions fail to compile with lots of different CBMEM >>> problems). >>> >>> In the 2010-11-24 revision, I've had to add >>> reg++; reg--; >>> in src/northbridge/amd/amdk8/raminit_f_dqs.c:setup_mtrr_dqs() and >>> regm3++; regm3--; >>> in src/southbridge/via/vt8237r/vt8237_ctrl.c:vt8237_cfg() to get >>> rid of warnings about unused variables. >>> >>> Flashing is done by simply running: >>> ./flashrom -V -w coreboot.rom -c W39V040C >>> >>> Does anyone here have any idea what might be wrong? Anyone got a >>> working .config, tips to use a certain known working revision, a >>> know working version of flashrom (although flashing two different >>> versions of ASUS's BIOS using flashrom works well, so I'm >>> guessing neither flashrom nor my usage of it is to blame), a >>> working coreboot.rom they can share, or anything else that might >>> help me move forward? >>> >>> Using Debian unstable to build, if that's any help. >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >> >> >> Hi, >> >> You will need to capture some output from coreboot to find where your >> system is having problems. >> >> http://www.coreboot.org/FAQ#How_do_I_use_a_null-modem_cable_to_get_coreboot… > > Thanks for the reply, but unfortunately, as I wrote in my > original mail, I get nothing on the serial port. > > When I boot the standard ASUS M2V BIOS, with a null-modem cable > plugged in, then exactly as I power on the M2V system, minicom on > the other end briefly (less than a second) switches from Offline > to Online, and then back to Offline, and then the system > continues to boot. > > Booting coreboot, minicom switches from Offline to Online exactly > when I power on the M2V system, and then the minicom status on > the other machine remains Online, but nothing ever arrives in the > minicom terminal window, and nothing else happens (no beeps, not > LEDs, nothing on the screen, just plain nothing). > > I have tested that the minicom connection over null-modem cable > between my M2V computer and the other machine works after booting > the standard ASUS M2V BIOS, although I then have HW flow control > enabled, which is then disabled before trying to boot the > coreboot BIOS. And yes, I have checked the serial port settings > in the coreboot config and they are set to the correct values. > > So, anyone got a working .config and/or working coreboot.rom I > can try? A known working coreboot revision I should download and > compile? Or any other tips/pointers? > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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Patch merged into coreboot/master: 9398cfc Unbreak boards where chipset can select between FSB and serial APIC bus
by gerrit＠coreboot.org 23 Apr '12

23 Apr '12

the following patch was just integrated into master: commit 9398cfcac1da9342e94a574e4c31c9e0b65198fd Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Apr 22 23:52:23 2012 +0200 Unbreak boards where chipset can select between FSB and serial APIC bus Commit d4d5e4d3e10da06a83d57a147bd58a733381de18 contains #ifdef instead of #if, making the FSB/serial bus selection for APIC always select serial bus. The bug is harmless on most chipsets because the bit is often RO, but it breaks at least on VIA K8T890. Change-Id: I89c4855922199eca7f921c3e4eb500656544c8e5 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Build-Tested: build bot (Jenkins) at Mon Apr 23 00:40:52 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Mon Apr 23 00:48:22 2012, giving +2 See http://review.coreboot.org/921 for details. -gerrit

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Patch set updated for coreboot: 9398cfc Unbreak boards where chipset can select between FSB and serial APIC bus
by Peter Stuge 23 Apr '12

23 Apr '12

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/921 -gerrit commit 9398cfcac1da9342e94a574e4c31c9e0b65198fd Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Apr 22 23:52:23 2012 +0200 Unbreak boards where chipset can select between FSB and serial APIC bus Commit d4d5e4d3e10da06a83d57a147bd58a733381de18 contains #ifdef instead of #if, making the FSB/serial bus selection for APIC always select serial bus. The bug is harmless on most chipsets because the bit is often RO, but it breaks at least on VIA K8T890. Change-Id: I89c4855922199eca7f921c3e4eb500656544c8e5 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/arch/x86/lib/ioapic.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index e974d7c..57b99e2 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -89,7 +89,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) ioapic_interrupts = 24; printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); -#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_FSB +#if CONFIG_IOAPIC_INTERRUPTS_ON_FSB /* * For the Pentium 4 and above APICs deliver their interrupts * on the front side bus, enable that. @@ -98,7 +98,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); #endif -#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS +#if CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); #endif

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New patch to review for coreboot: 2f34f0c Unbreak all boards where chipset is capable of selection of FSB/serial APIC bus
by Rudolf Marek 23 Apr '12

23 Apr '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/921 -gerrit commit 2f34f0c19b365f2cf1ac221dd6bdb667e92f5baf Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Apr 22 23:52:23 2012 +0200 Unbreak all boards where chipset is capable of selection of FSB/serial APIC bus The commit Change I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f contains #ifdef instead of #if making the FSB/serial bus selection for APIC always to fall to serial APIC bus This bug is not visible on most chipsets, because this bit is RO, but it do broke VIA K8T890 chipsets. Change-Id: I89c4855922199eca7f921c3e4eb500656544c8e5 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/arch/x86/lib/ioapic.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index e974d7c..57b99e2 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -89,7 +89,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) ioapic_interrupts = 24; printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); -#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_FSB +#if CONFIG_IOAPIC_INTERRUPTS_ON_FSB /* * For the Pentium 4 and above APICs deliver their interrupts * on the front side bus, enable that. @@ -98,7 +98,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); #endif -#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS +#if CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); #endif

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Patch merged into coreboot/master: a40d82e Drop build_opt_tbl
by gerrit＠coreboot.org 22 Apr '12

22 Apr '12

the following patch was just integrated into master: commit a40d82ec4f63fa0e06f16cf94d433af81ceb71ab Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Apr 21 21:11:52 2012 +0200 Drop build_opt_tbl It's gone from the build. Drop the code as well. Change-Id: Ice6fcb39565273360a576bda4826f16088f4666c Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Apr 22 10:23:47 2012, giving +2 See http://review.coreboot.org/914 for details. -gerrit

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Patch merged into coreboot/master: 2ec25fe amd: Fix unused variable warning
by gerrit＠coreboot.org 22 Apr '12

22 Apr '12

the following patch was just integrated into master: commit 2ec25fea1e3de3355784e62808fb9eb1c28e0fe8 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Sun Apr 22 00:17:04 2012 +0530 amd: Fix unused variable warning Comment out the id variable which is used in a commented code block. Change-Id: Ib002d57e5314971f0589d04b7e451ab7d7079f53 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Apr 22 08:53:38 2012, giving +2 See http://review.coreboot.org/913 for details. -gerrit

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coreboot April 2012