coreboot April 2012

coreboot@coreboot.org

39 participants
459 discussions

Patch merged into coreboot/master: 52c1746 coreboot_table.c: Add missing include files
by gerrit＠coreboot.org 27 Apr '12

27 Apr '12

the following patch was just integrated into master: commit 52c1746e86e7b742b3dede6337114d409dfdb928 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 00:34:54 2012 +0200 coreboot_table.c: Add missing include files If compiling coreboot with ChromeOS support, two more include files are required. Change-Id: I7e042e250e4a89e7dd4bab58443824d503c3f709 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 27 01:51:10 2012, giving +1 See http://review.coreboot.org/931 for details. -gerrit

1 0

New patch to review for coreboot: 8e3cd8c Update amd/south_station/fadt.c with various fixes
by Martin Roth 27 Apr '12

27 Apr '12

Martin Roth (martin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/942 -gerrit commit 8e3cd8cccd75e1093821e68f79a59db5211e9b7b Author: Martin Roth <martin(a)se-eng.com> Date: Fri Apr 27 11:48:32 2012 -0600 Update amd/south_station/fadt.c with various fixes This is a model fadt.c that I would like to use for updating several other AMD platforms with after acceptance. - Updated to match ACPI 3.0b specification and added comments to reflect that. - Since smi_cmd is 0, remove commands that rely on it: acpi_enable, acpi_disable, & pstate_cnt Add comments to that effect. - Changed preferred_pm_profile to SOHO Server (platform specific) - The southstation platform is legacy free - Updated iapc_boot_arch and flags to reflect that. - Added reset_register flag so that operating systems will actually use the reset_reg. This is important on legacy free systems. - Updated Generic Address Structures to use access_size name in the updated acpi.h. Added access sizes to the structures where reasonable. - Removed 64-bit x_firmware_ctl pointer to facs. This was causing a fwts failure and windows-64 BSOD. - Added bit width for pm2_cnt_blk and modified gpe0_blk bit to match the hardware. Change-Id: Icf1a982aa122636d1088c8b80f53d04732b54c49 Signed-off-by: Martin L Roth <martin(a)se-eng.com> --- src/mainboard/amd/south_station/fadt.c | 105 +++++++++++++++++++------------- 1 files changed, 62 insertions(+), 43 deletions(-) diff --git a/src/mainboard/amd/south_station/fadt.c b/src/mainboard/amd/south_station/fadt.c index 020d011..23dfa1f 100644 --- a/src/mainboard/amd/south_station/fadt.c +++ b/src/mainboard/amd/south_station/fadt.c @@ -30,17 +30,23 @@ #include <device/device.h> #include "SBPLATFORM.h" + +/* + * Reference section 5.2.9 Fixed ACPI Description Table (FADT) + * in the ACPI 3.0b specification. + */ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { u16 val = 0; acpi_header_t *header = &(fadt->header); printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); + /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); - header->length = 244; - header->revision = 3; + header->length = sizeof(acpi_fadt_t); + header->revision = ACPI_FADT_REV_ACPI_3_0; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); @@ -48,15 +54,14 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ - fadt->preferred_pm_profile = 0x03; - fadt->sci_int = 9; - /* disable system management mode by setting to 0: */ - fadt->smi_cmd = 0; - fadt->acpi_enable = 0xf0; - fadt->acpi_disable = 0xf1; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0xe2; + fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->preferred_pm_profile = PM_SOHO_SERVER; + fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 – ACPI SCI */ + fadt->smi_cmd = 0; /* disable system management mode */ + fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ + fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ + fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ + fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ val = PM1_EVT_BLK_ADDRESS; WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); @@ -90,7 +95,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; fadt->gpe0_blk = GPE0_BLK_ADDRESS; - fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + fadt->gpe1_blk = 0; /* No gpe1 block in hudson1 */ fadt->pm1_evt_len = 4; fadt->pm1_cnt_len = 2; @@ -103,89 +108,103 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->cst_cnt = 0xe3; fadt->p_lvl2_lat = 101; fadt->p_lvl3_lat = 1001; - fadt->flush_size = 0; - fadt->flush_stride = 0; + fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ fadt->duty_offset = 1; fadt->duty_width = 3; fadt->day_alrm = 0; /* 0x7d these have to be */ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ fadt->century = 0; /* 0x7f to make rtc alrm work */ - fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ - fadt->flags = 0x0001c1a5;/* 0x25; */ - - fadt->res2 = 0; - - fadt->reset_reg.space_id = 1; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; /* See table 5-10 */ + fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON; + + /* Format is from 5.2.3.1: Generic Address Structure */ + /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ + /* 8 bit write of value 0x06 to 0xCF9 in IO space */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->reset_reg.addrl = 0xcf9; fadt->reset_reg.addrh = 0x0; - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; + + fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + + fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = (u32) dsdt; fadt->x_dsdt_h = 0; - fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.access_size = 0; fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; fadt->x_pm1a_evt_blk.addrh = 0x0; - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.access_size = 0; fadt->x_pm1b_evt_blk.addrl = 0x0; fadt->x_pm1b_evt_blk.addrh = 0x0; - fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.access_size = 0; fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; fadt->x_pm1a_cnt_blk.addrh = 0x0; - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; fadt->x_pm1b_cnt_blk.addrl = 0x0; fadt->x_pm1b_cnt_blk.addrh = 0x0; - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; /* Hudson 1 Pm2Control is 8 bits */ fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; fadt->x_pm2_cnt_blk.addrh = 0x0; - fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.access_size = 0; fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; fadt->x_pm_tmr_blk.addrh = 0x0; - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; fadt->x_gpe0_blk.addrh = 0x0; - fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_gpe1_blk.bit_width = 0; fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = 0; fadt->x_gpe1_blk.addrh = 0x0;

1 0

Patch merged into coreboot/master: 7f88aa1 SMM: Add udelay on Sandybridge systems
by gerrit＠coreboot.org 27 Apr '12

27 Apr '12

the following patch was just integrated into master: commit 7f88aa1f2b39f0486f6cbee69df2cff0def4fee9 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 01:05:11 2012 +0200 SMM: Add udelay on Sandybridge systems Cougar Point southbridge does udelay in SMM, hence add it on Sandybridge systems. Change-Id: I6e5520ca27e7c6eaae632992fb68612067bc1e30 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 27 03:32:57 2012, giving +1 See http://review.coreboot.org/937 for details. -gerrit

1 0

Patch merged into coreboot/master: f98635b Cougar Point southbridge: Add includes and drop post_code()
by gerrit＠coreboot.org 27 Apr '12

27 Apr '12

the following patch was just integrated into master: commit f98635bb077d263d279216f107fd130201c1ccd1 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 01:02:26 2012 +0200 Cougar Point southbridge: Add includes and drop post_code() post_code() was added in our internal tree by duplicating code. It's not of much use at this point, since the code is quite well tested, so avoid bloating the bootblock (since compiled with ROMCC). Also add some missing include files that didn't seem to be needed with an older version of coreboot. Change-Id: Id62b838728a247e8bcadb4f1db17269be0d4f3f4 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 27 03:19:23 2012, giving +1 See http://review.coreboot.org/936 for details. -gerrit

1 0

Patch merged into coreboot/master: 33a8fab ChromeOS: add missing string.h in gnvs.c
by gerrit＠coreboot.org 27 Apr '12

27 Apr '12

the following patch was just integrated into master: commit 33a8fabdf07f07531b8ef2e3d88e95836acacaae Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 00:48:58 2012 +0200 ChromeOS: add missing string.h in gnvs.c string.h is required to build with the reference toolchain. Change-Id: I9fd8d2ea8fc676d3502989cbcc7aefe3b2d738b6 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 27 03:06:05 2012, giving +1 See http://review.coreboot.org/935 for details. -gerrit

1 0

Patch merged into coreboot/master: 56ddc41 SMSC MEC1308: Fix ACPI code to work with newer IASL versions
by gerrit＠coreboot.org 27 Apr '12

27 Apr '12

the following patch was just integrated into master: commit 56ddc41d17986ff7be91a5382c08c8beddd90663 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 00:47:21 2012 +0200 SMSC MEC1308: Fix ACPI code to work with newer IASL versions Newer versions of IASL didn't like our IO constructs. Use FixedIO instead, it's also shorter. Change-Id: I9364d993ecb71ffd84c0313ca1e2f870af59eb24 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 27 02:52:38 2012, giving +1 See http://review.coreboot.org/934 for details. -gerrit

1 0

Patch merged into coreboot/master: 29e5654 SMM: unify mainboard APM command handlers
by gerrit＠coreboot.org 27 Apr '12

27 Apr '12

the following patch was just integrated into master: commit 29e565474ac898c7b846d45aa5d4e27e2eb6b4db Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 00:44:04 2012 +0200 SMM: unify mainboard APM command handlers rename from mainboard_apm_cnt to mainboard_smi_apmc to match the function naming scheme of the other handlers. Add prototype for mainboard_smi_sleep (mainboard specific S3 sleep handlers in SMM) that is required by Sandybridge. Change-Id: Ib479397e460e33772d90d9d41dba267e4e7e3008 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 27 02:37:15 2012, giving +1 See http://review.coreboot.org/933 for details. -gerrit

1 0

Patch merged into coreboot/master: 93fef85 cpu/cpu.h: add ROMCC guards
by gerrit＠coreboot.org 27 Apr '12

27 Apr '12

the following patch was just integrated into master: commit 93fef85dc9f8e732c1905cf53828ee5782e43df1 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 00:39:17 2012 +0200 cpu/cpu.h: add ROMCC guards In order to use the generic microcode update code in the bootblock, cpu/cpu.h needs ROMCC guards. Also, delete the unused struct device declaration and move the struct bus declaration to where it's used. Change-Id: I0cc731c555593946e931a680ec93994932530599 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 27 02:21:08 2012, giving +1 See http://review.coreboot.org/932 for details. -gerrit

1 0

Patch merged into coreboot/master: d64e293 Move top level pc80 directory to drivers/
by gerrit＠coreboot.org 27 Apr '12

27 Apr '12

the following patch was just integrated into master: commit d64e293cd12e936e236c3e373d00af5f6b679b07 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Apr 27 02:31:28 2012 +0200 Move top level pc80 directory to drivers/ There is no reason for this to be a top level directory. Some stuff from lib/ should also be moved to drivers/ Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Apr 27 06:46:20 2012, giving +1 See http://review.coreboot.org/939 for details. -gerrit

1 0

Patch set updated for coreboot: 8e0e8bc Reverse Vendor ID & Device ID for map_oprom_vendev()
by Martin Roth 27 Apr '12

27 Apr '12

Martin Roth (martin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/938 -gerrit commit 8e0e8bc705bcf1394c1b0e2fb2144f08fada8803 Author: Martin Roth <martin(a)se-eng.com> Date: Thu Apr 26 16:04:18 2012 -0600 Reverse Vendor ID & Device ID for map_oprom_vendev() - When calling map_oprom_vendev() the vendor ID and device ID are joined into a 32 bit value. They were reversed from the order that I would have expected - Device ID as the high 16 bits and the Vendor ID as the low 16. This patch reverses them so so that the the dword comparison in map_oprom_vendev() matches what's entered into Kconfig for vendor,device. - Change files calling map_oprom_vendev() Change-Id: I5b84db3cb1a359a7533409fde7d05fbc6ba3fcc4 Signed-off-by: Martin L Roth <martin(a)se-eng.com> --- src/devices/pci_rom.c | 6 +++--- src/northbridge/intel/sandybridge/gma.c | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c index 800776e..e7933eb 100644 --- a/src/devices/pci_rom.c +++ b/src/devices/pci_rom.c @@ -37,7 +37,7 @@ struct rom_header *pci_rom_probe(struct device *dev) /* If it's in FLASH, then don't check device for ROM. */ rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL); - u32 vendev = dev->vendor | (dev->device << 16); + u32 vendev = (dev->vendor << 16) | dev->device; u32 mapped_vendev = vendev; if (map_oprom_vendev) @@ -45,8 +45,8 @@ struct rom_header *pci_rom_probe(struct device *dev) if (!rom_header) { if (vendev != mapped_vendev) { - rom_header = cbfs_load_optionrom(mapped_vendev & - 0xffff, mapped_vendev >> 16, NULL); + rom_header = cbfs_load_optionrom(mapped_vendev >> 16, + mapped_vendev & 0xffff , NULL); } } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 00b5957..4aabb75 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -37,14 +37,14 @@ u32 map_oprom_vendev(u32 vendev) u32 new_vendev=vendev; switch (vendev) { - case 0x01028086: /* GT1 Desktop */ - case 0x010a8086: /* GT1 Server */ - case 0x01128086: /* GT2 Desktop */ - case 0x01168086: /* GT2 Mobile */ - case 0x01228086: /* GT2 Desktop >=1.3GHz */ - case 0x01268086: /* GT2 Mobile >=1.3GHz */ - case 0x01668086: /* IVB */ - new_vendev=0x01068086; /* GT1 Mobile */ + case 0x80860102: /* GT1 Desktop */ + case 0x8086010a: /* GT1 Server */ + case 0x80860112: /* GT2 Desktop */ + case 0x80860116: /* GT2 Mobile */ + case 0x80860122: /* GT2 Desktop >=1.3GHz */ + case 0x80860126: /* GT2 Mobile >=1.3GHz */ + case 0x80860166: /* IVB */ + new_vendev=0x80860106; /* GT1 Mobile */ break; }

1 0

← Newer
1
...
7
8
9
10
11
12
13
...
46
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2012