New patch to review for coreboot: f98635b Cougar Point southbridge: Add includes and drop post_code()

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/936

-gerrit

commit f98635bb077d263d279216f107fd130201c1ccd1
Author: Stefan Reinauer 
Date:   Fri Apr 27 01:02:26 2012 +0200

Cougar Point southbridge: Add includes and drop post_code()

post_code() was added in our internal tree by duplicating code. It's not of
    much use at this point, since the code is quite well tested, so avoid bloating
    the bootblock (since compiled with ROMCC).
    Also add some missing include files that didn't seem to be needed with an
    older version of coreboot.

Change-Id: Id62b838728a247e8bcadb4f1db17269be0d4f3f4
    Signed-off-by: Stefan Reinauer 
---
 src/southbridge/intel/bd82x6x/bootblock.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 686e820..d6cba5f 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -17,6 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/tsc.h>
 #include "pch.h"

static void store_initial_timestamp(void)
@@ -59,7 +62,6 @@ static void enable_port80_on_lpc(void)
    u32 reg32 = *gcs;
    reg32 = reg32 & ~0x04;
    *gcs = reg32;
-	post_code(0x01);
 #endif
 }