coreboot May 2011

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Hi from LinuxTag 2011
by Peter Stuge 13 May '11

13 May '11

Greetings from Berlin! //Peter

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[commit] r6569 - trunk/src/mainboard/siemens/sitemp_g1p1
by repository service 13 May '11

13 May '11

Author: oxygene Date: Fri May 13 08:25:16 2011 New Revision: 6569 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6569 Log: siemens/sitemp_g1p1: Adapt read_option() to latest changes Signed-off-by: Josef Kellermann <seppk(a)arcor.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c Modified: trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c ===============================================================… [View More]

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read_option() in sitemp_g1p1/romstage.c
by Josef Kellermann 12 May '11

12 May '11

attached patch changes read_option() in mainboard/siemens/sitemp_g1p1/romstage.c. Signed-off-by: Josef Kellermann <seppk(a)arcor.de> <mailto://seppk@arcor.de>

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[commit] r6568 - trunk/src/mainboard/siemens/sitemp_g1p1
by repository service 12 May '11

12 May '11

Author: oxygene Date: Thu May 12 08:53:52 2011 New Revision: 6568 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6568 Log: Remove uart_init() in Siemens sitemp-g1p1 uart_init() was moved to common code in r6531, but I missed that when integrating the new mainboard code. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Acked-by: Patrick Georgi <patrick.georgi(a)secunet.com> Modified: trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c Modified: trunk/src/… [View More]

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support for siemens sitemp mainboard
by Josef Kellermann 11 May '11

11 May '11

I've compiled support for the Siemens 'sitemp' Mainboard. The board is similar to the AMD dbm690t. I adapt the code from the dbm690t according to customer requirement specification. I've been testing Linux as well as Windows XP booting on this board. Added 2 patches: 0001-mainboard-siemens.patch 0002-mainboard_kconfig.patch Signed-off-by: Josef Kellermann <seppk(a)arcor.de> <mailto://seppk@arcor.de>

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[commit] r6567 - in trunk/src/mainboard: . siemens siemens/sitemp_g1p1 siemens/sitemp_g1p1/acpi
by repository service 11 May '11

11 May '11

Author: oxygene Date: Wed May 11 09:47:43 2011 New Revision: 6567 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6567 Log: Add Siemens SITEMP-G1 board The code is loosely based on AMD dbm690t (and copied from there) and adapted to match the Siemens SITEMP-G1 board. It boots both Linux and Windows XP (and if it doesn't then complain with me [Patrick] because in that case I must have messed it up when integrating the patch) Signed-off-by: Josef Kellermann <seppk(a)arcor.de> … [View More]Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Added: trunk/src/mainboard/siemens/ trunk/src/mainboard/siemens/Kconfig trunk/src/mainboard/siemens/sitemp_g1p1/ - copied from r6565, trunk/src/mainboard/amd/dbm690t/ trunk/src/mainboard/siemens/sitemp_g1p1/Makefile.inc trunk/src/mainboard/siemens/sitemp_g1p1/acpi/debug.asl trunk/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl trunk/src/mainboard/siemens/sitemp_g1p1/acpi/globutil.asl trunk/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl trunk/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl trunk/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.c trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.h Modified: trunk/src/mainboard/Kconfig trunk/src/mainboard/siemens/sitemp_g1p1/Kconfig trunk/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl trunk/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl trunk/src/mainboard/siemens/sitemp_g1p1/acpi/sata.asl trunk/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl trunk/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c trunk/src/mainboard/siemens/sitemp_g1p1/chip.h trunk/src/mainboard/siemens/sitemp_g1p1/cmos.layout trunk/src/mainboard/siemens/sitemp_g1p1/devicetree.cb trunk/src/mainboard/siemens/sitemp_g1p1/dsdt.asl trunk/src/mainboard/siemens/sitemp_g1p1/fadt.c trunk/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c trunk/src/mainboard/siemens/sitemp_g1p1/irq_tables.c trunk/src/mainboard/siemens/sitemp_g1p1/mainboard.c trunk/src/mainboard/siemens/sitemp_g1p1/mptable.c trunk/src/mainboard/siemens/sitemp_g1p1/resourcemap.c trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c Modified: trunk/src/mainboard/Kconfig ============================================================================== --- trunk/src/mainboard/Kconfig Wed May 11 09:44:27 2011 (r6566) +++ trunk/src/mainboard/Kconfig Wed May 11 09:47:43 2011 (r6567) @@ -92,6 +92,8 @@ bool "RCA" config VENDOR_RODA bool "Roda" +config VENDOR_SIEMENS + bool "Siemens" config VENDOR_SOYO bool "Soyo" config VENDOR_SUNW @@ -163,6 +165,7 @@ source "src/mainboard/pcengines/Kconfig" source "src/mainboard/rca/Kconfig" source "src/mainboard/roda/Kconfig" +source "src/mainboard/siemens/Kconfig" source "src/mainboard/soyo/Kconfig" source "src/mainboard/sunw/Kconfig" source "src/mainboard/supermicro/Kconfig" Added: trunk/src/mainboard/siemens/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/siemens/Kconfig Wed May 11 09:47:43 2011 (r6567) @@ -0,0 +1,17 @@ +if VENDOR_SIEMENS + +choice + prompt "Mainboard model" + +config BOARD_SIEMENS_SITEMP_G1P1 + bool "MB SITEMP-G1 (U1P0/U1P1)" + +endchoice + +source "src/mainboard/siemens/sitemp_g1p1/Kconfig" + +config MAINBOARD_VENDOR + string + default "Siemens" + +endif # VENDOR_SIEMENS Modified: trunk/src/mainboard/siemens/sitemp_g1p1/Kconfig ============================================================================== --- trunk/src/mainboard/amd/dbm690t/Kconfig Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/Kconfig Wed May 11 09:47:43 2011 (r6567) @@ -1,4 +1,4 @@ -if BOARD_AMD_DBM690T +if BOARD_SIEMENS_SITEMP_G1P1 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -22,10 +22,16 @@ select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT select SET_FIDVID - + select GFXUMA + select EXT_CONF_SUPPORT + config MAINBOARD_DIR string - default amd/dbm690t + default siemens/sitemp_g1p1 + +config LINT01_CONVERSION + bool + default y config APIC_ID_OFFSET hex @@ -33,7 +39,7 @@ config MAINBOARD_PART_NUMBER string - default "DBM690T" + default "MB SITEMP-G1 (U1P0/U1P1)" config MAX_CPUS int @@ -42,7 +48,7 @@ config MAX_PHYSICAL_CPUS int default 1 - + config SB_HT_CHAIN_ON_BUS0 int default 1 @@ -59,4 +65,16 @@ int default 11 -endif # BOARD_AMD_DBM690T +config IOMMU + bool + default n + +config HW_SCRUBBER + bool + default n + +config ECC_MEMORY + bool + default n + +endif # BOARD_SIEMENS_SITEMP_G1P1 Added: trunk/src/mainboard/siemens/sitemp_g1p1/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/siemens/sitemp_g1p1/Makefile.inc Wed May 11 09:47:43 2011 (r6567) @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2010 Siemens AG, Inc. +## (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-y += int15_func.c + Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/debug.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/debug.asl Wed May 11 09:47:43 2011 (r6567) @@ -0,0 +1,198 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + DefinitionBlock ( + "DSDT.AML", + "DSDT", + 0x01, + "XXXXXX", + "XXXXXXXX", + 0x00010001 + ) + { + #include "debug.asl" + } +*/ + +/* +* 0x80: POST_BASE +* 0x3F8: DEBCOM_BASE +* X80: POST_REGION +* P80: PORT80 +* +* CREG: DEBCOM_REGION +* CUAR: DEBCOM_UART +* CDAT: DEBCOM_DATA +* CDLM: DEBCOM_DLM +* DLCR: DEBCOM_LCR +* CMCR: DEBCOM_MCR +* CLSR: DEBCOM_LSR +* +* DEBUG_INIT DINI +*/ + +OperationRegion(X80, SystemIO, 0x80, 1) + Field(X80, ByteAcc, NoLock, Preserve) +{ + P80, 8 +} + +OperationRegion(CREG, SystemIO, 0x3F8, 8) + Field(CREG, ByteAcc, NoLock, Preserve) +{ + CDAT, 8, + CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8 +} + +/* +* DINI +* Initialize the COM port to 115,200 8-N-1 +*/ +Method(DINI) +{ + store(0x83, DLCR) + store(0x01, CDAT) /* 115200 baud (low) */ + store(0x00, CDLM) /* 115200 baud (high) */ + store(0x03, DLCR) /* word=8 stop=1 parity=none */ + store(0x03, CMCR) /* DTR=1 RTS=1 Out2=Off Loop=Off */ + store(0x00, CDLM) /* turn off interrupts */ +} + +/* +* THRE +* Wait for COM port transmitter holding register to go empty +*/ +Method(THRE) +{ + and(CLSR, 0x20, local0) + while (Lequal(local0, Zero)) { + and(CLSR, 0x20, local0) + } +} + +/* +* OUTX +* Send a single raw character +*/ +Method(OUTX, 1) +{ + THRE() + store(Arg0, CDAT) +} + +/* +* OUTC +* Send a single character, expanding LF into CR/LF +*/ +Method(OUTC, 1) +{ + if (LEqual(Arg0, 0x0a)) { + OUTX(0x0d) + } + OUTX(Arg0) +} + +/* +* DBGN +* Send a single hex nibble +*/ +Method(DBGN, 1) +{ + and(Arg0, 0x0f, Local0) + if (LLess(Local0, 10)) { + add(Local0, 0x30, Local0) + } else { + add(Local0, 0x37, Local0) + } + OUTC(Local0) +} + +/* +* DBGB +* Send a hex byte +*/ +Method(DBGB, 1) +{ + ShiftRight(Arg0, 4, Local0) + DBGN(Local0) + DBGN(Arg0) +} + +/* +* DBGW +* Send a hex word +*/ +Method(DBGW, 1) +{ + ShiftRight(Arg0, 8, Local0) + DBGB(Local0) + DBGB(Arg0) +} + +/* +* DBGD +* Send a hex Dword +*/ +Method(DBGD, 1) +{ + ShiftRight(Arg0, 16, Local0) + DBGW(Local0) + DBGW(Arg0) +} + +/* +* DBGO +* Send either a string or an integer +*/ +Method(DBGO, 1) +{ + /* DINI() */ + if (LEqual(ObjectType(Arg0), 1)) { + if (LGreater(Arg0, 0xffff)) { + DBGD(Arg0) + } else { + if (LGreater(Arg0, 0xff)) { + DBGW(Arg0) + } else { + DBGB(Arg0) + } + } + } else { + Name(BDBG, Buffer(80) {}) + store(Arg0, BDBG) + store(0, Local1) + while (One) { + store(GETC(BDBG, Local1), Local0) + if (LEqual(Local0, 0)) { + return (0) + } + OUTC(Local0) + Increment(Local1) + } + } + return (0) +} + +/* Get a char from a string */ +Method(GETC, 2) +{ + CreateByteField(Arg0, Arg1, DBGC) + return (DBGC) +} Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/event.asl Wed May 11 09:47:43 2011 (r6567) @@ -0,0 +1,316 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Supported sleep states: */ +Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ +Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ +Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ +Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ +Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ +Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + +Name(\_SB.CSPS ,0) /* Current Sleep State (S0, ... , S5) */ +Name(CSMS, 0) /* Current System State */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + \_SB.PCI0.SIOS (Arg0) +} /* End Method(\_PTS) */ + +/* +* The following method results in a "not a valid reserved NameSeg" +* warning so I have commented it out for the duration. It isn't +* used, so it could be removed. +* +* +* \_GTS OEM Going To Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +* +* Method(\_GTS, 1) { +* DBGO("\\_GTS\n") +* DBGO("From S0 to S") +* DBGO(Arg0) +* DBGO("\n") +* } +*/ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + \_SB.PCI0.SIOW (Arg0) + Return(WKST) +} /* End Method(\_WAK) */ + +Scope(\_GPE) { /* Start Scope GPE */ + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + Notify (\_TZ.TZ00, 0x80) + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event */ + /* SATA Hot Plug Support -> acpi/sata.asl */ +} /* End Scope GPE */ Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/globutil.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/globutil.asl Wed May 11 09:47:43 2011 (r6567) @@ -0,0 +1,218 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope(\_SB) { + #include "globutil.asl" +} +*/ + +/* string compare functions */ +Method(MIN, 2) +{ + if (LLess(Arg0, Arg1)) { + Return(Arg0) + } else { + Return(Arg1) + } +} + +Method(SLEN, 1) +{ + Store(Arg0, Local0) + Return(Sizeof(Local0)) +} + +Method(S2BF, 1) +{ + Add(SLEN(Arg0), One, Local0) + Name(BUFF, Buffer(Local0) {}) + Store(Arg0, BUFF) + Return(BUFF) +} + +/* Strong string compare. Checks both length and content */ +Method(SCMP, 2) +{ + Store(S2BF(Arg0), Local0) + Store(S2BF(Arg1), Local1) + Store(Zero, Local4) + Store(SLEN(Arg0), Local5) + Store(SLEN(Arg1), Local6) + Store(MIN(Local5, Local6), Local7) + + While(LLess(Local4, Local7)) { + Store(Derefof(Index(Local0, Local4)), Local2) + Store(Derefof(Index(Local1, Local4)), Local3) + if (LGreater(Local2, Local3)) { + Return(One) + } else { + if (LLess(Local2, Local3)) { + Return(Ones) + } + } + Increment(Local4) + } + if (LLess(Local4, Local5)) { + Return(One) + } else { + if (LLess(Local4, Local6)) { + Return(Ones) + } else { + Return(Zero) + } + } +} + +/* Weak string compare. Checks to find Arg1 at beginning of Arg0. +* Fails if length(Arg0) < length(Arg1). Returns 0 on Fail, 1 on +* Pass. +*/ +Method(WCMP, 2) +{ + Store(S2BF(Arg0), Local0) + Store(S2BF(Arg1), Local1) + if (LLess(SLEN(Arg0), SLEN(Arg1))) { + Return(0) + } + Store(Zero, Local2) + Store(SLEN(Arg1), Local3) + + While(LLess(Local2, Local3)) { + if (LNotEqual(Derefof(Index(Local0, Local2)), + Derefof(Index(Local1, Local2)))) { + Return(0) + } + Increment(Local2) + } + Return(One) +} + +/* ARG0 = IRQ Number(0-15) +* Returns Bit Map +*/ +Method(I2BM, 1) +{ + Store(0, Local0) + if (LNotEqual(ARG0, 0)) { + Store(1, Local1) + ShiftLeft(Local1, ARG0, Local0) + } + Return(Local0) +} +Method (SEQL, 2, Serialized) +{ + Store (SizeOf (Arg0), Local0) + Store (SizeOf (Arg1), Local1) + If (LNot (LEqual (Local0, Local1))) { Return (Zero) } + + Name (BUF0, Buffer (Local0) {}) + Store (Arg0, BUF0) + Name (BUF1, Buffer (Local0) {}) + Store (Arg1, BUF1) + Store (Zero, Local2) + While (LLess (Local2, Local0)) + { + Store (DerefOf (Index (BUF0, Local2)), Local3) + Store (DerefOf (Index (BUF1, Local2)), Local4) + If (LNot (LEqual (Local3, Local4))) { Return (Zero) } + + Increment (Local2) + } + + Return (One) +} + +/* GetMemoryResources(Node, Link) */ +Method (GMEM, 2, NotSerialized) +{ + Name (BUF0, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x00000000, // Address Range Minimum + 0x00000000, // Address Range Maximum + 0x00000000, // Address Translation Offset + 0x00000001,,, + , AddressRangeMemory, TypeStatic) + }) + CreateDWordField (BUF0, 0x0A, MMIN) + CreateDWordField (BUF0, 0x0E, MMAX) + CreateDWordField (BUF0, 0x16, MLEN) + Store (0x00, Local0) + Store (0x00, Local4) + Store (0x00, Local3) + While (LLess (Local0, 0x10)) + { + /* Get value of the first register */ + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1) + Increment (Local0) + Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2) + If (LEqual (And (Local1, 0x03), 0x03)) /* Pair enabled? */ + { + If (LEqual (Arg0, And (Local2, 0x07))) /* Node matches? */ + { + /* If Link Matches (or we got passed 0xFF) */ + If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04)))) + { + /* Extract the Base and Limit values */ + Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN) + Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX) + Or (MMAX, 0xFFFF, MMAX) + Subtract (MMAX, MMIN, MLEN) + Increment (MLEN) + + If (Local4) /* I've already done this once */ + { + Concatenate (RTAG (BUF0), Local3, Local5) + Store (Local5, Local3) + } + Else + { + Store (RTAG (BUF0), Local3) + } + + Increment (Local4) + } + } + } + + Increment (Local0) + } + + If (LNot (Local4)) /* No resources for this node and link. */ + { + Store (RTAG (BUF0), Local3) + } + + Return (Local3) +} + +Method (RTAG, 1, NotSerialized) +{ + Store (Arg0, Local0) + Store (SizeOf (Local0), Local1) + Subtract (Local1, 0x02, Local1) + Multiply (Local1, 0x08, Local1) + CreateField (Local0, 0x00, Local1, RETB) + Store (RETB, Local2) + Return (Local2) +} Modified: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl ============================================================================== --- trunk/src/mainboard/amd/dbm690t/acpi/ide.asl Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/ide.asl Wed May 11 09:47:43 2011 (r6567) @@ -50,18 +50,23 @@ 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ }) -OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ - Field(ICRG, AnyAcc, NoLock, Preserve) +OperationRegion(IDEC, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(IDEC, AnyAcc, NoLock, Preserve) { - PPTS, 8, /* Primary PIO Slave Timing */ - PPTM, 8, /* Primary PIO Master Timing */ - OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ - PMTM, 8, /* Primary MWDMA Master Timing */ - OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ - OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPTS, 8, /* 0x40: 0:7 Primary PIO Slave Timing */ + PPTM, 8, /* 0x40: 8:15 Primary PIO Master Timing */ + OFFSET(0x04), + PMTS, 8, /* 0x44: 0:7 Primary MWDMA Slave Timing */ + PMTM, 8, /* 0x44: 7:15 Primary MWDMA Master Timing */ + OFFSET(0x08), + PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), + PPMM, 4, /* Primary PIO master Mode */ PPSM, 4, /* Primary PIO slave Mode */ - OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ - OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + OFFSET(0x14), + PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), + PDMM, 4, /* Primary UltraDMA Mode */ PDSM, 4, /* Primary UltraDMA Mode */ } @@ -74,9 +79,9 @@ Return(Multiply(30, Add(Local0, Local1))) } -Device(PRID) +Device(PRIM) { - Name (_ADR, Zero) + Name (_ADR, 0) Method(_GTM, 0) { NAME(OTBF, Buffer(20) { /* out buffer */ @@ -206,7 +211,7 @@ } } /* End Device(MST) */ - Device(SLAV) + Device(SLV) { Name(_ADR, 1) Method(_GTF) { Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/platform.asl Wed May 11 09:47:43 2011 (r6567) @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(PCIF, 0) + +Method(_PIC, 1, NotSerialized) +{ + Store(Arg0, PCIF) + If (Arg0) + { + \_SB.PCI0.LPC0.CIRQ() + } +} + +External (\_PR.CPU0, DeviceObj) +External (\_PR.CPU1, DeviceObj) + +Scope(\_SB) +{ + + Method(_INI, 0) + { + Store (2000, OSYS) + + If (CondRefOf(_OSI, Local0)) { + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + } + } +} \ No newline at end of file Modified: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl ============================================================================== --- trunk/src/mainboard/amd/dbm690t/acpi/routing.asl Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/routing.asl Wed May 11 09:47:43 2011 (r6567) @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,112 +18,33 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 - ) - { - #include "routing.asl" - } -*/ - + /* Routing is in System Bus scope */ -Scope(\_SB) { +Scope(\_SB) +{ Name(PR0, Package(){ /* NB devices */ - /* Bus 0, Dev 0 - RS690 Host Controller */ - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, INTC, 0 }, - Package(){0x0002FFFF, 1, INTD, 0 }, - Package(){0x0002FFFF, 2, INTA, 0 }, - Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, INTA, 0 }, - Package(){0x0004FFFF, 1, INTB, 0 }, - Package(){0x0004FFFF, 2, INTC, 0 }, - Package(){0x0004FFFF, 3, INTD, 0 }, - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - /* Package(){0x0005FFFF, 0, INTB, 0 }, */ - /* Package(){0x0005FFFF, 1, INTC, 0 }, */ - /* Package(){0x0005FFFF, 2, INTD, 0 }, */ - /* Package(){0x0005FFFF, 3, INTA, 0 }, */ - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - /* SB devices */ - /* Bus 0, Dev 17 - SATA controller #2 */ /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0012FFFF, 1, INTA, 0 }, + Package(){0x0012FFFF, 1, \_SB.PCI0.LPC0.INTG, 0 }, /* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */ - Package(){0x0013FFFF, 0, INTA, 0 }, - Package(){0x0013FFFF, 1, INTB, 0 }, - Package(){0x0013FFFF, 2, INTC, 0 }, - Package(){0x0013FFFF, 3, INTD, 0 }, + Package(){0x0013FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 }, + Package(){0x0013FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 }, + Package(){0x0013FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 }, + Package(){0x0013FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 }, /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */ - Package(){0x0014FFFF, 0, INTA, 0 }, - Package(){0x0014FFFF, 1, INTB, 0 }, - Package(){0x0014FFFF, 2, INTC, 0 }, - Package(){0x0014FFFF, 3, INTD, 0 }, + Package(){0x0014FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 }, + Package(){0x0014FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 }, + Package(){0x0014FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 }, + Package(){0x0014FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 }, }) Name(APR0, Package(){ /* NB devices in APIC mode */ /* Bus 0, Dev 0 - RS690 Host Controller */ - - /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ - /* Package(){0x0001FFFF, 0, 0, 18 }, */ - /* package(){0x0001FFFF, 1, 0, 19 }, */ - - /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ - Package(){0x0002FFFF, 0, 0, 18 }, - /* Package(){0x0002FFFF, 1, 0, 19 }, */ - /* Package(){0x0002FFFF, 2, 0, 16 }, */ - /* Package(){0x0002FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ - Package(){0x0004FFFF, 0, 0, 16 }, - /* Package(){0x0004FFFF, 1, 0, 17 }, */ - /* Package(){0x0004FFFF, 2, 0, 18 }, */ - /* Package(){0x0004FFFF, 3, 0, 19 }, */ - - /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ - Package(){0x0005FFFF, 0, 0, 17 }, - /* Package(){0x0005FFFF, 1, 0, 18 }, */ - /* Package(){0x0005FFFF, 2, 0, 19 }, */ - /* Package(){0x0005FFFF, 3, 0, 16 }, */ - - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - /* Package(){0x0006FFFF, 1, 0, 19 }, */ - /* Package(){0x0006FFFF, 2, 0, 16 }, */ - /* Package(){0x0006FFFF, 3, 0, 17 }, */ - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - /* Package(){0x0007FFFF, 1, 0, 16 }, */ - /* Package(){0x0007FFFF, 2, 0, 17 }, */ - /* Package(){0x0007FFFF, 3, 0, 18 }, */ - - /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ - /* SB devices in APIC mode */ - /* Bus 0, Dev 17 - SATA controller #2 */ /* Bus 0, Dev 18 - SATA controller #1 */ Package(){0x0012FFFF, 0, 0, 22 }, @@ -130,42 +53,34 @@ Package(){0x0013FFFF, 1, 0, 17 }, Package(){0x0013FFFF, 2, 0, 18 }, Package(){0x0013FFFF, 3, 0, 19 }, - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */ - Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, Package(){0x0014FFFF, 2, 0, 18 }, Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ }) Name(PR1, Package(){ /* Internal graphics - RS690 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, + Package(){0x0005FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 }, + Package(){0x0005FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 }, + Package(){0x0005FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 }, + Package(){0x0005FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 }, }) Name(APR1, Package(){ /* Internal graphics - RS690 VGA, Bus1, Dev5 */ Package(){0x0005FFFF, 0, 0, 18 }, Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ }) Name(PS2, Package(){ /* The external GFX - Hooked to PCIe slot 2 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, + Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTC, 0 }, + Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTD, 0 }, + Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTA, 0 }, + Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTB, 0 }, }) Name(APS2, Package(){ @@ -178,10 +93,10 @@ Name(PS4, Package(){ /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, + Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTA, 0 }, + Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTB, 0 }, + Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTC, 0 }, + Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTD, 0 }, }) Name(APS4, Package(){ @@ -194,10 +109,10 @@ Name(PS5, Package(){ /* PCIe slot - Hooked to PCIe slot 5 */ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, + Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTB, 0 }, + Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTC, 0 }, + Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTD, 0 }, + Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTA, 0 }, }) Name(APS5, Package(){ @@ -210,10 +125,10 @@ Name(PS6, Package(){ /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, + Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTC, 0 }, + Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTD, 0 }, + Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTA, 0 }, + Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTB, 0 }, }) Name(APS6, Package(){ @@ -225,15 +140,15 @@ }) Name(PS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, + /* PCIe slot - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, \_SB.PCI0.LPC0.INTD, 0 }, + Package(){0x0000FFFF, 1, \_SB.PCI0.LPC0.INTA, 0 }, + Package(){0x0000FFFF, 2, \_SB.PCI0.LPC0.INTB, 0 }, + Package(){0x0000FFFF, 3, \_SB.PCI0.LPC0.INTC, 0 }, }) Name(APS7, Package(){ - /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + /* PCIe slot - Hooked to PCIe slot 7 */ Package(){0x0000FFFF, 0, 0, 19 }, Package(){0x0000FFFF, 1, 0, 16 }, Package(){0x0000FFFF, 2, 0, 17 }, @@ -241,18 +156,23 @@ }) Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, - Package(){0x0007FFFF, 0, 0, 0x16 }, - Package(){0x0007FFFF, 1, 0, 0x17 }, - Package(){0x0007FFFF, 2, 0, 0x14 }, - Package(){0x0007FFFF, 3, 0, 0x15 }, + /* PCI slots: slot 1 behind Dev14, Fun4. */ + Package(){0x005FFFF, 0, \_SB.PCI0.LPC0.INTF, 0 }, // Phoenix does it + Package(){0x005FFFF, 1, \_SB.PCI0.LPC0.INTG, 0 }, // Phoenix does it + Package(){0x004FFFF, 0, \_SB.PCI0.LPC0.INTE, 0 }, + Package(){0x004FFFF, 1, \_SB.PCI0.LPC0.INTF, 0 }, + Package(){0x004FFFF, 2, \_SB.PCI0.LPC0.INTG, 0 }, + Package(){0x004FFFF, 3, \_SB.PCI0.LPC0.INTH, 0 }, + }) + + Name(AP2P, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 21 }, // Phoenix does it + Package(){0x0005FFFF, 1, 0, 22 }, // Phoenix does it + Package(){0x0004FFFF, 0, 0, 20 }, + Package(){0x0004FFFF, 1, 0, 21 }, + Package(){0x0004FFFF, 2, 0, 22 }, + Package(){0x0004FFFF, 3, 0, 23 }, }) + } Modified: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/sata.asl ============================================================================== --- trunk/src/mainboard/amd/dbm690t/acpi/sata.asl Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/sata.asl Wed May 11 09:47:43 2011 (r6567) @@ -118,7 +118,7 @@ if (LGreater(\_SB.P0IS,0)) { sleep(32) } - Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + Notify(\_SB.PCI0.SATA.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ store(one, \_SB.P0PR) } @@ -126,7 +126,7 @@ if (LGreater(\_SB.P1IS,0)) { sleep(32) } - Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + Notify(\_SB.PCI0.SATA.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ store(one, \_SB.P1PR) } @@ -134,7 +134,7 @@ if (LGreater(\_SB.P2IS,0)) { sleep(32) } - Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + Notify(\_SB.PCI0.SATA.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ store(one, \_SB.P2PR) } @@ -142,8 +142,9 @@ if (LGreater(\_SB.P3IS,0)) { sleep(32) } - Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + Notify(\_SB.PCI0.SATA.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ store(one, \_SB.P3PR) } } } + Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/statdef.asl Wed May 11 09:47:43 2011 (r6567) @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* Status and notification definitions */ + +#define STA_MISSING 0x00 +#define STA_PRESENT 0x01 +#define STA_ENABLED 0x03 +#define STA_DISABLED 0x09 +#define STA_INVISIBLE 0x0B +#define STA_UNAVAILABLE 0x0D +#define STA_VISIBLE 0x0F + +/* SMBus status codes */ +#define SMB_OK 0x00 +#define SMB_UnknownFail 0x07 +#define SMB_DevAddrNAK 0x10 +#define SMB_DeviceError 0x11 +#define SMB_DevCmdDenied 0x12 +#define SMB_UnknownErr 0x13 +#define SMB_DevAccDenied 0x17 +#define SMB_Timeout 0x18 +#define SMB_HstUnsuppProtocol 0x19 +#define SMB_Busy 0x1A +#define SMB_PktChkError 0x1F + +/* Device Object Notification Values */ +#define NOTIFY_BUS_CHECK 0x00 +#define NOTIFY_DEVICE_CHECK 0x01 +#define NOTIFY_DEVICE_WAKE 0x02 +#define NOTIFY_EJECT_REQUEST 0x03 +#define NOTIFY_DEVICE_CHECK_JR 0x04 +#define NOTIFY_FREQUENCY_ERROR 0x05 +#define NOTIFY_BUS_MODE 0x06 +#define NOTIFY_POWER_FAULT 0x07 +#define NOTIFY_CAPABILITIES 0x08 +#define NOTIFY_PLD_CHECK 0x09 +#define NOTIFY_SLIT_UPDATE 0x0B + +/* Battery Device Notification Values */ +#define NOTIFY_BAT_STATUSCHG 0x80 +#define NOTIFY_BAT_INFOCHG 0x81 +#define NOTIFY_BAT_MAINTDATA 0x82 + +/* Power Source Object Notification Values */ +#define NOTIFY_PWR_STATUSCHG 0x80 + +/* Thermal Zone Object Notification Values */ +#define NOTIFY_TZ_STATUSCHG 0x80 +#define NOTIFY_TZ_TRIPPTCHG 0x81 +#define NOTIFY_TZ_DEVLISTCHG 0x82 +#define NOTIFY_TZ_RELTBLCHG 0x83 + +/* Power Button Notification Values */ +#define NOTIFY_POWER_BUTTON 0x80 + +/* Sleep Button Notification Values */ +#define NOTIFY_SLEEP_BUTTON 0x80 + +/* Lid Notification Values */ +#define NOTIFY_LID_STATUSCHG 0x80 + +/* Processor Device Notification Values */ +#define NOTIFY_CPU_PPCCHG 0x80 +#define NOTIFY_CPU_CSTATECHG 0x81 +#define NOTIFY_CPU_THROTLCHG 0x82 + +/* User Presence Device Notification Values */ +#define NOTIFY_USR_PRESNCECHG 0x80 + +/* Battery Device Notification Values */ +#define NOTIFY_ALS_ILLUMCHG 0x80 +#define NOTIFY_ALS_COLORTMPCHG 0x81 +#define NOTIFY_ALS_RESPCHG 0x82 + + Added: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/thermal.asl Wed May 11 09:47:43 2011 (r6567) @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +/* THERMAL */ +Scope(\_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ + Return(Package() {\_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ + } + } + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CPU0, \_PR.CPU1}) + } + Return (Package() {\_PR.CPU0}) + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ +} \ No newline at end of file Modified: trunk/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl ============================================================================== --- trunk/src/mainboard/amd/dbm690t/acpi/usb.asl Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi/usb.asl Wed May 11 09:47:43 2011 (r6567) @@ -18,13 +18,6 @@ */ /* simple name description */ -/* -DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 - ) - { - #include "usb.asl" - } -*/ Method(UCOC, 0) { Sleep(20) Store(0x13,CMTI) @@ -38,7 +31,7 @@ UCOC() if(LEqual(GPB0,PLC0)) { Not(PLC0,PLC0) - Store(PLC0, \_SB.PT0D) + Store(PLC0, \_SB_.PT0D) } } } @@ -51,7 +44,7 @@ UCOC() if (LEqual(GPB1,PLC1)) { Not(PLC1,PLC1) - Store(PLC1, \_SB.PT1D) + Store(PLC1, \_SB_.PT1D) } } } @@ -64,7 +57,7 @@ UCOC() if (LEqual(GPB2,PLC2)) { Not(PLC2,PLC2) - Store(PLC2, \_SB.PT2D) + Store(PLC2, \_SB_.PT2D) } } } @@ -77,7 +70,7 @@ UCOC() if (LEqual(GPB3,PLC3)) { Not(PLC3,PLC3) - Store(PLC3, \_SB.PT3D) + Store(PLC3, \_SB_.PT3D) } } } @@ -90,7 +83,7 @@ UCOC() if (LEqual(GPB4,PLC4)) { Not(PLC4,PLC4) - Store(PLC4, \_SB.PT4D) + Store(PLC4, \_SB_.PT4D) } } } @@ -103,7 +96,7 @@ UCOC() if (LEqual(GPB5,PLC5)) { Not(PLC5,PLC5) - Store(PLC5, \_SB.PT5D) + Store(PLC5, \_SB_.PT5D) } } } @@ -117,7 +110,7 @@ UCOC() if (LEqual(GPB6,PLC6)) { Not(PLC6,PLC6) - Store(PLC6, \_SB.PT6D) + Store(PLC6, \_SB_.PT6D) } } } @@ -131,7 +124,7 @@ UCOC() if (LEqual(GPB7,PLC7)) { Not(PLC7,PLC7) - Store(PLC7, \_SB.PT7D) + Store(PLC7, \_SB_.PT7D) } } } @@ -143,7 +136,7 @@ Method (_L17) { if (LEqual(G8IS,PLC8)) { Not(PLC8,PLC8) - Store(PLC8, \_SB.PT8D) + Store(PLC8, \_SB_.PT8D) } } } @@ -154,7 +147,7 @@ Scope (\_GPE) { Method (_L0E) { if (LEqual(G9IS,0)) { - Store(1,\_SB.PT9D) + Store(1,\_SB_.PT9D) } } } Modified: trunk/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/acpi_tables.c Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c Wed May 11 09:47:43 2011 (r6567) @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,19 +23,25 @@ #include <string.h> #include <arch/acpi.h> #include <arch/ioapic.h> +#include <arch/smp/mpspec.h> #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> -#include "northbridge/amd/amdk8/acpi.h" +#include <../../../northbridge/amd/amdk8/acpi.h> #include <arch/cpu.h> #include <cpu/amd/model_fxx_powernow.h> - -extern u16 pm_base; +#include <southbridge/amd/rs690/rs690.h> #define DUMP_ACPI_TABLES 0 +#ifndef CONFIG_LINT01_CONVERSION +#define CONFIG_LINT01_CONVERSION 1 +#endif + +extern u16 pm_base; + /* * Assume the max pstate number is 8 * 0x21(33 bytes) is one package length of _PSS package @@ -41,11 +49,67 @@ #define Maxpstate 8 #define Defpkglength 0x21 +#define GLOBAL_VARS_SIZE 0x100 + +typedef struct { + /* Miscellaneous */ + u16 osys; + u16 linx; + u32 pcba; + u8 mpen; + u8 reserv[247]; +} __attribute__((packed)) global_vars_t; + +static void acpi_write_gvars(global_vars_t *gvars) +{ + device_t dev; + struct resource *res; + + memset((void *)gvars, 0, GLOBAL_VARS_SIZE); + + gvars->pcba = EXT_CONF_BASE_ADDRESS; + dev = dev_find_slot(0, PCI_DEVFN(0,0)); + res = probe_resource(dev, 0x1C); + if( res ) + gvars->pcba = res->base; + + gvars->mpen = 1; +} + +static void acpi_create_my_hpet(acpi_hpet_t *hpet) +{ +#define HPET_ADDR 0xfed00000ULL + acpi_header_t *header=&(hpet->header); + acpi_addr_t *addr=&(hpet->addr); + + memset((void *)hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = HPET_ADDR & 0xffffffff; + addr->addrh = HPET_ADDR >> 32; + + hpet->id = 0x43538301; + hpet->number = 0; + hpet->min_tick = 20; + + header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); +} #if DUMP_ACPI_TABLES == 1 static void dump_mem(u32 start, u32 end) { - u32 i; print_debug("dump_mem:"); for (i = start; i < end; i++) { @@ -62,7 +126,17 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - /* Just a dummy */ + struct resource *res; + resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default + + device_t dev = dev_find_slot(0,PCI_DEVFN(0,0)); + // we report mmconf base + res = probe_resource(dev, 0x1C); + if( res ) + mmconf_base = res->base; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ? + return current; } @@ -74,20 +148,23 @@ /* Write SB600 IOAPIC, only one */ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); - +#if CONFIG_LINT01_CONVERSION == 0 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); +#else + /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ /* 5 mean: 0101 --> Edige-triggered, Active high */ /* create all subtables for processors */ - /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + current = acpi_create_madt_lapic_nmis(current, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); /* 1: LINT1 connect to NMI */ - + set_nbcfg_enable_bits(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x68, 1 << 16, 1 << 16); // Local Interrupt Conversion Enable +#endif return current; } @@ -97,99 +174,126 @@ return (unsigned long) (acpigen_get_current()); } +#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10) + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; + int i; + acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt; + acpi_srat_t *srat; + acpi_xsdt_t *xsdt; + acpi_mcfg_t *mcfg; acpi_hpet_t *hpet; acpi_madt_t *madt; acpi_fadt_t *fadt; acpi_facs_t *facs; acpi_header_t *dsdt; acpi_header_t *ssdt; - + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ /* Align ACPI tables to 16byte */ - start = (start + 0x0f) & -0x10; current = start; + ALIGN_CURRENT; printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); /* We need at least an RSDP and an RSDT Table */ rsdp = (acpi_rsdp_t *) current; current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; rsdt = (acpi_rsdt_t *) current; current += sizeof(acpi_rsdt_t); - + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + /* clear all table memory */ memset((void *)start, 0, current - start); - acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdp(rsdp, rsdt, xsdt); acpi_write_rsdt(rsdt); - + acpi_write_xsdt(xsdt); /* * We explicitly add these tables later on: */ - /* If we want to use HPET Timers Linux wants an MADT */ + current = ALIGN(current, 64); + /* FACS */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + acpi_create_facs(facs); + current += sizeof(acpi_facs_t); + + /* HPET */ printk(BIOS_DEBUG, "ACPI: * HPET\n"); hpet = (acpi_hpet_t *) current; + acpi_create_my_hpet(hpet); current += sizeof(acpi_hpet_t); - acpi_create_hpet(hpet); acpi_add_table(rsdp, hpet); - + + /* If we want to use HPET Timers Linux wants an MADT */ printk(BIOS_DEBUG, "ACPI: * MADT\n"); madt = (acpi_madt_t *) current; acpi_create_madt(madt); current += madt->header.length; acpi_add_table(rsdp, madt); + /* MCFG */ + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + /* SSDT */ printk(BIOS_DEBUG, "ACPI: * SSDT\n"); ssdt = (acpi_header_t *)current; - - acpi_create_ssdt_generator(ssdt, "DYNADATA"); + acpi_create_ssdt_generator(ssdt, "COREBOOT"); current += ssdt->length; - acpi_add_table(rsdp, ssdt); - - /* FACS */ - printk(BIOS_DEBUG, "ACPI: * FACS\n"); - facs = (acpi_facs_t *) current; - current += sizeof(acpi_facs_t); - acpi_create_facs(facs); - + acpi_add_table(rsdp, ssdt); + /* DSDT */ printk(BIOS_DEBUG, "ACPI: * DSDT\n"); dsdt = (acpi_header_t *)current; memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); current += dsdt->length; memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); + + /* Pack gvars into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xBADEAFFE) { + printk(BIOS_DEBUG, "ACPI: Patching up globals in DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; + break; + } + } + + /* And fill it */ + acpi_write_gvars((global_vars_t *)current); + current += GLOBAL_VARS_SIZE; + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); + /* FADT */ printk(BIOS_DEBUG, "ACPI: * FADT\n"); fadt = (acpi_fadt_t *) current; current += sizeof(acpi_fadt_t); - acpi_create_fadt(fadt, facs, dsdt); acpi_add_table(rsdp, fadt); -#if DUMP_ACPI_TABLES == 1 - printk(BIOS_DEBUG, "rsdp\n"); - dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); - - printk(BIOS_DEBUG, "rsdt\n"); - dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + /* SRAT */ + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + acpi_add_table(rsdp, srat); - printk(BIOS_DEBUG, "madt\n"); - dump_mem(madt, ((void *)madt) + madt->header.length); - - printk(BIOS_DEBUG, "ssdt\n"); - dump_mem(ssdt, ((void *)ssdt) + ssdt->length); - - printk(BIOS_DEBUG, "fadt\n"); - dump_mem(fadt, ((void *)fadt) + fadt->header.length); -#endif + printk(BIOS_DEBUG, "current = %lx\n", current); printk(BIOS_INFO, "ACPI: done.\n"); return current; Modified: trunk/src/mainboard/siemens/sitemp_g1p1/chip.h ============================================================================== --- trunk/src/mainboard/amd/dbm690t/chip.h Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/chip.h Wed May 11 09:47:43 2011 (r6567) @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,4 +20,10 @@ */ extern struct chip_operations mainboard_ops; -struct mainboard_config {}; + +struct mainboard_config +{ + u32 uma_size; /* How many UMA should be used in memory for TOP. */ + unsigned int plx_present : 1; +}; + Modified: trunk/src/mainboard/siemens/sitemp_g1p1/cmos.layout ============================================================================== --- trunk/src/mainboard/amd/dbm690t/cmos.layout Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/cmos.layout Wed May 11 09:47:43 2011 (r6567) @@ -2,6 +2,8 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2008 Advanced Micro Devices, Inc. +## Copyright (C) 2010 Siemens AG, Inc. +## (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -32,9 +34,11 @@ #56 8 r 0 day_of_month #64 8 r 0 month #72 8 r 0 year +# ======================================================= #80 4 r 0 rate_select #84 3 r 0 REF_Clock #87 1 r 0 UIP +# ======================================================= #88 1 r 0 auto_switch_DST #89 1 r 0 24_hour_mode #90 1 r 0 binary_values_enable @@ -43,28 +47,44 @@ #93 1 r 0 alarm_interrupt_enable #94 1 r 0 periodic_interrupt_enable #95 1 r 0 disable_clock_updates +# ======================================================== #96 288 r 0 temporary_filler 0 384 r 0 reserved_memory -384 1 e 4 boot_option -385 1 e 4 last_boot -386 1 e 1 ECC_memory +# ======================================================== +#384 1 e 4 unused +385 1 r 4 last_boot +#386 1 r 1 unused +387 1 e 16 cmos_defaults_loaded 388 4 r 0 reboot_bits 392 3 e 5 baud_rate -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock +#395 1 r 1 unused +#396 1 r 1 unused +#397 2 r 8 unused 399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data +#400 8 r 18 reserved +408 4 e 6 debug_level +412 1 e 1 power_on_after_fail +#413 1 r 1 unused +414 1 e 17 sata_mode +415 1 e 1 nmi +416 1 e 1 cpu_fan_control +417 1 e 1 chassis_fan_control +418 1 e 13 cpu_fan_polarity +419 1 e 13 chassis_fan_polarity +420 4 e 14 cpu_t_min +424 4 e 14 cpu_t_max +428 4 e 15 cpu_dutycycle_min +432 4 e 15 cpu_dutycycle_max +436 4 e 14 chassis_t_min +440 4 e 14 chassis_t_max +444 4 e 15 chassis_dutycycle_min +448 4 e 15 chassis_dutycycle_max +#452 4 r 9 unused +456 4 e 10 boot_delay +460 4 e 11 lcd_panel_id +#=========================================================== +464 512 s 0 boot_devices +976 8 h 0 boot_default 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved @@ -88,30 +108,100 @@ 5 5 4800 5 6 2400 5 7 1200 -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +#7 0 Network +#7 1 HDD +#7 2 Floppy +#7 8 Fallback_Network +#7 9 Fallback_HDD +#7 10 Fallback_Floppy #7 3 ROM 8 0 DDR400 8 1 DDR333 8 2 DDR266 8 3 DDR200 -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% - +# boot delay +10 0 off +10 1 1s +10 2 2s +10 3 3s +10 4 4s +10 5 5s +10 6 6s +10 7 7s +10 8 8s +10 9 9s +10 10 10s +# LCD Panel ID +11 0 no_panel +11 1 1024x768_65MHz_Dual +11 2 1920x1200_162MHz +11 3 1600x1200_162MHz +11 4 1024x768_65MHz +11 5 1400x1050_108MHz +11 6 1680x1050_119MHz +11 7 2048x1536_164MHz +11 8 1280x1024_108MHz +11 9 1366x768_86MHz_chimei_V32B1L01 +# TV Standard +#12 0 NTSC +#12 1 PAL +#12 2 PALM +#12 3 PAL60 +#12 4 NTSCJ +#12 5 PALCN +#12 6 PALN +#12 9 SCART-RGB +#12 15 no_tv +# CPU/Chassis FAN Control: polarity +13 0 Active_high +13 1 Active_low +# Temperature �C +14 0 30 +14 1 35 +14 2 40 +14 3 45 +14 4 50 +14 5 55 +14 6 60 +14 7 65 +14 8 70 +14 9 75 +14 10 80 +14 11 85 +14 12 90 +14 13 95 +14 14 100 +# Dutycycle % +15 0 25% +15 1 30% +15 2 35% +15 3 40% +15 4 45% +15 5 50% +15 6 55% +15 7 60% +15 8 65% +15 9 70% +15 10 75% +15 11 80% +15 12 85% +15 13 90% +15 14 95% +15 15 100% +# cmos_defaults_loaded +16 0 No +16 1 Yes +# sata_mode +17 0 AHCI +17 1 IDE +# reserved +18 32 2000 +# ============================== checksums checksum 392 983 984 Modified: trunk/src/mainboard/siemens/sitemp_g1p1/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/dbm690t/devicetree.cb Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/devicetree.cb Wed May 11 09:47:43 2011 (r6567) @@ -15,30 +15,41 @@ end end device pci_domain 0 on - subsystemid 0x1022 0x3050 inherit + subsystemid 0x110a 0x4076 inherit chip northbridge/amd/amdk8 device pci 18.0 on # southbridge chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 + device pci 0.0 on # Northbridge configuration space (0x7910) + end device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F + device pci 5.0 on # Internal Graphics 0x791F + end + device pci 5.2 on # + end + end + device pci 2.0 on # PCIE P2P bridge 0x7913 (external GFX-port0) + end + device pci 3.0 off # PCIE P2P bridge 0x791b (external GFX-port1) + end + device pci 4.0 on # PCIE P2P bridge port 0 (0x7914) + end + device pci 5.0 on # PCIE P2P bridge port 1 (0x7915) + end + device pci 6.0 on # PCIE P2P bridge port 2 (0x7916) + end + device pci 7.0 on # PCIE P2P bridge port 3 (0x7917) + end + device pci 8.0 off # NB/SB Link P2P bridge end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" register "gfx_dual_slot" = "0" register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" + register "gfx_tmds" = "1" # needed for DVI output, but this results in a conflict if PLX installed ! register "gfx_compliance" = "0" register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" + register "gfx_link_width" = "0" # 4 (0x8) if PLX installed end chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus device pci 12.0 on end # SATA 0x4380 @@ -48,7 +59,7 @@ device pci 13.3 on end # USB 0x438a device pci 13.4 on end # USB 0x438b device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 + device pci 14.0 on # SM 0x4385 chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end @@ -75,7 +86,7 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 off # Com2 + device pnp 2e.2 on # Com2 io 0x60 = 0x2f8 irq 0x70 = 3 end @@ -107,7 +118,9 @@ device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # ACI 0x4382 device pci 14.6 on end # MCI 0x438e - register "hda_viddid" = "0x10ec0882" +# register "ide0_enable" = "1" +# register "sata0_enable" = "1" + register "hda_viddid" = "0x10ec0882" end #southbridge/amd/sb600 end # device pci 18.0 Modified: trunk/src/mainboard/siemens/sitemp_g1p1/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/dbm690t/dsdt.asl Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/dsdt.asl Wed May 11 09:47:43 2011 (r6567) @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,30 +19,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* DefinitionBlock Statement */ -DefinitionBlock ( - "DSDT.AML", /* Output filename */ - "DSDT", /* Signature */ - 0x02, /* DSDT Revision, needs to be 2 for 64bit */ - "AMD ", /* OEMID */ - "DBM690T ", /* TABLE ID */ - 0x00010001 /* OEM Revision */ - ) -{ /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ - +DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005) +{ /* Data to be patched by the BIOS during POST */ - /* FIXME the patching is not done yet! */ /* Memory related values */ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ - Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ - Name(PBLN, 0x0) /* Length of BIOS area */ - - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ - Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ - /* USB overcurrent mapping pins. */ Name(UOM0, 0) Name(UOM1, 2) @@ -52,11 +37,9 @@ Name(UOM7, 2) Name(UOM8, 6) Name(UOM9, 6) - - /* Some global data */ - Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ - Name(OSV, Ones) /* Assume nothing */ - Name(PMOD, One) /* Assume APIC */ + + Name(DSEN, 1) // Display Output Switching Enable + // Power notification /* PIC IRQ mapping registers, C00h-C01h */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) @@ -69,11 +52,8 @@ PINB, 0x00000008, /* Index 1 */ PINC, 0x00000008, /* Index 2 */ PIND, 0x00000008, /* Index 3 */ - AINT, 0x00000008, /* Index 4 */ - SINT, 0x00000008, /* Index 5 */ - , 0x00000008, /* Index 6 */ - AAUD, 0x00000008, /* Index 7 */ - AMOD, 0x00000008, /* Index 8 */ + SINT, 0x00000008, /* Index 4 */ + Offset(0x09), PINE, 0x00000008, /* Index 9 */ PINF, 0x00000008, /* Index A */ PING, 0x00000008, /* Index B */ @@ -263,16 +243,26 @@ PWDA, 1, } - Scope(\_SB) { + OperationRegion (GVAR, SystemMemory, 0xBADEAFFE, 0x100) + Field (GVAR, ByteAcc, NoLock, Preserve) + { + Offset (0x00), + OSYS, 16, + LINX, 16, + PCBA, 32, + MPEN, 8 + } + + Name (IOLM,0xe0000000) + +#include "acpi/platform.asl" + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x2000000) /* PCIe reserved space for 31 busses */ Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ + Offset(0x00090024), /* Byte offset to SATA BAR5 register 24h - Bus 0, Device 18, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1, @@ -296,9 +286,9 @@ ,14, P92E, 1, /* Port92 decode enable */ } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve) + + OperationRegion(BAR5, SystemMemory, STB5, 0x1000) + Field(BAR5, AnyAcc, NoLock, Preserve) { /* Port 0 */ Offset(0x120), /* Port 0 Task file status */ @@ -369,794 +359,113 @@ P3PR, 1, } } - - #include "acpi/routing.asl" - - Scope(\_SB) { - - Method(CkOT, 0){ - - if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ - - if(CondRefOf(\_OSI,Local1)) - { - Store(1, OSTP) /* Assume some form of XP */ - if (\_OSI("Windows 2006")) /* Vista */ - { - Store(2, OSTP) - } - } else { - If(WCMP(\_OS,"Linux")) { - Store(3, OSTP) /* Linux */ - } Else { - Store(4, OSTP) /* Gotta be WinCE */ - } - } - Return(OSTP) - } - - Method(_PIC, 0x01, NotSerialized) - { - If (Arg0) - { - \_SB.CIRQ() - } - Store(Arg0, PMOD) - } - - Method(CIRQ, 0x00, NotSerialized) - { - Store(0, PINA) - Store(0, PINB) - Store(0, PINC) - Store(0, PIND) - Store(0, PINE) - Store(0, PINF) - Store(0, PING) - Store(0, PINH) - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PINA) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - Store(0, PINA) - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINA, IRQN) - Return(IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINA) - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PINB) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - Store(0, PINB) - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINB, IRQN) - Return(IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINB) - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PINC) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - Store(0, PINC) - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINC, IRQN) - Return(IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINC) - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIND) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - Store(0, PIND) - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PIND, IRQN) - Return(IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PIND) - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PINE) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - Store(0, PINE) - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINE, IRQN) - Return(IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINE) - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PINF) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - Store(0, PINF) - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return(PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINF, IRQN) - Return(IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINF) - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PING) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - Store(0, PING) - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PING, IRQN) - Return(IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PING) - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PINH) { - Return(0x0B) /* sata is invisible */ - } else { - Return(0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - Store(0, PINH) - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - ShiftLeft(1, PINH, IRQN) - Return(IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Decrement(Local0) - } - Store(Local0, PINH) - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ - - - /* Supported sleep states: */ - Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ - - If (LAnd(SSFG, 0x01)) { - Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ - } - If (LAnd(SSFG, 0x02)) { - Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ - } - If (LAnd(SSFG, 0x04)) { - Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ - } - If (LAnd(SSFG, 0x08)) { - Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ - } - - Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ - - Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ - Name(CSMS, 0) /* Current System State */ - - /* Wake status package */ - Name(WKST,Package(){Zero, Zero}) - - /* - * \_PTS - Prepare to Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2, etc - * - * Exit: - * -none- - * - * The _PTS control method is executed at the beginning of the sleep process - * for S1-S5. The sleeping value is passed to the _PTS control method. This - * control method may be executed a relatively long time before entering the - * sleep state and the OS may abort the operation without notification to - * the ACPI driver. This method cannot modify the configuration or power - * state of any device in the system. - */ - Method(\_PTS, 1) { - /* DBGO("\\_PTS\n") */ - /* DBGO("From S0 to S") */ - /* DBGO(Arg0) */ - /* DBGO("\n") */ - - /* Don't allow PCIRST# to reset USB */ - if (LEqual(Arg0,3)){ - Store(0,URRE) - } - - /* Clear sleep SMI status flag and enable sleep SMI trap. */ - /*Store(One, CSSM) - Store(One, SSEN)*/ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) - *} - */ - - /* Clear wake status structure. */ - Store(0, Index(WKST,0)) - Store(0, Index(WKST,1)) - \_SB.PCI0.SIOS (Arg0) - } /* End Method(\_PTS) */ - - /* - * The following method results in a "not a valid reserved NameSeg" - * warning so I have commented it out for the duration. It isn't - * used, so it could be removed. - * - * - * \_GTS OEM Going To Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - * - * Method(\_GTS, 1) { - * DBGO("\\_GTS\n") - * DBGO("From S0 to S") - * DBGO(Arg0) - * DBGO("\n") - * } - */ - - /* - * \_BFS OEM Back From Sleep method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * -none- - */ - Method(\_BFS, 1) { - /* DBGO("\\_BFS\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - } - - /* - * \_WAK System Wake method - * - * Entry: - * Arg0=The value of the sleeping state S1=1, S2=2 - * - * Exit: - * Return package of 2 DWords - * Dword 1 - Status - * 0x00000000 wake succeeded - * 0x00000001 Wake was signaled but failed due to lack of power - * 0x00000002 Wake was signaled but failed due to thermal condition - * Dword 2 - Power Supply state - * if non-zero the effective S-state the power supply entered - */ - Method(\_WAK, 1) { - /* DBGO("\\_WAK\n") */ - /* DBGO("From S") */ - /* DBGO(Arg0) */ - /* DBGO(" to S0\n") */ - - /* Re-enable HPET */ - Store(1,HPDE) - - /* Restore PCIRST# so it resets USB */ - if (LEqual(Arg0,3)){ - Store(1,URRE) - } - - /* Arbitrarily clear PciExpWakeStatus */ - Store(PWST, PWST) - - /* if(DeRefOf(Index(WKST,0))) { - * Store(0, Index(WKST,1)) - * } else { - * Store(Arg0, Index(WKST,1)) - * } - */ - \_SB.PCI0.SIOW (Arg0) - Return(WKST) - } /* End Method(\_WAK) */ - - Scope(\_GPE) { /* Start Scope GPE */ - /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 3 */ - Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ - - /* Legacy PM event */ - Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ - } - - /* Temp warning (TWarn) event */ - Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ - Notify (\_TZ.TZ00, 0x80) - } - - /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ - - /* USB controller PME# */ - Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ - - /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ - - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ - - /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ - - /* ExtEvent0 SCI event */ - Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ - } - - - /* ExtEvent1 SCI event */ - Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ - } - - /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ - - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ - - /* GPIO0 or GEvent8 event */ - Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ - - /* Azalia SCI event */ - Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ - Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ - } - - /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ - - /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ - - /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ - - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ - - } /* End Scope GPE */ - - #include "acpi/usb.asl" +#include "acpi/event.asl" +#include "acpi/routing.asl" +#include "acpi/usb.asl" /* South Bridge */ - Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + Scope(\_SB) + { + /* Start \_SB scope */ + +#include "acpi/globutil.asl" + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ - Device(PCI0) { + Device(PCI0) + { + External (MMIO) External (TOM1) - External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ + External (TOM2) + Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ Return(0) - } + } + Method(_STA, 0) { /* DBGO("\\_SB\\PCI0\\_STA\n") */ Return(0x0B) /* Status is visible */ } + + Device (MEMR) + { + Name (_HID, EisaId ("PNP0C02")) + Name (MEM1, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00000000, // Address Base + 0x00000000, // Address Length + _Y1A) + Memory32Fixed (ReadWrite, + 0x00000000, // Address Base + 0x00000000, // Address Length + _Y1B) + }) + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._BAS, MB01) + CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._LEN, ML01) + CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._BAS, MB02) + CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02) + If (PCIF) + { + Store (0xFEC00000, MB01) + Store (0xFEE00000, MB02) + Store (0x1000, ML01) + Store (0x1000, ML02) + } + + Return (MEM1) + } + } Method(_PRT,0) { - If(PMOD){ Return(APR0) } /* APIC mode */ + If(PCIF){ Return(APR0) } /* APIC mode */ Return (PR0) /* PIC Mode */ } /* end _PRT */ - + + OperationRegion (BAR1, PCI_Config, 0x14, 0x04) + Field (BAR1, ByteAcc, NoLock, Preserve) + { + Z009, 32 + } + /* Describe the Northbridge devices */ Device(AMRT) { Name(_ADR, 0x00000000) } /* end AMRT */ - + /* The internal GFX bridge */ Device(AGPB) { Name(_ADR, 0x00010000) Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - Return (APR1) - } + Method(_PRT,0) { Return (APR1) } + + Device (VGA) + { + Name (_ADR, 0x00050000) + Method (_DOS, 1) + { + /* Windows 2000 and Windows XP call _DOS to enable/disable + * Display Output Switching during init and while a switch + * is already active + */ + Store (And(Arg0, 7), DSEN) + } + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + } } /* end AGPB */ /* The external GFX bridge */ @@ -1164,18 +473,18 @@ Name(_ADR, 0x00020000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS2) } /* APIC mode */ + If(PCIF){ Return(APS2) } /* APIC mode */ Return (PS2) /* PIC Mode */ } /* end _PRT */ } /* end PBR2 */ - /* Dev3 is also an external GFX bridge, not used in Herring */ + /* Dev3 is also an external GFX bridge */ Device(PBR4) { Name(_ADR, 0x00040000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS4) } /* APIC mode */ + If(PCIF){ Return(APS4) } /* APIC mode */ Return (PS4) /* PIC Mode */ } /* end _PRT */ } /* end PBR4 */ @@ -1184,8 +493,8 @@ Name(_ADR, 0x00050000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ + If(PCIF){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ } /* end _PRT */ } /* end PBR5 */ @@ -1193,7 +502,7 @@ Name(_ADR, 0x00060000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS6) } /* APIC mode */ + If(PCIF){ Return(APS6) } /* APIC mode */ Return (PS6) /* PIC Mode */ } /* end _PRT */ } /* end PBR6 */ @@ -1203,27 +512,26 @@ Name(_ADR, 0x00070000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - If(PMOD){ Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ + If(PCIF){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ - - /* PCI slot 1, 2, 3 */ + /* PCI slot 1 */ Device(PIBR) { Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - + Name(_PRW, Package() {4, 5}) // Phoenix doeas it so Method(_PRT, 0) { - Return (PCIB) + If(PCIF){ Return(AP2P) } /* APIC Mode */ + Return (PCIB) /* PIC Mode */ } } /* Describe the Southbridge devices */ - Device(STCR) { + Device(SATA) { Name(_ADR, 0x00120000) - #include "acpi/sata.asl" - } /* end STCR */ +#include "acpi/sata.asl" + } /* end SATA */ Device(UOH1) { Name(_ADR, 0x00130000) @@ -1292,7 +600,7 @@ } Method(_INI) { - If(LEqual(OSTP,3)){ /* If we are running Linux */ + If(LEqual(LINX,1)){ /* If we are running Linux */ Store(zero, NSEN) Store(one, NSDO) Store(one, NSDI) @@ -1300,18 +608,350 @@ } } /* end AZHD */ - Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ + Device(LPC0) + { + Name (_ADR, 0x00140003) + Mutex (PSMX, 0x00) + + /* PIC IRQ mapping registers, C00h-C01h */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PINA, 0x00000008, /* Index 0 */ + PINB, 0x00000008, /* Index 1 */ + PINC, 0x00000008, /* Index 2 */ + PIND, 0x00000008, /* Index 3 */ + SINT, 0x00000008, /* Index 4 */ + Offset(0x09), + PINE, 0x00000008, /* Index 9 */ + PINF, 0x00000008, /* Index A */ + PING, 0x00000008, /* Index B */ + PINH, 0x00000008, /* Index C */ + } + + Method(CIRQ, 0x00, NotSerialized) + { + Store(0, PINA) + Store(0, PINB) + Store(0, PINC) + Store(0, PIND) + Store(0, SINT) + Store(0, PINE) + Store(0, PINF) + Store(0, PING) + Store(0, PINH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){10,11} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PINA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + Store(0, PINA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + Return(IRQB) // Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + Store (IRQB, Local0) // + CreateWordField(Local0, 0x1, IRQ0) + ShiftLeft(1, PINA, IRQ0) + Return(Local0) + } /* Method(_SB.INTA._CRS) */ + Method(_SRS, 1) { + CreateWordField(ARG0, 1, IRQ0) + /* Use lowest available IRQ */ + FindSetRightBit(IRQ0, Local0) + Decrement (Local0) + Store(Local0, PINA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PINB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + Store(0, PINB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + Return(IRQB) // Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + Store (IRQB, Local0) // {10,11} + CreateWordField(Local0, 0x1, IRQ0) + ShiftLeft(1, PINB, IRQ0) + Return(Local0) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + CreateWordField(ARG0, 1, IRQ0) + /* Use lowest available IRQ */ + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PINB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PINC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + Store(0, PINC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + Return(IRQB) // Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + Store (IRQB, Local0) // {10,11} + CreateWordField(Local0, 0x1, IRQ0) + ShiftLeft(1, PINC, IRQ0) + Return(Local0) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + CreateWordField(ARG0, 1, IRQ0) + /* Use lowest available IRQ */ + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PINC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIND) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + Store(0, PIND) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + Return(IRQB) // Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + Store (IRQB, Local0) // {10,11} + CreateWordField(Local0, 0x1, IRQ0) + ShiftLeft(1, PIND, IRQ0) + Return(Local0) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + CreateWordField(ARG0, 1, IRQ0) + /* Use lowest available IRQ */ + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PIND) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PINE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + Store(0, PINE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + Return(IRQB) // Return(IRQP) + } + + Method(_CRS ,0) { + Store (IRQB, Local0) // {10,11} + CreateWordField(Local0, 0x1, IRQ0) + ShiftLeft(1, PINE, IRQ0) + Return(Local0) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + CreateWordField(ARG0, 1, IRQ0) + /* Use lowest available IRQ */ + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PINE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PINF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + Store(0, PINF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + Return(IRQB) // Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + Store (IRQB, Local0) // {10,11} + CreateWordField(Local0, 0x1, IRQ0) + ShiftLeft(1, PINF, IRQ0) + Return(Local0) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + CreateWordField(ARG0, 1, IRQ0) + /* Use lowest available IRQ */ + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PINF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PING) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + Store(0, PING) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + Return(IRQB) // Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + Store (IRQB, Local0) // {10,11} + CreateWordField(Local0, 0x1, IRQ0) + ShiftLeft(1, PING, IRQ0) + Return(Local0) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + CreateWordField(ARG0, 1, IRQ0) + /* Use lowest available IRQ */ + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PING) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PINH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + Store(0, PINH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + Return(IRQB) // Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + Store (IRQB, Local0) // {10,11} + CreateWordField(Local0, 0x1, IRQ0) + ShiftLeft(1, PINH, IRQ0) + Return(Local0) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + CreateWordField(ARG0, 1, IRQ0) + /* Use lowest available IRQ */ + FindSetRightBit(IRQ0, Local0) + Decrement(Local0) + Store(Local0, PINH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible)*/ Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) + IRQ (Edge, ActiveHigh, Exclusive, ) {8} + IO(Decode16,0x0070, 0x0070, 1, 2) /* IO(Decode16,0x0070, 0x0070, 0, 4) */ }) } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ @@ -1319,8 +959,8 @@ Device(TMR) { /* Timer */ Name(_HID,EISAID("PNP0100")) /* System Timer */ Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) + IRQ (Edge, ActiveHigh, Exclusive, ) {0} + IO(Decode16, 0x0040, 0x0040, 1, 4) /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ }) } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ @@ -1328,15 +968,15 @@ Device(SPKR) { /* Speaker */ Name(_HID,EISAID("PNP0800")) /* AT style speaker */ Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) + IO(Decode16, 0x0061, 0x0061, 1, 1) }) } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ Device(PIC) { Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) + IRQ (Edge, ActiveHigh, Exclusive, ) {2} + IO(Decode16,0x0020, 0x0020, 1, 2) IO(Decode16,0x00A0, 0x00A0, 0, 2) /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ @@ -1346,7 +986,7 @@ Device(MAD) { /* 8257 DMA */ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} + DMA(Compatibility,NotBusMaster,Transfer8_16){4} IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) @@ -1359,12 +999,12 @@ Device(COPR) { Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} + IO(Decode16, 0x00F0, 0x00F0, 1, 0x10) + IRQ (Edge, ActiveHigh, Exclusive, ) {13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - Device(HPTM) { + Device(HPET) { Name(_HID,EISAID("PNP0103")) Name(CRS,ResourceTemplate() { Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ @@ -1377,19 +1017,55 @@ Store(HPBA, HPBA) Return(CRS) } - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - } /* end LIBR */ - - Device(HPBR) { - Name(_ADR, 0x00140004) - } /* end HostPciBr */ + } + + Device (KBC0) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQ (Edge, ActiveHigh, Exclusive, ) {1} + }) + } + + Device (MSE0) + { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () + { + IRQ (Edge, ActiveHigh, Exclusive, ) {12} + }) + } + } /* end LPC0 */ Device(ACAD) { Name(_ADR, 0x00140005) + Name (_PRW, Package (0x02) + { + 0x0C, + 0x04 + }) } /* end Ac97audio */ Device(ACMD) { Name(_ADR, 0x00140006) + Name (_PRW, Package (0x02) + { + 0x0C, + 0x04 + }) } /* end Ac97modem */ /* ITE IT8712F Support */ @@ -1435,7 +1111,7 @@ * Keyboard PME is routed to SB600 Gevent3. We can wake * up the system by pressing the key. */ - Method (SIOS, 1) + Method (SIOS, 1) { /* We only enable KBD PME for S5. */ If (LLess (Arg0, 0x05)) @@ -1468,6 +1144,7 @@ XPNP() } +/* ############################################################################################### */ Name(CRES, ResourceTemplate() { IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) @@ -1487,133 +1164,39 @@ 0xF300 /* length */ ) - Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ /* DRAM Memory from 1MB to TopMem */ - Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ - - /* BIOS space just below 4GB */ - DWORDMemory( - ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PCBM - ) - - /* DRAM memory from 4GB to TopMem2 */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - DMHI - ) - - /* BIOS space just below 16EB */ - QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, /* Granularity */ - 0x00000000, /* Min */ - 0x00000000, /* Max */ - 0x00000000, /* Translation */ - 0x00000001, /* Max-Min, RLEN */ - ,, - PEBM - ) - + DWORDMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0, 0, 0, 0x00, 1, ,, EMM2) + WORDIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00, 0x0D00, 0xffff, 0x00, 0xf300) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ CreateDWordField(CRES, ^EMM1._BAS, EM1B) CreateDWordField(CRES, ^EMM1._LEN, EM1L) - CreateDWordField(CRES, ^DMLO._BAS, DMLB) - CreateDWordField(CRES, ^DMLO._LEN, DMLL) - CreateDWordField(CRES, ^PCBM._MIN, PBMB) - CreateDWordField(CRES, ^PCBM._LEN, PBML) - - CreateQWordField(CRES, ^DMHI._MIN, DMHB) - CreateQWordField(CRES, ^DMHI._LEN, DMHL) - CreateQWordField(CRES, ^PEBM._MIN, EBMB) - CreateQWordField(CRES, ^PEBM._LEN, EBML) + + CreateDWordField(CRES, ^EMM2._MIN, EM2B) + CreateDWordField(CRES, ^EMM2._MAX, EM2E) + CreateDWordField(CRES, ^EMM2._LEN, EM2L) + + Store(TOM1, EM2B) + Subtract(IOLM, 1, EM2E) + Subtract(IOLM, TOM1, EM2L) If(LGreater(LOMH, 0xC0000)){ Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ } - /* Set size of memory from 1MB to TopMem */ - Subtract(TOM1, 0x100000, DMLL) - - /* - * If(LNotEqual(TOM2, 0x00000000)){ - * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) - * } - */ - - /* If there is no memory above 4GB, put the BIOS just below 4GB */ - If(LEqual(TOM2, 0x00000000)){ - Store(PBAD,PBMB) /* Reserve the "BIOS" space */ - Store(PBLN,PBML) - } - Else { /* Otherwise, put the BIOS just below 16EB */ - ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ - Store(PBLN,EBML) - } - Return(CRES) /* note to change the Name buffer */ - } /* end of Method(_SB.PCI0._CRS) */ - - /* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ - Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* Determine the OS we're running on */ - CkOT() - - /* On older chips, clear PciExpWakeDisEn */ - /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) - * } - */ - } /* End Method(_SB._INI) */ + } +/* ########################################################################################## */ } /* End Device(PCI0) */ - - Device(PWRB) { /* Start Power button device */ - Name(_HID, EISAID("PNP0C0C")) - Name(_UID, 0xAA) - Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ - Name(_STA, 0x0B) /* sata is invisible */ - } } /* End \_SB scope */ Scope(\_SI) { @@ -1626,7 +1209,7 @@ } /* End Scope SI */ Mutex (SBX0, 0x00) - OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + OperationRegion (SMB0, SystemIO, 0xB00, 0x10) // 0x0C replace by 0x10 Field (SMB0, ByteAcc, NoLock, Preserve) { HSTS, 8, /* SMBUS status */ SSTS, 8, /* SMBUS slave status */ @@ -1639,7 +1222,11 @@ SCNT, 8, /* SMBUS slave control */ SCMD, 8, /* SMBUS shaow cmd */ SEVT, 8, /* SMBUS slave event */ - SDAT, 8 /* SMBUS slave data */ + SDAT, 8, /* SMBUS slave data */ + SMK1, 8, + SLMC, 8, + RADD, 8, + SADD, 8 } Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ @@ -1718,75 +1305,5 @@ Return (Local0) } - - /* THERMAL */ - Scope(\_TZ) { - Name (KELV, 2732) - Name (THOT, 800) - Name (TCRT, 850) - - ThermalZone(TZ00) { - Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ - /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ - Return(Add(0, 2730)) - } - Method(_AL0,0) { /* Returns package of cooling device to turn on */ - /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ - Return(Package() {\_TZ.TZ00.FAN0}) - } - Device (FAN0) { - Name(_HID, EISAID("PNP0C0B")) - Name(_PR0, Package() {PFN0}) - } - - PowerResource(PFN0,0,0) { - Method(_STA) { - Store(0xF,Local0) - Return(Local0) - } - Method(_ON) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ - } - Method(_OFF) { - /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ - } - } - - Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ - Return (Add (THOT, KELV)) - } - Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ - /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ - Return (Add (TCRT, KELV)) - } - Method(_TMP,0) { /* return current temp of this zone */ - Store (SMBR (0x07, 0x4C,, 0x00), Local0) - If (LGreater (Local0, 0x10)) { - Store (Local0, Local1) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400, KELV)) - } - - Store (SMBR (0x07, 0x4C, 0x01), Local0) - /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ - /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ - If (LGreater (Local0, 0x10)) { - If (LGreater (Local0, Local1)) { - Store (Local0, Local1) - } - - Multiply (Local1, 10, Local1) - Return (Add (Local1, KELV)) - } - Else { - Add (Local0, THOT, Local0) - Return (Add (400 , KELV)) - } - } /* end of _TMP */ - } /* end of TZ00 */ - } +#include "acpi/thermal.asl" } -/* End of ASL file */ Modified: trunk/src/mainboard/siemens/sitemp_g1p1/fadt.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/fadt.c Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/fadt.c Wed May 11 09:47:43 2011 (r6567) @@ -26,7 +26,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include "southbridge/amd/sb600/sb600.h" +#include <../southbridge/amd/sb600/sb600.h> /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb acpi */ @@ -56,7 +56,8 @@ memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, "COREBOOT", 8); memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 0; + header->oem_revision = 0x20101005; + header->asl_compiler_revision = 3; fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; Modified: trunk/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/get_bus_conf.c Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c Wed May 11 09:47:43 2011 (r6567) @@ -32,6 +32,7 @@ /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. */ +u8 bus_isa; u8 bus_rs690[8]; u8 bus_sb600[2]; u32 apicid_sb600; @@ -53,6 +54,8 @@ 0x20202020, }; +u32 bus_type[256]; + u32 sbdn_rs690; u32 sbdn_sb600; @@ -64,7 +67,7 @@ { u32 apicid_base; device_t dev; - int i; + int i, j; if (get_bus_conf_done == 1) return; /* do it only once */ @@ -89,13 +92,25 @@ bus_rs690[i] = 0; } + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff; bus_sb600[0] = bus_rs690[0]; + bus_type[bus_rs690[0]] = 1; + /* sb600 */ dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4)); if (dev) { bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb600[1]; j < bus_isa; j++) + bus_type[j] = 1; } /* rs690 */ @@ -103,10 +118,16 @@ dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0)); if (dev) { bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_rs690[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + bus_type[bus_rs690[i]] = 1; /* PCI bus. */ + } } } /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); #else Added: trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.c Wed May 11 09:47:43 2011 (r6567) @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2009 Libra Li <libra.li(a)technexion.com> + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <console/console.h> +#include <arch/interrupt.h> +#include "int15_func.h" + +int sbios_INT15_handler(struct eregs *); +/*extern*/ unsigned long vgainfo_addr; + +static INT15_function_extensions __int15_func; + +/* System BIOS int15 function */ +int sbios_INT15_handler(struct eregs *regs) +{ + int res = -1; + + printk(BIOS_DEBUG, "System BIOS INT 15h\n"); + + switch (regs->eax & 0xffff) { +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + case 0x5f35: + regs->eax = 0x5f; + regs->ecx = BOOT_DISPLAY_DEFAULT; + res = 0; + break; + case 0x5f40: + regs->eax = 0x5f; + regs->ecx = 3; // This is mainboard specific + printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx); + res = 0; + break; + case 0x4e08: + switch (regs->ebx & 0xff) { + case 0x00: + regs->eax &= ~(0xff); + regs->ebx = (regs->ebx & ~(0xff)) | __int15_func.regs.func00_LCD_panel_id; + printk(BIOS_DEBUG, "DISPLAY = %x\n", regs->ebx & 0xff); + res = 0; + break; + case 0x02: + break; + case 0x05: + regs->eax &= ~(0xff); + regs->ebx = (regs->ebx & ~(0xff)) | __int15_func.regs.func05_TV_standard; + printk(BIOS_DEBUG, "TV = %x\n", regs->ebx & 0xff); + res = 0; + break; + case 0x80: + regs->eax &= ~(0xff); + regs->ebx &= ~(0xff); + printk(BIOS_DEBUG, "Integrated System Information = %x:%x\n", regs->edx, regs->edi); + vgainfo_addr = (regs->edx * 16) + regs->edi; + res = 0; + break; + case 0x89: + regs->eax &= ~(0xff); + regs->ebx &= ~(0xff); + printk(BIOS_DEBUG, "Get supported display device information\n"); + res = 0; + break; + default: + break; + } + break; + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); + break; + } + + return res; +} + +/* Initialization VBIOS function extensions */ +void install_INT15_function_extensions(INT15_function_extensions *int15_func) +{ + printk(BIOS_DEBUG, "Initialize function extensions for Callback function number 04E08h ..\n"); + __int15_func.regs.func00_LCD_panel_id = int15_func->regs.func00_LCD_panel_id; + __int15_func.regs.func05_TV_standard = int15_func->regs.func05_TV_standard; + mainboard_interrupt_handlers(0x15, &sbios_INT15_handler); +} Added: trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/siemens/sitemp_g1p1/int15_func.h Wed May 11 09:47:43 2011 (r6567) @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2009 Libra Li <libra.li(a)technexion.com> + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +typedef struct { + u8 func00_LCD_panel_id; // Callback Sub-Function 00h - Get LCD Panel ID + u8 func02_set_expansion; + u8 func05_TV_standard; // Callback Sub-Function 05h - Select Boot-up TV Standard + u16 func80_sysinfo_table; +}INT15_regs; + +typedef struct { + INT15_regs regs; +}INT15_function_extensions; + +extern void install_INT15_function_extensions(INT15_function_extensions *); Modified: trunk/src/mainboard/siemens/sitemp_g1p1/irq_tables.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/irq_tables.c Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/irq_tables.c Wed May 11 09:47:43 2011 (r6567) @@ -23,6 +23,7 @@ Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM */ + #include <console/console.h> #include <device/pci.h> #include <string.h> @@ -31,7 +32,23 @@ #include <cpu/amd/amdk8_sysconf.h> - +/* Platform IRQs */ +#define PIRQA 10 +#define PIRQB 11 +#define PIRQC 5 +#define PIRQD 15 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, @@ -51,6 +68,7 @@ pirq_info->slot = slot; pirq_info->rfu = rfu; } +extern u8 bus_isa; extern u8 bus_rs690[8]; extern u8 bus_sb600[2]; extern unsigned long sbdn_sb600; @@ -96,9 +114,7 @@ slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4, - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); + write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 4, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 1, 0); pirq_info++; slot_num++; Modified: trunk/src/mainboard/siemens/sitemp_g1p1/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/mainboard.c Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/mainboard.c Wed May 11 09:47:43 2011 (r6567) @@ -2,7 +2,9 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. - * + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -16,135 +18,393 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <arch/io.h> +#include <delay.h> #include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> +#include <pc80/mc146818rtc.h> +#include <cpu/x86/lapic.h> #include <southbridge/amd/sb600/sb600.h> +#include <southbridge/amd/rs690/chip.h> +#include <southbridge/amd/rs690/rs690.h> +#include <superio/ite/it8712f/it8712f.h> #include "chip.h" +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#include <x86emu/x86emu.h> +#endif +#include "int15_func.h" + +// ****LCD panel ID support: ***** +// Callback Sub-Function 00h - Get LCD Panel ID +#define PANEL_TABLE_ID_NO 0 // no LCD +#define PANEL_TABLE_ID1 1 // 1024x768_65MHz_Dual +#define PANEL_TABLE_ID2 2 // 920x1200_162MHz +#define PANEL_TABLE_ID3 3 // 600x1200_162MHz +#define PANEL_TABLE_ID4 4 // 1024x768_65MHz +#define PANEL_TABLE_ID5 5 // 1400x1050_108MHz +#define PANEL_TABLE_ID6 6 // 1680x1050_119MHz +#define PANEL_TABLE_ID7 7 // 2048x1536_164MHz +#define PANEL_TABLE_ID8 8 // 1280x1024_108MHz +#define PANEL_TABLE_ID9 9 // 1366x768_86MHz_chimei_V32B1L01 + +// Callback Sub-Function 05h � Select Boot-up TV Standard +#define TV_MODE_00 0x00 /* NTSC */ +#define TV_MODE_01 0x01 /* PAL */ +#define TV_MODE_02 0x02 /* PALM */ +#define TV_MODE_03 0x03 /* PAL60 */ +#define TV_MODE_04 0x04 /* NTSCJ */ +#define TV_MODE_05 0x05 /* PALCN */ +#define TV_MODE_06 0x06 /* PALN */ +#define TV_MODE_09 0x09 /* SCART-RGB */ +#define TV_MODE_NO 0xff /* No TV Support */ + +#define PLX_VIDDID 0x861610b5 + +/* 7475 Common Registers */ +#define REG_DEVREV2 0x12 /* ADT7490 only */ +#define REG_VTT 0x1E /* ADT7490 only */ +#define REG_EXTEND3 0x1F /* ADT7490 only */ +#define REG_VOLTAGE_BASE 0x20 +#define REG_TEMP_BASE 0x25 +#define REG_TACH_BASE 0x28 +#define REG_PWM_BASE 0x30 +#define REG_PWM_MAX_BASE 0x38 +#define REG_DEVID 0x3D +#define REG_VENDID 0x3E +#define REG_DEVID2 0x3F +#define REG_STATUS1 0x41 +#define REG_STATUS2 0x42 +#define REG_VID 0x43 /* ADT7476 only */ +#define REG_VOLTAGE_MIN_BASE 0x44 +#define REG_VOLTAGE_MAX_BASE 0x45 +#define REG_TEMP_MIN_BASE 0x4E +#define REG_TEMP_MAX_BASE 0x4F +#define REG_TACH_MIN_BASE 0x54 +#define REG_PWM_CONFIG_BASE 0x5C +#define REG_TEMP_TRANGE_BASE 0x5F +#define REG_PWM_MIN_BASE 0x64 +#define REG_TEMP_TMIN_BASE 0x67 +#define REG_TEMP_THERM_BASE 0x6A +#define REG_REMOTE1_HYSTERSIS 0x6D +#define REG_REMOTE2_HYSTERSIS 0x6E +#define REG_TEMP_OFFSET_BASE 0x70 +#define REG_CONFIG2 0x73 +#define REG_EXTEND1 0x76 +#define REG_EXTEND2 0x77 +#define REG_CONFIG1 0x40 // ADT7475 +#define REG_CONFIG3 0x78 +#define REG_CONFIG5 0x7C +#define REG_CONFIG6 0x10 // ADT7475 +#define REG_CONFIG7 0x11 // ADT7475 +#define REG_CONFIG4 0x7D +#define REG_STATUS4 0x81 /* ADT7490 only */ +#define REG_VTT_MIN 0x84 /* ADT7490 only */ +#define REG_VTT_MAX 0x86 /* ADT7490 only */ + +#define VID_VIDSEL 0x80 /* ADT7476 only */ + +#define CONFIG2_ATTN 0x20 +#define CONFIG3_SMBALERT 0x01 +#define CONFIG3_THERM 0x02 +#define CONFIG4_PINFUNC 0x03 +#define CONFIG4_MAXDUTY 0x08 +#define CONFIG4_ATTN_IN10 0x30 +#define CONFIG4_ATTN_IN43 0xC0 +#define CONFIG5_TWOSCOMP 0x01 +#define CONFIG5_TEMPOFFSET 0x02 +#define CONFIG5_VIDGPIO 0x10 /* ADT7476 only */ +#define REMOTE1 0 +#define LOCAL 1 +#define REMOTE2 2 + +/* ADT7475 Settings */ +#define ADT7475_VOLTAGE_COUNT 5 /* Not counting Vtt */ +#define ADT7475_TEMP_COUNT 3 +#define ADT7475_TACH_COUNT 4 +#define ADT7475_PWM_COUNT 3 + +/* Macros to easily index the registers */ +#define TACH_REG(idx) (REG_TACH_BASE + ((idx) * 2)) +#define TACH_MIN_REG(idx) (REG_TACH_MIN_BASE + ((idx) * 2)) + +#define PWM_REG(idx) (REG_PWM_BASE + (idx)) +#define PWM_MAX_REG(idx) (REG_PWM_MAX_BASE + (idx)) +#define PWM_MIN_REG(idx) (REG_PWM_MIN_BASE + (idx)) +#define PWM_CONFIG_REG(idx) (REG_PWM_CONFIG_BASE + (idx)) + +#define VOLTAGE_REG(idx) (REG_VOLTAGE_BASE + (idx)) +#define VOLTAGE_MIN_REG(idx) (REG_VOLTAGE_MIN_BASE + ((idx) * 2)) +#define VOLTAGE_MAX_REG(idx) (REG_VOLTAGE_MAX_BASE + ((idx) * 2)) + +#define TEMP_REG(idx) (REG_TEMP_BASE + (idx)) +#define TEMP_MIN_REG(idx) (REG_TEMP_MIN_BASE + ((idx) * 2)) +#define TEMP_MAX_REG(idx) (REG_TEMP_MAX_BASE + ((idx) * 2)) +#define TEMP_TMIN_REG(idx) (REG_TEMP_TMIN_BASE + (idx)) +#define TEMP_THERM_REG(idx) (REG_TEMP_THERM_BASE + (idx)) +#define TEMP_OFFSET_REG(idx) (REG_TEMP_OFFSET_BASE + (idx)) +#define TEMP_TRANGE_REG(idx) (REG_TEMP_TRANGE_BASE + (idx)) -#define ADT7461_ADDRESS 0x4C -#define ARA_ADDRESS 0x0C /* Alert Response Address */ #define SMBUS_IO_BASE 0x1000 +#define ADT7475_ADDRESS 0x2E + +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define A_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) // 0x2: SMM space at 640KB-768KB extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, - u8 val); -#define ADT7461_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) -#define ARA_read_byte(address) \ - do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) -#define ADT7461_write_byte(address, val) \ - do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) +extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); uint64_t uma_memory_base, uma_memory_size; +static u32 smbus_io_base = SMBUS_IO_BASE; +static u32 adt7475_address = ADT7475_ADDRESS; -/******************************************************** -* dbm690t uses a BCM5789 as on-board NIC. -* It has a pin named LOW_POWER to enable it into LOW POWER state. -* In order to run NIC, we should let it out of Low power state. This pin is -* controlled by sb600 GPM3. -* RRG4.2.3 GPM as GPIO -* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers: -* I/O C50, C51, C52, PM I/O94, 95, 96. -* RRG4.2.3.1 GPM pins as Input -* RRG4.2.3.2 GPM pins as Output -********************************************************/ -static void enable_onboard_nic(void) +/* Macro to read the registers */ +#define adt7475_read_byte(reg) \ + do_smbus_read_byte(smbus_io_base, adt7475_address, reg) + +#define adt7475_write_byte(reg, val) \ + do_smbus_write_byte(smbus_io_base, adt7475_address, reg, val) + +#define TWOS_COMPL 1 + +struct __table__{ + const char *info; + u8 val; +}; + +struct __table__ dutycycles[] = { + {"25%", 0x3f},{"30%", 0x4c},{"35%", 0x59},{"40%", 0x66},{"45%", 0x73}, + {"50%", 0x80},{"55%", 0x8d},{"60%", 0x9a},{"65%", 0xa7},{"70%", 0xb4}, + {"75%", 0xc1},{"80%", 0xce},{"85%", 0xdb},{"90%", 0xe8},{"95%", 0xf5}, + {"100%", 0xff} +}; +#define SIZEOF_DUTYCYCLES sizeof(dutycycles)/sizeof(struct __table__) +#define DUTYCYCLE(i,d) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].val : dutycycles[d].val // hopefully d is a correct value !!! fix +#define DUTYCYCLE_INFO(i) (i < SIZEOF_DUTYCYCLES) ? dutycycles[i].info : "out_of_range" +#if TWOS_COMPL == 0 +struct __table__ temperatures[] = { + {"30�C", 0x5e},{"35�C", 0x63},{"40�C", 0x68},{"45�C", 0x6d},{"50�C", 0x72}, + {"55�C", 0x77},{"60�C", 0x7c},{"65�C", 0x81},{"70�C", 0x86},{"75�C", 0x8b}, + {"80�C", 0x90} +}; +#else +struct __table__ temperatures[] = { + {"30�C", 30},{"35�C", 35},{"40�C", 40},{"45�C", 45},{"50�C", 50}, + {"55�C", 55},{"60�C", 60},{"65�C", 65},{"70�C", 70},{"75�C", 75}, + {"80�C", 80} +}; +#endif +int trange[] = {2.0,2.5,3.33,4.0,5.0,6.67,8.0,10.0,13.33,16.0,20.0,26.67,32.0,40.0,53.33,80.0}; + +#define SIZEOF_TEMPERATURES sizeof(temperatures)/sizeof(struct __table__) +#define TEMPERATURE(i,d) (i < SIZEOF_TEMPERATURES) ? temperatures[i].val : temperatures[d].val // hopefully d is a correct value !!! fix +#define TEMPERATURE_INFO(i) (i < SIZEOF_TEMPERATURES) ? temperatures[i].info : "out of range" + +struct fan_control { + unsigned int enable : 1; + u8 polarity; + u8 t_min; + u8 t_max; + u8 pwm_min; + u8 pwm_max; + u8 t_range; +}; +/* ############################################################################################# */ +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +static int int15_handler(void) { - u8 byte; +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + + switch (M.x86.R_AX) { + case 0x4e08: /* Boot Display */ + switch (M.x86.R_BX) { + case 0x80: + M.x86.R_AX &= ~(0xff); // Success + M.x86.R_BX &= ~(0xff); + printk(BIOS_DEBUG, "Integrated System Information\n"); + break; + case 0x00: + M.x86.R_AX &= ~(0xff); + M.x86.R_BX = 0x00; + printk(BIOS_DEBUG, "Panel ID = 0\n"); + break; + case 0x05: + M.x86.R_AX &= ~(0xff); + M.x86.R_BX = 0xff; + printk(BIOS_DEBUG, "TV = off\n"); + break; + default: + return 0; + } + break; + case 0x5f35: /* Boot Display */ + M.x86.R_AX = 0x005f; // Success + M.x86.R_CL = BOOT_DISPLAY_DEFAULT; + break; + case 0x5f40: /* Boot Panel Type */ + // M.x86.R_AX = 0x015f; // Supported but failed + M.x86.R_AX = 0x005f; // Success + M.x86.R_CL = 3; // Display ID + break; + default: + /* Interrupt was not handled */ + return 0; + } - printk(BIOS_INFO, "%s.\n", __func__); + /* Interrupt handled */ + return 1; +} - /* set index register 0C50h to 13h (miscellaneous control) */ - outb(0x13, 0xC50); /* CMIndex */ +static void int15_install(void) +{ + typedef int (* yabel_handleIntFunc)(void); + extern yabel_handleIntFunc yabel_intFuncArray[256]; + yabel_intFuncArray[0x15] = int15_handler; +} +#endif +/* ############################################################################################# */ + + /** + * @brief + * + * @param + */ - /* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */ - byte = inb(0xC51); - byte &= 0x3F; - byte |= 0x40; - outb(byte, 0xC51); - - /* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */ - byte = inb(0xC52); - byte &= ~0x8; - outb(byte, 0xC52); - - /* set CM data register 0C51h bits [7:6] to 10b to set Output state control */ - byte = inb(0xC51); - byte &= 0x3F; - byte |= 0x80; /* 7:6=10 */ - outb(byte, 0xC51); - - /* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */ - byte = inb(0xC52); - byte &= ~0x8; - outb(byte, 0xC52); +static u8 calc_trange(u8 t_min, u8 t_max) { + + u8 prev; + int i; + int diff = t_max - t_min; + + // walk through the trange table + for(i = 0, prev = 0; i < sizeof(trange)/sizeof(int); i++) { + if( trange[i] < diff ) { + prev = i; // save last val + continue; + } + if( diff == trange[i] ) return i; + if( (diff - trange[prev]) < (trange[i] - diff) ) break; // return with last val index + return i; + } + return prev; } /******************************************************** -* dbm690t uses SB600 GPIO9 to detect IDE_DMA66. +* sina uses SB600 GPIO9 to detect IDE_DMA66. * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to * get the cable type, 40 pin or 80 pin? ********************************************************/ -static void get_ide_dma66(void) +static void cable_detect(void) { + u8 byte; struct device *sm_dev; struct device *ide_dev; - - printk(BIOS_INFO, "%s.\n", __func__); + + /* SMBus Module and ACPI Block (Device 20, Function 0) on SB600 */ + printk(BIOS_DEBUG, "%s.\n", __func__); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); byte = pci_read_config8(sm_dev, 0xA9); byte |= (1 << 5); /* Set Gpio9 as input */ pci_write_config8(sm_dev, 0xA9, byte); - + + /* IDE Controller (Device 20, Function 1) on SB600 */ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); + + byte = pci_read_config8(ide_dev, 9); + printk(BIOS_INFO, "IDE controller in %s Mode\n", byte & (1 << 0) ? "Native" : "Compatibility"); + byte = pci_read_config8(ide_dev, 0x56); byte &= ~(7 << 0); - if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) + if( pci_read_config8(sm_dev, 0xAA) & (1 << 5) ) byte |= 2 << 0; /* mode 2 */ else byte |= 5 << 0; /* mode 5 */ + printk(BIOS_INFO, "DMA mode %d selected\n", byte & (7 << 0)); pci_write_config8(ide_dev, 0x56, byte); } -/* - * set thermal config +/** + * @brief Detect the ADT7475 device + * + * @param */ -static void set_thermal_config(void) + +static const char * adt7475_detect( void ) { + + int vendid, devid, devid2; + const char *name = NULL; + + vendid = adt7475_read_byte(REG_VENDID); + devid2 = adt7475_read_byte(REG_DEVID2); + if (vendid != 0x41 || /* Analog Devices */ + (devid2 & 0xf8) != 0x68) { + return name; + } + + devid = adt7475_read_byte(REG_DEVID); + if (devid == 0x73) + name = "adt7473"; + else if (devid == 0x75 && adt7475_address == 0x2e) + name = "adt7475"; + else if (devid == 0x76) + name = "adt7476"; + else if ((devid2 & 0xfc) == 0x6c) + name = "adt7490"; + + return name; +} + +// thermal control defaults +const struct fan_control cpu_fan_control_defaults = { + .enable = 0, // disable by default + .polarity = 0, // high by default + .t_min = 3, // default = 45�C + .t_max = 7, // 65�C + .pwm_min = 1, // default dutycycle = 30% + .pwm_max = 13, // 90% +}; +const struct fan_control case_fan_control_defaults = { + .enable = 0, // disable by default + .polarity = 0, // high by default + .t_min = 2, // default = 40�C + .t_max = 8, // 70�C + .pwm_min = 0, // default dutycycle = 25% + .pwm_max = 13, // 90% +}; + +static void pm_init( void ) { - u8 byte; u16 word; - device_t sm_dev; - - /* set ADT 7461 */ - ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ - ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ - ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ - ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ - - ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ - ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ - - byte = ADT7461_read_byte(0x02); /* read status register to clear it */ - ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ - printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); + u8 byte; + device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - /* sb600 settings for thermal config */ /* set SB600 GPIO 64 to GPIO with pull-up */ byte = pm2_ioread(0x42); byte &= 0x3f; pm2_iowrite(0x42, byte); - /* set GPIO 64 to input */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + /* set GPIO 64 to tristate */ word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; pci_write_config16(sm_dev, 0x56, word); @@ -163,41 +423,477 @@ byte = pm_ioread(0x3c); byte &= 0xf3; pm_iowrite(0x3c, byte); + + /* set GPM5 to not wake from s5 */ + byte = pm_ioread(0x77); + byte &= ~(1 << 5); + pm_iowrite(0x77, byte); +} + + /** + * @brief Setup thermal config on SINA Mainboard + * + * @param + */ + +static void set_thermal_config(void) +{ + u8 byte, byte2; + u8 cpu_pwm_conf, case_pwm_conf; + device_t sm_dev; + struct fan_control cpu_fan_control, case_fan_control; + const char *name = NULL; + + + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + smbus_io_base = pci_read_config32(sm_dev, 0x10) & ~(0xf); // get BAR0-Address which holds the SMBUS_IO_BASE + + if( (name = adt7475_detect()) == NULL ) { + printk(BIOS_NOTICE, "Couldn't detect an ADT7473/75/76/90 part at %x:%x\n", smbus_io_base, adt7475_address); + return; + } + printk(BIOS_DEBUG, "Found %s part at %x:%x\n", name, smbus_io_base, adt7475_address); + + cpu_fan_control = cpu_fan_control_defaults; + case_fan_control = case_fan_control_defaults; + + if( get_option(&byte, "cpu_fan_control") == -4 ) { + printk(BIOS_WARNING, "%s: CMOS checksum invalid, keeping default values\n",__func__); + } else { + // get all the options needed + if( get_option(&byte, "cpu_fan_control") == 0 ) + cpu_fan_control.enable = byte ? 1 : 0; + + get_option(&cpu_fan_control.polarity, "cpu_fan_polarity"); + get_option(&cpu_fan_control.t_min, "cpu_t_min"); + get_option(&cpu_fan_control.t_max, "cpu_t_max"); + get_option(&cpu_fan_control.pwm_min, "cpu_dutycycle_min"); + get_option(&cpu_fan_control.pwm_max, "cpu_dutycycle_max"); + + if( get_option(&byte, "chassis_fan_control") == 0) + case_fan_control.enable = byte ? 1 : 0; + get_option(&case_fan_control.polarity, "chassis_fan_polarity"); + get_option(&case_fan_control.t_min, "chassis_t_min"); + get_option(&case_fan_control.t_max, "chassis_t_max"); + get_option(&case_fan_control.pwm_min, "chassis_dutycycle_min"); + get_option(&case_fan_control.pwm_max, "chassis_dutycycle_max"); + + } + + printk(BIOS_DEBUG, "cpu_fan_control:%s", cpu_fan_control.enable ? "enable" : "disable"); + printk(BIOS_DEBUG, " cpu_fan_polarity:%s", cpu_fan_control.polarity ? "low" : "high"); + + printk(BIOS_DEBUG, " cpu_t_min:%s", TEMPERATURE_INFO(cpu_fan_control.t_min)); + cpu_fan_control.t_min = TEMPERATURE(cpu_fan_control.t_min, cpu_fan_control_defaults.t_min); + + printk(BIOS_DEBUG, " cpu_t_max:%s", TEMPERATURE_INFO(cpu_fan_control.t_max)); + cpu_fan_control.t_max = TEMPERATURE(cpu_fan_control.t_max, cpu_fan_control_defaults.t_max); + + printk(BIOS_DEBUG, " cpu_pwm_min:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_min)); + cpu_fan_control.pwm_min = DUTYCYCLE(cpu_fan_control.pwm_min, cpu_fan_control_defaults.pwm_min); + + printk(BIOS_DEBUG, " cpu_pwm_max:%s", DUTYCYCLE_INFO(cpu_fan_control.pwm_max)); + cpu_fan_control.pwm_max = DUTYCYCLE(cpu_fan_control.pwm_max, cpu_fan_control_defaults.pwm_max); + + cpu_fan_control.t_range = calc_trange(cpu_fan_control.t_min, cpu_fan_control.t_max); + printk(BIOS_DEBUG, " cpu_t_range:0x%02x\n", cpu_fan_control.t_range); + cpu_fan_control.t_range <<= 4; + cpu_fan_control.t_range |= (4 << 0); // 35.3Hz + + printk(BIOS_DEBUG, "chassis_fan_control:%s", case_fan_control.enable ? "enable" : "disable"); + printk(BIOS_DEBUG, " chassis_fan_polarity:%s", case_fan_control.polarity ? "low" : "high"); + + printk(BIOS_DEBUG, " chassis_t_min:%s", TEMPERATURE_INFO(case_fan_control.t_min)); + case_fan_control.t_min = TEMPERATURE(case_fan_control.t_min, case_fan_control_defaults.t_min); + + printk(BIOS_DEBUG, " chassis_t_max:%s", TEMPERATURE_INFO(case_fan_control.t_max)); + case_fan_control.t_max = TEMPERATURE(case_fan_control.t_max, case_fan_control_defaults.t_max); + + printk(BIOS_DEBUG, " chassis_pwm_min:%s", DUTYCYCLE_INFO(case_fan_control.pwm_min)); + case_fan_control.pwm_min = DUTYCYCLE(case_fan_control.pwm_min, case_fan_control_defaults.pwm_min); + + printk(BIOS_DEBUG, " chassis_pwm_max:%s", DUTYCYCLE_INFO(case_fan_control.pwm_max)); + case_fan_control.pwm_max = DUTYCYCLE(case_fan_control.pwm_max, case_fan_control_defaults.pwm_max); + + case_fan_control.t_range = calc_trange(case_fan_control.t_min, case_fan_control.t_max); + printk(BIOS_DEBUG, " case_t_range:0x%02x\n", case_fan_control.t_range); + case_fan_control.t_range <<= 4; + case_fan_control.t_range |= (4 << 0); // 35.3Hz + + cpu_pwm_conf = (((cpu_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output + case_pwm_conf = (((case_fan_control.polarity & 0x1) << 4) | 0x2); // bit 4 control polarity of PWMx output + cpu_pwm_conf |= cpu_fan_control.enable ? (0 << 5) : (7 << 5); // manual control + case_pwm_conf |= case_fan_control.enable ? (1 << 5) : (7 << 5); // local temp + + /* set adt7475 */ + + adt7475_write_byte(REG_CONFIG1, 0x04); // clear register, bit 2 is read only + + /* Config Register 6: */ + adt7475_write_byte(REG_CONFIG6, 0x00); + /* Config Register 7 */ + adt7475_write_byte(REG_CONFIG7, 0x00); + + /* Config Register 5: */ + /* set Offset 64 format, enable THERM on Remote 1& Local */ + adt7475_write_byte(REG_CONFIG5, TWOS_COMPL ? 0x61 : 0x60); + /* No offset for remote 1 */ + adt7475_write_byte(TEMP_OFFSET_REG(0), 0x00); + /* No offset for local */ + adt7475_write_byte(TEMP_OFFSET_REG(1), 0x00); + /* No offset for remote 2 */ + adt7475_write_byte(TEMP_OFFSET_REG(2), 0x00); + + /* remote 1 low temp limit */ + adt7475_write_byte(TEMP_MIN_REG(0), 0x00); + /* remote 1 High temp limit (90C) */ + adt7475_write_byte(TEMP_MAX_REG(0), 0x9a); + + /* local Low Temp Limit */ + adt7475_write_byte(TEMP_MIN_REG(1), 0x00); + /* local High Limit (90C) */ + adt7475_write_byte(TEMP_MAX_REG(1), 0x9a); + + /* remote 1 therm temp limit (95C) */ + adt7475_write_byte(TEMP_THERM_REG(0), 0x9f); + /* local therm temp limit (95C) */ + adt7475_write_byte(TEMP_THERM_REG(1), 0x9f); + + /* PWM 1 configuration register CPU fan controlled by CPU Thermal Diode */ + adt7475_write_byte(PWM_CONFIG_REG(0), cpu_pwm_conf); + /* PWM 3 configuration register Case fan controlled by ADTxxxx temp */ + adt7475_write_byte(PWM_CONFIG_REG(2), case_pwm_conf); + + if( cpu_fan_control.enable ) { + /* PWM 1 minimum duty cycle (37%) */ + adt7475_write_byte(PWM_MIN_REG(0), cpu_fan_control.pwm_min); + /* PWM 1 Maximum duty cycle (100%) */ + adt7475_write_byte(PWM_MAX_REG(0), cpu_fan_control.pwm_max); + /* Remote 1 temperature Tmin (32C) */ + adt7475_write_byte(TEMP_TMIN_REG(0), cpu_fan_control.t_min); + /* remote 1 Trange (53C ramp range) */ + adt7475_write_byte(TEMP_TRANGE_REG(0), cpu_fan_control.t_range); + } else { + adt7475_write_byte(PWM_REG(0), cpu_fan_control.pwm_max); + } + + if( case_fan_control.enable ) { + /* PWM 2 minimum duty cycle (37%) */ + adt7475_write_byte(PWM_MIN_REG(2), case_fan_control.pwm_min); + /* PWM 2 Maximum Duty Cycle (100%) */ + adt7475_write_byte(PWM_MAX_REG(2), case_fan_control.pwm_max); + /* local temperature Tmin (32C) */ + adt7475_write_byte(TEMP_TMIN_REG(1), case_fan_control.t_min); + /* local Trange (53C ramp range) */ + adt7475_write_byte(TEMP_TRANGE_REG(1), case_fan_control.t_range); // Local TRange + adt7475_write_byte(TEMP_TRANGE_REG(2), case_fan_control.t_range); // PWM2 Freq + } else { + adt7475_write_byte(PWM_REG(2), case_fan_control.pwm_max); + } + + /* Config Register 3 - enable smbalert & therm */ + adt7475_write_byte(0x78, 0x03); + /* Config Register 4 - enable therm output */ + adt7475_write_byte(0x7d, 0x09); + /* Interrupt Mask Register 2 - Mask SMB alert for Therm Conditions, Fan 3 fault, SmbAlert Fan for Therm Timer event */ + adt7475_write_byte(0x75, 0x2e); + + /* Config Register 1 Set Start bit */ + adt7475_write_byte(0x40, 0x05); + + /* Read status register to clear any old errors */ + byte2 = adt7475_read_byte(0x42); + byte = adt7475_read_byte(0x41); + + printk(BIOS_DEBUG, "Init 'Thermal Monitor' end , status 0x42 = 0x%02x, status 0x41 = 0x%02x\n", + byte2, byte); + +} + + /** + * @brief + * + * @param + */ + +static void patch_mmio_nonposted( void ) +{ + unsigned reg, index; + resource_t rbase, rend; + u32 base, limit; + struct resource *resource; + device_t dev; + device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1)); + + printk(BIOS_DEBUG,"%s ...\n", __func__); + + dev = dev_find_slot(1, PCI_DEVFN(5,0)); + // the uma frame buffer + index = 0x10; + resource = probe_resource(dev, index); + if( resource ) { + // fixup resource nonposted in k8 mmio + /* Get the base address */ + rbase = (resource->base >> 8) & ~(0xff); + /* Get the limit (rounded up) */ + rend = (resource_end(resource) >> 8) & ~(0xff); + + printk(BIOS_DEBUG,"%s %x base = %0llx limit = %0llx\n", dev_path(dev), index, rbase, rend); + + for( reg = 0xb8; reg >= 0x80; reg -= 8 ) { + base = pci_read_config32(k8_f1,reg); + limit = pci_read_config32(k8_f1,reg+4); + printk(BIOS_DEBUG," %02x[%08x] %02x[%08x]", reg, base, reg+4, limit); + if( ((base & ~(0xff)) == rbase) && ((limit & ~(0xff)) == rend) ) { + limit |= (1 << 7); + printk(BIOS_DEBUG, "\nPatching %s %x <- %08x", dev_path(k8_f1), reg, limit); + pci_write_config32(k8_f1, reg+4, limit); + break; + } + } + printk(BIOS_DEBUG, "\n"); + } +} + + /** + * @brief + * + * @param + */ + +static void wait_pepp( void ) { + + int boot_delay = 0; + + if( get_option(&boot_delay, "boot_delay") < 0) + boot_delay = 5; + + printk(BIOS_DEBUG, "boot_delay = %d sec\n", boot_delay); + if ( boot_delay > 0 ) { + init_timer(); + // wait for PEPP-Board + printk(BIOS_INFO, "Give PEPP-Board %d sec(s) time to coming up ", boot_delay); + while ( boot_delay ) { + lapic_write(LAPIC_TMICT, 0xffffffff); + udelay(1000000); // delay time approx. 1 sec + printk(BIOS_INFO, "."); + boot_delay--; + } + printk(BIOS_INFO, "\n"); + } +} + + /** + * @brief + * + * @param + */ + +struct { + unsigned int bus; + unsigned int devfn; +} slot[] = { + {0, PCI_DEVFN(0,0)}, + {0, PCI_DEVFN(18,0)}, + {0, PCI_DEVFN(19,0)},{0, PCI_DEVFN(19,1)},{0, PCI_DEVFN(19,2)},{0, PCI_DEVFN(19,3)},{0, PCI_DEVFN(19,4)},{0, PCI_DEVFN(19,5)}, + {0, PCI_DEVFN(20,0)},{0, PCI_DEVFN(20,1)},{0, PCI_DEVFN(20,2)},{0, PCI_DEVFN(20,3)},{0, PCI_DEVFN(20,5)},{0, PCI_DEVFN(20,6)}, + {0, PCI_DEVFN(5,0)},{0, PCI_DEVFN(5,2)}, + {255,0}, +}; + + +static void update_subsystemid( device_t dev ) { + + int i; + struct mainboard_config *mb = dev->chip_info; + + dev->subsystem_vendor = 0x110a; + if( mb->plx_present ){ + dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077 + } else { + dev->subsystem_device = 0x4077; // U1P0 = 0x4077 + } + printk(BIOS_INFO, "%s [%x/%x]\n", dev->chip_ops->name, dev->subsystem_vendor, dev->subsystem_device ); + for( i=0; slot[i].bus < 255; i++) { + device_t d; + d = dev_find_slot(slot[i].bus,slot[i].devfn); + if( d ) { + printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device); + d->subsystem_device = dev->subsystem_device; + } + } +} + + /** + * @brief + * + * @param + */ - /* THERMTRIP pin */ - /* byte = pm_ioread(0x68); - * byte |= 1 << 3; - * pm_iowrite(0x68, byte); - * - * byte = pm_ioread(0x55); - * byte |= 1 << 0; - * pm_iowrite(0x55, byte); - * - * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); - * pm_iowrite(0x67, byte); +static void detect_hw_variant( device_t dev ) { + + device_t nb_dev =0, dev2 = 0; + struct southbridge_amd_rs690_config *cfg; + u32 lc_state, id = 0; + struct mainboard_config *mb = dev->chip_info; + + printk(BIOS_INFO, "Scan for PLX device ...\n"); + nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!nb_dev) { + die("CAN NOT FIND RS690 DEVICE, HALT!\n"); + /* NOT REACHED */ + } + + dev2 = dev_find_slot(0, PCI_DEVFN(2, 0)); + if (!dev2) { + die("CAN NOT FIND GFX DEVICE 2, HALT!\n"); + /* NOT REACHED */ + } + PcieReleasePortTraining(nb_dev, dev2, 2); // we assume PLX is connected to port 2 + + mdelay(40); + lc_state = nbpcie_p_read_index(dev2, 0xa5); /* lc_state */ + printk(BIOS_DEBUG, "lc current state=%x\n", lc_state); + /* LC_CURRENT_STATE = bit0-5 */ + switch( lc_state & 0x3f ){ + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + printk(BIOS_NOTICE, "No device present, skipping PLX scan ..\n"); + break; + case 0x07: + case 0x10: + { + struct device dummy; + u32 pci_primary_bus, buses; + u16 secondary, subordinate; + + printk(BIOS_DEBUG, "Scan for PLX bridge behind %s[%x]\n", dev_path(dev2), pci_read_config32(dev2, PCI_VENDOR_ID)); + // save the existing primary/secondary/subordinate bus number configuration. + secondary = dev2->bus->secondary; + subordinate = dev2->bus->subordinate; + buses = pci_primary_bus = pci_read_config32(dev2, PCI_PRIMARY_BUS); + + // Configure the bus numbers for this bridge + // bus number 1 is for internal gfx device, so we start with busnumber 2 + + buses &= 0xff000000; + buses |= ((2 << 8) | (0xff << 16)); + // setup the buses in device 2 + pci_write_config32(dev2,PCI_PRIMARY_BUS, buses); + + // fake a device descriptor for a device behind device 2 + dummy.bus = dev2->bus; + dummy.bus->secondary = (buses >> 8) & 0xff; + dummy.bus->subordinate = (buses >> 16) & 0xff; + dummy.path.type = DEVICE_PATH_PCI; + dummy.path.pci.devfn = PCI_DEVFN(0,0); // PLX: device number 0, function 0 + + id = pci_read_config32(&dummy, PCI_VENDOR_ID); + /* Have we found something? + * Some broken boards return 0 if a slot is empty, but + * the expected answer is 0xffffffff + */ + if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { + printk(BIOS_DEBUG, "%s, bad id 0x%x\n", dev_path(&dummy), id); + } else { + printk(BIOS_DEBUG, "found device [%x]\n", id); + } + // restore changes made for device 2 + dev2->bus->secondary = secondary; + dev2->bus->secondary = subordinate; + pci_write_config32(dev2, PCI_PRIMARY_BUS, pci_primary_bus); + } + break; + default: + break; + } + + mb->plx_present = 0; + if( id == PLX_VIDDID ){ + printk(BIOS_INFO, "found PLX device\n"); + mb->plx_present = 1; + cfg = (struct southbridge_amd_rs690_config *)dev2->chip_info; + if( cfg->gfx_tmds ) { + printk(BIOS_INFO, "Disable 'gfx_tmds' support\n"); + cfg->gfx_tmds = 0; + cfg->gfx_link_width = 4; + } + return; + } +} + +static void smm_lock( void ) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x69, + D_LCK | G_SMRAME | A_BASE_SEG); +} + + /** + * @brief Init + * + * @param the root device + */ + +static void init(device_t dev) +{ +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0 + INT15_function_extensions int15_func; +#endif + + printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n", + dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__); + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0 + if( get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") < 0 ) + int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO; + int15_func.regs.func05_TV_standard = TV_MODE_NO; + install_INT15_function_extensions(&int15_func); +#endif + set_thermal_config(); + pm_init(); + cable_detect(); + patch_mmio_nonposted(); + smm_lock(); } /************************************************* -* enable the dedicated function in dbm690t board. +* enable the dedicated function in sina board. * This function called early than rs690_enable. *************************************************/ -static void dbm690t_enable(device_t dev) +static void enable_dev(device_t dev) { - printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev); + + printk(BIOS_INFO, "%s %s[%x/%x] %s\n", + dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__); +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL + /* Install custom int15 handler for VGA OPROM */ + int15_install(); +#endif + detect_hw_variant(dev); + update_subsystemid(dev); + #if (CONFIG_GFXUMA == 1) + { msr_t msr, msr2; - + /* TOP_MEM: the top of DRAM below 4G */ msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + printk(BIOS_DEBUG, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", __func__, msr.lo, msr.hi); - + /* TOP_MEM2: the top of DRAM above 4G */ msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + + printk(BIOS_DEBUG, "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", __func__, msr2.lo, msr2.hi); switch (msr.lo) { @@ -219,35 +915,50 @@ } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ + } #else - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - uma_memory_base = 0x38000000; /* 1GB system memory supposed */ + uma_memory_size = 0; + uma_memory_base = 0; #endif - enable_onboard_nic(); - get_ide_dma66(); - set_thermal_config(); + wait_pepp(); + dev->ops->init = init; // rest of mainboard init later } + /** + * @brief + * + * @param + */ + int add_mainboard_resources(struct lb_memory *mem) { + device_t dev; + struct resource *res; + + dev = dev_find_slot(0, PCI_DEVFN(0,0)); + res = probe_resource(dev, 0x1C); + if( res ) { + printk(BIOS_INFO, "mmconf: base=%0llx size=%0llx\n", res->base, res->size); + lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, res->size); + } /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); - lb_add_memory_range(mem, LB_MEM_RESERVED, - uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif return 0; } struct chip_operations mainboard_ops = { - CHIP_NAME("AMD DBM690T Mainboard") - .enable_dev = dbm690t_enable, + CHIP_NAME(CONFIG_MAINBOARD_PART_NUMBER) + .enable_dev = enable_dev, }; Modified: trunk/src/mainboard/siemens/sitemp_g1p1/mptable.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/mptable.c Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/mptable.c Wed May 11 09:47:43 2011 (r6567) @@ -23,135 +23,50 @@ #include <arch/io.h> #include <string.h> #include <stdint.h> + #include <cpu/amd/amdk8_sysconf.h> +extern u8 bus_isa; extern u8 bus_rs690[8]; extern u8 bus_sb600[2]; extern u32 apicid_sb600; +extern u32 bus_type[256]; extern u32 sbdn_rs690; extern u32 sbdn_sb600; static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - int bus_isa; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - + int isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); - smp_write_processors(mc); get_bus_conf(); + printk(BIOS_DEBUG, "%s: bus_isa=%d, apic_id=0x%x\n", __func__, bus_isa, apicid_sb600); - mptable_write_buses(mc, NULL, &bus_isa); - + mptable_write_buses(mc, NULL, &isa_bus); + if (isa_bus != bus_isa) { + printk(BIOS_ERR, "ISA bus numbering schemes differ! Please fix mptable.c\n"); + } /* I/O APICs: APIC ID Version State Address */ { device_t dev; - u32 dword; - u8 byte; - dev = - dev_find_slot(bus_sb600[0], - PCI_DEVFN(sbdn_sb600 + 0x14, 0)); + dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0)); if (dev) { - dword = pci_read_config32(dev, 0x74) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sb600, 0x11, dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = pci_read_config32(dev, 0xac); - dword &= ~(7 << 26); - dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ - /* dword |= 1<<22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ + struct resource *res; + res = find_resource(dev, 0x74); + smp_write_ioapic(mc, apicid_sb600, 0x20, res->base); } } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0); - - /* PCI interrupts are level triggered, and are - * associated with a specific bus/device/function tuple. - */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) -#else -#define PCI_INT(bus, dev, fn, pin) -#endif - - /* usb */ - PCI_INT(0x0, 0x13, 0x0, 0x10); - PCI_INT(0x0, 0x13, 0x1, 0x11); - PCI_INT(0x0, 0x13, 0x2, 0x12); - PCI_INT(0x0, 0x13, 0x3, 0x13); - - /* sata */ - PCI_INT(0x0, 0x12, 0x0, 0x16); - - /* HD Audio: b0:d20:f1:reg63 should be 0. */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* on board NIC & Slot PCIE. */ - PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12); - PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13); - PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12); - PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13); - PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10); - PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11); - PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12); - PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13); - - /* PCI slots */ - /* PCI_SLOT 0. */ - PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* Compute the checksums */ mc->mpe_checksum = @@ -162,9 +77,19 @@ return smp_next_mpe_entry(mc); } +static void fixup_virtual_wire(void *v) +{ + struct intel_mp_floating *mf = v; + + mf->mpf_checksum = 0; + mf->mpf_feature2 = MP_FEATURE_VIRTUALWIRE; + mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16); +} + unsigned long write_smp_table(unsigned long addr) { void *v; v = smp_write_floating_table(addr); + fixup_virtual_wire(v); return (unsigned long)smp_write_config_table(v); } Modified: trunk/src/mainboard/siemens/sitemp_g1p1/resourcemap.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/resourcemap.c Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/resourcemap.c Wed May 11 09:47:43 2011 (r6567) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void setup_dbm690t_resource_map(void) +static void setup_sitemp_resource_map(void) { static const unsigned int register_values[] = { /* Careful set limit registers before base registers which contain the enables */ Modified: trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Tue May 10 23:53:13 2011 (r6565) +++ trunk/src/mainboard/siemens/sitemp_g1p1/romstage.c Wed May 11 09:47:43 2011 (r6567) @@ -2,6 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Siemens AG, Inc. + * (Written by Josef Kellermann <joseph.kellermann(a)heitec.de> for Siemens AG, Inc.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,10 +18,14 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #define RC0 (6<<8) #define RC1 (7<<8) +#define DIMM0 0x50 +#define DIMM1 0x51 + +#define ICS951462_ADDRESS 0x69 #define SMBUS_HUB 0x71 #include <stdint.h> @@ -31,25 +37,36 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> + #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" + #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/early_serial.c" -#include <spd.h> -#include <usbdebug.h> + #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" + #include "northbridge/amd/amdk8/setup_resource_map.c" + #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} +/* called in raminit_f.c */ +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +/*called in raminit_f.c */ static inline int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); @@ -67,6 +84,135 @@ #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c" +#define __WARNING__(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg) +#define __DEBUG__(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) +#define __INFO__(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg) + +#if CONFIG_USE_OPTION_TABLE +#define DUMP_CMOS_RAM 0 +static inline int cmos_error(void) { + unsigned char reg_d; + /* See if the cmos error condition has been flagged */ + outb(0xd, 0x72); + reg_d = inb(0x73); +#if DUMP_CMOS_RAM + __DEBUG__("RTC_VRT = %x\n", reg_d & RTC_VRT); +#endif + return (reg_d & RTC_VRT) == 0; +} + +static inline void set_chksum(int range_start, int range_end, int cks_loc) +{ + int addr; + unsigned sum; + sum = 0; + for( addr = range_start; addr <= range_end; addr++) { + outb(addr, 0x72); + sum += inb(0x73); + } + sum = ~(sum & 0x0ffff); + outb(cks_loc, 0x72); + outb(((sum >> 8) & 0x0ff),0x73); + outb(cks_loc+1,0x72); + outb((sum & 0x0ff),0x73); +} + +static inline int cmos_chksum_valid(void) { + unsigned char addr, val; + unsigned long sum, old_sum; + +#if DUMP_CMOS_RAM + u8 i; + /* Compute the cmos checksum */ + for (addr = 14, i = 0; addr < LB_CKS_RANGE_START; addr++,i++) { + outb(addr, 0x72); + val = inb(0x73); + if( i%16 == 0 ) __DEBUG__("%02x:", addr); + __DEBUG__(" %02x",val); + if( i%16 == 15 ) __DEBUG__("\n"); + } +#endif + sum = 0; + for(addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) { + outb(addr, 0x72); + val = inb(0x73); +#if DUMP_CMOS_RAM + if( i%16 == 0 ) __DEBUG__("%02x:", addr); + __DEBUG__(" %02x",val); + if( i%16 == 15 ) __DEBUG__("\n"); + i++; +#endif + sum += val; + } +#if DUMP_CMOS_RAM + __DEBUG__("\n"); +#endif + sum = (sum & 0xffff) ^ 0xffff; + + /* Read the stored checksum */ + outb(LB_CKS_LOC, 0x72); + old_sum = inb(0x73) << 8; + outb(LB_CKS_LOC+1, 0x72); + old_sum |= inb(0x73); +#if DUMP_CMOS_RAM + __DEBUG__("CMOS checksum: old = %lx, new = %lx\n", old_sum, sum); +#endif + return sum == old_sum; +} + +#include <cbfs.h> +static inline void check_cmos( void ) { + + char *cmos_default = NULL; + int i; +#if DUMP_CMOS_RAM + u8 c = 0; +#endif + if (cmos_error() || !cmos_chksum_valid()) { + cmos_default = cbfs_find_file("cmos.default", 0xaa); + if (cmos_default) { +#if DUMP_CMOS_RAM + __DEBUG__("Write cmos default ...\n"); +#endif + outb(0x0a,0x72); + i = inb(0x73); + i &= ~(1 << 4); + outb(i,0x73); + + for (i = 14; i < 128; i++) { +#if DUMP_CMOS_RAM + if( c%16 == 0 ) __DEBUG__("%02x:", i); + __DEBUG__(" %02x", (u8)cmos_default[i]); + if( c%16 == 15 ) __DEBUG__("\n"); + c++; +#endif + outb(i,0x72); + outb(cmos_default[i],0x73); + } + +#if DUMP_CMOS_RAM + __DEBUG__("\n"); +#endif + if( !cmos_chksum_valid() ) + __DEBUG__("CMOS CHECKSUM ERROR\n"); + /* Now reboot to run with default cmos. */ + outb(0x06, 0xcf9); + for (;;) asm("hlt"); /* Wait for reset! */ + } + } + + // update altcentury + outb(0x32, 0x72); + i = inb(0x73); + if ( i != 0x20 ) { + outb(0x20,0x73); + set_chksum(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC); + } + +} + +#endif + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; @@ -75,31 +221,41 @@ msr_t msr; struct cpuid_result cpuid1; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); + /* sb600_lpc_port80(); */ sb600_pci_port80(); } - if (bist == 0) + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } - enable_rs690_dev8(); + enable_rs690_dev8(); // enable CFG access to Dev8, which is the SB P2P Bridge sb600_lpc_init(); - +#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0) + check_cmos(); // rebooting in case of corrupted cmos !!!!! +#endif /* it8712f_enable_serial does not use its 1st parameter. */ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + it8712f_kill_watchdog(); + uart_init(); console_init(); - +#if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1) + check_cmos(); // rebooting in case of corrupted cmos !!!!! +#endif + post_code(0x03); + /* Halt if there was a built in self test failure */ report_bist_failure(bist); - printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); + __DEBUG__("bsp_apicid=0x%x\n", bsp_apicid); - setup_dbm690t_resource_map(); + setup_sitemp_resource_map(); setup_coherent_ht_domain(); @@ -115,14 +271,17 @@ /* run _early_setup before soft-reset. */ rs690_early_setup(); sb600_early_setup(); - + + post_code(0x04); + /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); - if ((cpuid1.edx & 0x6) == 0x6) { + if( (cpuid1.edx & 0x6) == 0x6 ) { + /* Read FIDVID_STATUS */ msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + __DEBUG__("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); @@ -130,31 +289,47 @@ /* show final fid and vid */ msr=rdmsr(0xc0010042); - printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + __DEBUG__("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + } else { - printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); + __DEBUG__("Changing FIDVID not supported\n"); } - + + post_code(0x05); + needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs690_htinit(); - printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); - + __DEBUG__("needs_reset=0x%x\n", needs_reset); + + post_code(0x06); + if (needs_reset) { - print_info("ht reset -\n"); + __INFO__("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now; */ - printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n", + __DEBUG__("sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n", sysinfo->nodes, sysinfo->ctrl, spd_addr); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + post_code(0x07); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - - rs690_before_pci_init(); + + post_code(0x08); + + rs690_before_pci_init(); // does nothing sb600_before_pci_init(); + +#if CONFIG_USE_OPTION_TABLE + if( read_option(CMOS_VSTART_cmos_defaults_loaded, CMOS_VLEN_cmos_defaults_loaded, 0) ) + __WARNING__("WARNING: CMOS DEFAULTS LOADED. PLEASE CHECK CMOS OPTION \"cmos_default_loaded\" !\n"); +#endif post_cache_as_ram(); } + [View Less]

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[commit] r6566 - trunk/src/northbridge/amd/amdk8
by repository service 11 May '11

11 May '11

Author: oxygene Date: Wed May 11 09:44:27 2011 New Revision: 6566 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6566 Log: Work around unclean CMOS handling for now Stefan switched away from #ifdef across the tree (and is absolutely right with that), but unfortunately there are some special cases that trigger in even more special situations. Revert one such change selectively. It's destined to go once CMOS is reworked. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de… [View More]

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[PATCHes] Adopt coreboot build system for libpayload
by Patrick Georgi 11 May '11

11 May '11

[resend] Hi, attached patches change libpayload to use the coreboot build system copied into libpayload. Among the advantages is that it simplifies building a more standard set of libraries (eg. libcurses, libc, libpci) which simplifies porting code to libpayload a bit (as Makefiles can be used with fewer changes). For compatibility purposes, the build system still generates a libpayload.a, which is simply a superset over all other libraries. The first patch changes the build system to the … [View More]

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[PATCH] Replace the values of APIC timer init with macros
by Vikram Narayanan 11 May '11

11 May '11

This replaces the fixed shift values in the apic timer init with macros. Signed-off by: Vikram Narayanan <vikram186(a)gmail.com> --- --- a/src/cpu/x86/lapic/apic_timer.c Sun May 8 00:18:12 2011 +++ b/src/cpu/x86/lapic/apic_timer.c Sun May 8 00:08:54 2011 @@ -36,7 +36,7 @@ msr_t fsb_clock_sts; /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17) | (1<< 16) | (0 << 12) | (0 << 0)); + lapic_write(LAPIC_LVTT, (… [View More]

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[PATCH] Hide CMOS_VSTART_ and CMOS_VLEN_ prefixes for read_option() use
by Patrick Georgi 11 May '11

11 May '11

[let's try again] Hi, as a first step to the CMOS infrastructure project (as detailed in the wiki), this patch changes read_option() by wrapping it in a macro, simplifying its use from read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault) to read_option(foo, somedefault) Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>

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coreboot May 2011