coreboot May 2011

coreboot@coreboot.org

62 participants
161 discussions

[commit] r6565 - in trunk/src: cpu/amd/dualcore cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/quadcore include/pc80 lib mainboard/getac/p470 mainboard/kontron/986lcd-m mainboard/roda/rk886ex northb...
by repository service 10 May '11

10 May '11

Author: oxygene Date: Tue May 10 23:53:13 2011 New Revision: 6565 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6565 Log: Change read_option() to a macro that wraps some API uglyness Simplify read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault) to read_option(foo, somedefault) Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/cpu/amd/dualcore/dualcore.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/cpu/amd/quadcore/quadcore.c trunk/src/include/pc80/mc146818rtc.h trunk/src/lib/uart8250.c trunk/src/mainboard/getac/p470/romstage.c trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c trunk/src/northbridge/amd/amdk8/coherent_ht.c trunk/src/northbridge/amd/amdk8/raminit.c trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/intel/e7520/raminit.c trunk/src/northbridge/intel/e7525/raminit.c trunk/src/pc80/mc146818rtc_early.c Modified: trunk/src/cpu/amd/dualcore/dualcore.c ============================================================================== --- trunk/src/cpu/amd/dualcore/dualcore.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/cpu/amd/dualcore/dualcore.c Tue May 10 23:53:13 2011 (r6565) @@ -49,7 +49,7 @@ unsigned nodes; unsigned nodeid; - if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0)) { + if (read_option(multi_core, 0)) { return; // disable multi_core } Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue May 10 23:53:13 2011 (r6565) @@ -72,7 +72,7 @@ nodes = get_nodes(); if (!CONFIG_LOGICAL_CPUS || - read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 means multi core + read_option(multi_core, 0) != 0) { // 0 means multi core disable_siblings = 1; } else { disable_siblings = 0; Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Tue May 10 23:53:13 2011 (r6565) @@ -25,7 +25,7 @@ nodes = get_nodes(); if (!CONFIG_LOGICAL_CPUS || - read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 means multi core + read_option(multi_core, 0) != 0) { // 0 means multi core disable_siblings = 1; } else { disable_siblings = 0; Modified: trunk/src/cpu/amd/quadcore/quadcore.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/cpu/amd/quadcore/quadcore.c Tue May 10 23:53:13 2011 (r6565) @@ -82,7 +82,7 @@ u32 nodeid; // disable multi_core - if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { + if (read_option(multi_core, 0) != 0) { printk(BIOS_DEBUG, "Skip additional core init\n"); return; } Modified: trunk/src/include/pc80/mc146818rtc.h ============================================================================== --- trunk/src/include/pc80/mc146818rtc.h Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/include/pc80/mc146818rtc.h Tue May 10 23:53:13 2011 (r6565) @@ -110,15 +110,16 @@ void rtc_init(int invalid); #if CONFIG_USE_OPTION_TABLE int get_option(void *dest, const char *name); -unsigned read_option(unsigned start, unsigned size, unsigned def); +unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); #else static inline int get_option(void *dest __attribute__((unused)), const char *name __attribute__((unused))) { return -2; } -static inline unsigned read_option(unsigned start, unsigned size, unsigned def) +static inline unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) { return def; } #endif #else #include <pc80/mc146818rtc_early.c> #endif +#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default)) #endif /* PC80_MC146818RTC_H */ Modified: trunk/src/lib/uart8250.c ============================================================================== --- trunk/src/lib/uart8250.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/lib/uart8250.c Tue May 10 23:53:13 2011 (r6565) @@ -99,7 +99,7 @@ static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 }; unsigned b_index = 0; #if defined(__PRE_RAM__) - b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0); + b_index = read_option(baud_rate, 0); b_index &= 7; div = divisor[b_index]; #else Modified: trunk/src/mainboard/getac/p470/romstage.c ============================================================================== --- trunk/src/mainboard/getac/p470/romstage.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/mainboard/getac/p470/romstage.c Tue May 10 23:53:13 2011 (r6565) @@ -83,7 +83,7 @@ static void ich7_enable_lpc(void) { int lpt_en = 0; - if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { + if (read_option(lpt, 0) != 0) { lpt_en = 1<<2; // enable LPT } // Enable Serial IRQ Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue May 10 23:53:13 2011 (r6565) @@ -59,7 +59,7 @@ static void ich7_enable_lpc(void) { int lpt_en = 0; - if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { + if (read_option(lpt, 0) != 0) { lpt_en = 1<<2; // enable LPT } // Enable Serial IRQ @@ -228,18 +228,18 @@ reg32 = FD_ACMOD|FD_ACAUD|FD_PATA; reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4; - if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) { + if (read_option(ethernet1, 0) != 0) { printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n"); reg32 |= FD_PCIE1; } - if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) { + if (read_option(ethernet2, 0) != 0) { printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n"); reg32 |= FD_PCIE2; } else { if (reg32 & FD_PCIE1) port_shuffle = 1; } - if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) { + if (read_option(ethernet3, 0) != 0) { printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n"); reg32 |= FD_PCIE3; } else { Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Tue May 10 23:53:13 2011 (r6565) @@ -70,7 +70,7 @@ static void ich7_enable_lpc(void) { int lpt_en = 0; - if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { + if (read_option(lpt, 0) != 0) { lpt_en = 1<<2; // enable LPT } // Enable Serial IRQ Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/coherent_ht.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/northbridge/amd/amdk8/coherent_ht.c Tue May 10 23:53:13 2011 (r6565) @@ -1599,7 +1599,7 @@ #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; - if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */ + if (read_option(multi_core, 0) == 0) { /* multi_core */ total_cpus = verify_dualcore(nodes); } else { Modified: trunk/src/northbridge/amd/amdk8/raminit.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/northbridge/amd/amdk8/raminit.c Tue May 10 23:53:13 2011 (r6565) @@ -548,7 +548,7 @@ if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } - if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { + if (read_option(ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); @@ -1100,7 +1100,7 @@ { unsigned long tom_k, base_k; - if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { + if (read_option(interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl); } else { printk(BIOS_DEBUG, "Interleaving disabled\n"); @@ -1530,7 +1530,7 @@ min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ - read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; + read_option(max_mem_clock, 0)]; if (bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; } Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Tue May 10 23:53:13 2011 (r6565) @@ -1108,7 +1108,7 @@ * and if so count them. */ #if defined(CMOS_VSTART_interleave_chip_selects) - if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) == 0) + if (read_option(interleave_chip_selects, 1) == 0) return 0; #else #if !CONFIG_INTERLEAVE_CHIP_SELECTS @@ -1806,7 +1806,7 @@ min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ #ifdef CMOS_VSTART_max_mem_clock - read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0) + read_option(max_mem_clock, 0) #else #if defined(CONFIG_MAX_MEM_CLOCK) CONFIG_MAX_MEM_CLOCK @@ -2375,7 +2375,7 @@ dcl |= DCL_DimmEccEn; } #ifdef CMOS_VSTART_ECC_memory - if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { + if (read_option(ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } #else // CMOS_VSTART_ECC_memory not defined Modified: trunk/src/northbridge/intel/e7520/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7520/raminit.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/northbridge/intel/e7520/raminit.c Tue May 10 23:53:13 2011 (r6565) @@ -618,7 +618,7 @@ } ecc = 2; #if CONFIG_HAVE_OPTION_TABLE - if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { + if (read_option(ECC_memory, 1) == 0) { ecc = 0; /* ECC off in CMOS so disable it */ print_debug("ECC off\n"); } else Modified: trunk/src/northbridge/intel/e7525/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7525/raminit.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/northbridge/intel/e7525/raminit.c Tue May 10 23:53:13 2011 (r6565) @@ -624,7 +624,7 @@ } ecc = 2; #if CONFIG_HAVE_OPTION_TABLE - if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) { + if (read_option(ECC_memory, 1) == 0) { ecc = 0; /* ECC off in CMOS so disable it */ print_debug("ECC off\n"); } else Modified: trunk/src/pc80/mc146818rtc_early.c ============================================================================== --- trunk/src/pc80/mc146818rtc_early.c Tue May 10 23:47:57 2011 (r6564) +++ trunk/src/pc80/mc146818rtc_early.c Tue May 10 23:53:13 2011 (r6565) @@ -92,7 +92,7 @@ return (byte & (1<<1)); } -unsigned read_option(unsigned start, unsigned size, unsigned def) +unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) { #if CONFIG_USE_OPTION_TABLE unsigned byte;

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[commit] r6564 - trunk/src/cpu/x86/lapic
by repository service 10 May '11

10 May '11

Author: oxygene Date: Tue May 10 23:47:57 2011 New Revision: 6564 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6564 Log: This replaces the fixed shift values in the apic timer init with macros. Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/cpu/x86/lapic/apic_timer.c Modified: trunk/src/cpu/x86/lapic/apic_timer.c ============================================================================== --- trunk/src/cpu/x86/lapic/apic_timer.c Tue May 10 23:42:52 2011 (r6563) +++ trunk/src/cpu/x86/lapic/apic_timer.c Tue May 10 23:47:57 2011 (r6564) @@ -36,7 +36,7 @@ msr_t fsb_clock_sts; /* Set the apic timer to no interrupts and periodic mode */ - lapic_write(LAPIC_LVTT, (1 << 17) | (1<< 16) | (0 << 12) | (0 << 0)); + lapic_write(LAPIC_LVTT, (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)); /* Set the divider to 1, no divider */ lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);

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[commit] r6563 - trunk/util/options
by repository service 10 May '11

10 May '11

Author: oxygene Date: Tue May 10 23:42:52 2011 New Revision: 6563 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6563 Log: Fix compilation error due to non-unix style line endings in cmos.layout file while generating option_table.h. Windows, Mac and *nix type line endings are now taken care of. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Acked-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Modified: trunk/util/options/build_opt_tbl.c Modified: trunk/util/options/build_opt_tbl.c ============================================================================== --- trunk/util/options/build_opt_tbl.c Mon May 9 22:53:38 2011 (r6562) +++ trunk/util/options/build_opt_tbl.c Tue May 10 23:42:52 2011 (r6563) @@ -276,6 +276,7 @@ int enum_length; int len; char buf[16]; + char val; for(i=1;i<argc;i++) { if(argv[i][0]!='-') { @@ -371,8 +372,9 @@ } /* skip commented and blank lines */ - if(line[0]=='#') continue; - if(line[strspn(line," ")]=='\n') continue; + val = line[strspn(line," ")]; + /* takes care of *nix, Mac and Windows line ending formats */ + if (val=='#' || val=='\n' || val=='\r') continue; /* scan in the input data */ sscanf(line,"%d %d %c %d %s", &ce->bit,&ce->length,&uc,&ce->config_id,&ce->name[0]);

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[RFC] src/drivers/generic/generic used but not there
by Stefan Reinauer 10 May '11

10 May '11

Hi, Looking for drivers/generic/generic in the source code, we use it quite a lot: grep generic.generic src/mainboard/*/*/devicetree.cb |wc -l 391 However: ls src/drivers/generic/ Kconfig Makefile.inc debug It does not exist. Should we drop all those sub trees? Or try to fix them? What is needed to fix them?

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Re: [coreboot] Lenovo T60 coreboot build error
by Josh Stump 10 May '11

10 May '11

I have attempted using Advanced Mode, I get the same error when I click "Advanced Settings"... Corrupted interface descriptors in the new BIOS file. Part Table Signature not found in the Interface. Error code: -161 I will consider trying phlash16... On Tue, May 10, 2011 at 11:13 AM, Scott Duplichan <scott(a)notabs.org> wrote: > Josh Stump wrote: > > ] Any chances of being able to use a Windows based utility to flash, > ] I tried with Pheonix WinPhlash but it gave an error.... > > The advanced mode of WinPhlash might help. You could uncheck "Verify BIOS > part number" > and "Verify BIOS checksum". The help file shows how to enable advanced mode > by adding > Advanced=1 to the [UI] section of phlash.ini. If that doesn't work, you > could try the 16-bit > version (phlash16.exe). > > Even if this lets you flash coreboot using software, you still need a way > to > recover in > case you end up in a non-booting state. > > Thanks, > Scott > > > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Lenovo T60 coreboot build error
by Josh Stump 10 May '11

10 May '11

This is with svn checkout of version 6561 - I have tried with Seabios stable & Seabios master but get the same error. Building under Ubuntu 11.04 64 bit Makefile:225: warning: overriding commands for target `build/cpu/x86/name/name.ramstage.o' Makefile:225: warning: ignoring old commands for target `build/cpu/x86/name/name.ramstage.o' GEN bootblock/ldscript.ld LINK bootblock.elf OBJCOPY coreboot.bootblock CC lib/memset.romstage.o CC lib/memcpy.romstage.o CC lib/memcmp.romstage.o CC lib/cbfs.romstage.o CC lib/lzma.romstage.o CC lib/ramtest.romstage.o CC lib/cbmem.romstage.o CC lib/uart8250.romstage.o CC console/vtxprintf.romstage.o GEN build.h CC console/console.romstage.o CC console/post.romstage.o CC console/die.romstage.o CC romstage.inc POST romstage.inc GEN romstage/crt0.S CC mainboard/lenovo/t60/crt0.s CC mainboard/lenovo/t60/crt0.romstage.o CC mainboard/lenovo/t60/dock.romstage.o CC arch/x86/lib/romstage_console.romstage.o CC arch/x86/lib/cbfs_and_run.romstage.o CC southbridge/intel/i82801gx/early_smbus.romstage.o CC northbridge/intel/i945/udelay.romstage.o CC northbridge/intel/i945/raminit.romstage.o CC northbridge/intel/i945/early_init.romstage.o CC northbridge/intel/i945/errata.romstage.o CC northbridge/intel/i945/debug.romstage.o GEN romstage/ldscript.ld LINK coreboot.romstage CBFS coreboot.pre CC arch/x86/lib/c_start.ramstage.o CC console/uart8250_console.driver.o CC ec/lenovo/h8/h8.driver.o CC ec/lenovo/pmh7/pmh7.driver.o CC southbridge/intel/i82801gx/i82801gx.driver.o CC southbridge/intel/i82801gx/ac97.driver.o CC southbridge/intel/i82801gx/azalia.driver.o CC southbridge/intel/i82801gx/ide.driver.o CC southbridge/intel/i82801gx/lpc.driver.o CC southbridge/intel/i82801gx/nic.driver.o CC southbridge/intel/i82801gx/pci.driver.o CC southbridge/intel/i82801gx/pcie.driver.o CC southbridge/intel/i82801gx/sata.driver.o CC southbridge/intel/i82801gx/smbus.driver.o CC southbridge/intel/i82801gx/usb.driver.o CC southbridge/intel/i82801gx/usb_ehci.driver.o CC southbridge/ti/pci1x2x/pci1x2x.driver.o CC northbridge/intel/i945/northbridge.driver.o CC northbridge/intel/i945/gma.driver.o CC cpu/intel/model_69x/model_69x_init.driver.o CC cpu/intel/model_6dx/model_6dx_init.driver.o CC cpu/intel/model_6ex/model_6ex_init.driver.o CC cpu/intel/model_6fx/model_6fx_init.driver.o CC mainboard/lenovo/t60/static.ramstage.o CC lib/memset.ramstage.o CC lib/memcpy.ramstage.o CC lib/memcmp.ramstage.o CC lib/memmove.ramstage.o CC lib/malloc.ramstage.o CC lib/delay.ramstage.o CC lib/fallback_boot.ramstage.o CC lib/compute_ip_checksum.ramstage.o CC lib/version.ramstage.o CC lib/cbfs.ramstage.o CC lib/lzma.ramstage.o CC lib/gcc.ramstage.o CC lib/clog2.ramstage.o CC lib/cbmem.ramstage.o CC lib/uart8250.ramstage.o CC boot/hardwaremain.ramstage.o CC boot/selfboot.ramstage.o CC console/printk.ramstage.o CC console/console.ramstage.o CC console/vtxprintf.ramstage.o CC console/vsprintf.ramstage.o CC console/post.ramstage.o CC console/die.ramstage.o CC devices/device.ramstage.o CC devices/root_device.ramstage.o CC devices/device_util.ramstage.o CC devices/pci_device.ramstage.o CC devices/pcix_device.ramstage.o CC devices/pciexp_device.ramstage.o CC devices/agp_device.ramstage.o CC devices/cardbus_device.ramstage.o CC devices/pnp_device.ramstage.o CC devices/pci_ops.ramstage.o CC devices/smbus_ops.ramstage.o CC devices/pci_rom.ramstage.o CC mainboard/lenovo/t60/mainboard.ramstage.o CC mainboard/lenovo/t60/mptable.ramstage.o CC mainboard/lenovo/t60/irq_tables.ramstage.o CC mainboard/lenovo/t60/acpi_tables.ramstage.o IASL build/mainboard/lenovo/t60/dsdt.ramstage.o Intel ACPI Component Architecture ASL Optimizing Compiler version 20100528 [Oct 15 2010] Copyright (c) 2000 - 2010 Intel Corporation Supports ACPI Specification Revision 4.0a ASL Input: build/mainboard/lenovo/t60/dsdt.ramstage.asl - 2334 lines, 42093 bytes, 1027 keywords AML Output: build/mainboard/lenovo/t60/dsdt.aml - 11765 bytes, 471 named objects, 556 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 386 Optimizations CC mainboard/lenovo/t60/fadt.ramstage.o CC pc80/mc146818rtc.ramstage.o CC pc80/isa-dma.ramstage.o CC pc80/i8259.ramstage.o CC pc80/keyboard.ramstage.o CC devices/oprom/x86.ramstage.o CC devices/oprom/x86_asm.ramstage.o CC devices/oprom/x86_interrupts.ramstage.o CC ec/acpi/ec.ramstage.o CC arch/x86/boot/boot.ramstage.o CC arch/x86/boot/coreboot_table.ramstage.o CC arch/x86/boot/multiboot.ramstage.o CC arch/x86/boot/gdt.ramstage.o CC arch/x86/boot/tables.ramstage.o CC arch/x86/boot/mpspec.ramstage.o CC arch/x86/boot/pirq_routing.ramstage.o CC arch/x86/boot/acpi.ramstage.o CC arch/x86/boot/acpigen.ramstage.o CC arch/x86/boot/wakeup.ramstage.o CC arch/x86/lib/cpu.ramstage.o CC arch/x86/lib/pci_ops_conf1.ramstage.o CC arch/x86/lib/pci_ops_conf2.ramstage.o CC arch/x86/lib/pci_ops_mmconf.ramstage.o CC arch/x86/lib/pci_ops_auto.ramstage.o CC arch/x86/lib/exception.ramstage.o CC arch/x86/lib/ioapic.ramstage.o CC pc80/vga/vga_io.ramstage.o CC southbridge/intel/i82801gx/reset.ramstage.o CC southbridge/intel/i82801gx/watchdog.ramstage.o CC southbridge/intel/i82801gx/smi.ramstage.o CC northbridge/intel/i945/acpi.ramstage.o CC superio/nsc/pc87382/superio.ramstage.o CC superio/nsc/pc87384/superio.ramstage.o CC cpu/intel/socket_mFCPGA478/socket_mFCPGA478.ramstage.o CC cpu/x86/mtrr/mtrr.ramstage.o CC cpu/x86/lapic/lapic.ramstage.o CC cpu/x86/lapic/lapic_cpu_init.ramstage.o CC cpu/x86/lapic/secondary.ramstage.o CC cpu/x86/lapic/apic_timer.ramstage.o CC cpu/x86/cache/cache.ramstage.o CC lib/memcpy.smm.o CC lib/uart8250.smm.o CC console/printk.smm.o CC console/vtxprintf.smm.o CC mainboard/lenovo/t60/mainboard_smi.smm.o CC mainboard/lenovo/t60/dock.smm.o CC ec/acpi/ec.smm.o CC southbridge/intel/i82801gx/smihandler.smm.o CC northbridge/intel/i945/udelay.smm.o CC cpu/x86/smm/smmhandler.smm.o CC cpu/x86/smm/smihandler.smm.o CC cpu/x86/smm/smiutil.smm.o OBJCOPY cpu/x86/smm/smm_wrap.ramstage.o CC cpu/x86/smm/smmrelocate.ramstage.o CC cpu/intel/microcode/microcode.ramstage.o CC cpu/intel/hyperthreading/intel_sibling.ramstage.o CC cpu/intel/speedstep/acpi.ramstage.o CC cpu/x86/name/name.ramstage.o AR coreboot.a CC coreboot_ram.o CC coreboot_ram GIT SeaBIOS origin/master Switched to branch 'master' Deleted branch coreboot (was 1efb10b). Branch coreboot set up to track remote branch master from origin. Switched to a new branch 'coreboot' CONFIG SeaBIOS origin/master Build default config # # configuration written to /home/josh/bios/coreboot/payloads/external/SeaBIOS/seabios/.config # MAKE SeaBIOS origin/master Build Kconfig config file /home/josh/bios/coreboot/payloads/external/SeaBIOS/seabios/.config:77:warning: override: reassigning to symbol COREBOOT /home/josh/bios/coreboot/payloads/external/SeaBIOS/seabios/.config:78:warning: override: reassigning to symbol DEBUG_SERIAL # # configuration written to /home/josh/bios/coreboot/payloads/external/SeaBIOS/seabios/.config # Compiling whole program out/ccode.16.s Compiling to assembler out/asm-offsets.s Generating offset file out/asm-offsets.h Compiling (16bit) out/code16.o Compiling whole program out/ccode32flat.o Compiling whole program out/code32seg.o Building ld scripts (version "pre-0.6.3-20110509_113214-josh-laptop") Fixed space: 0xe05b-0x10000 total: 8101 slack: 3 Percent slack: 0.0% 16bit size: 39456 32bit segmented size: 2412 32bit flat size: 13972 32bit flat init size: 39392 Linking out/rom16.o out/romlayout16.lds:705 cannot move location counter backwards (from 000000000000ca88 to 000000000000ca6c) make[2]: *** [out/rom16.o] Error 1 make[1]: *** [seabios] Error 2 make: *** [seabios] Error 2

4 9

news about coreboot & llano Fudzilla.com
by Knut Kujat 10 May '11

10 May '11

Hi everyone, FYI: http://www.fudzilla.com/processors/item/22677-amd-to-use-coreboot-in-llano-… Bye, Knut Kujat.

2 1

[PATCH] RS690 code booting RS740 with ECS A740GM-M
by Ivaylo Valkov 09 May '11

09 May '11

Adds RS740 HT and internal graphics PCI ids. Adds support for RS740 in RS690 code (some of the fam10 code from RS780). Adds support for ECS A740GM-M. This definitely needs more patches and fine-tuning. Only tested on RS740. Signed-off-by: Ivaylo Valkov <ivaylo(a)e-valkov.org> --- Hello all, And thank you for all the work you have done so far. This is kind of long e-mail, so for the impatient - with these patches I am able to initialize the RS740 chipset on the ECS A740GM-M motherboard and boot GNU/Linux (with Xorg), but the code definitely needs more fine-tuning and patching. All my hardware died recently, so I bought two identical ECS A740GM-M [1] replacement boards with AMD RS740/740G chipset as an opportunity to help the coreboot project gather some information. The requested information for flashrom and the RS740 chipset is attached. One thing led to another and I've gone a lot further - the board seems usable. Flashrom works on the board. The flash chip is recognised as MX25L8005, but it is actually [2] MX25L8006. [3] In spite of that I was able to flash it and boot the proprietary BIOS and coreboot. I've experienced some CMOS checksum errors with the proprietary BIOS after flashing, but everything worked fine after setting the date. This does not happen always and I can't see a pattern when it does. Should I post the flashrom related information on the flashrom mailing list? With flashrom working and the information on this list (and few other places) that the RS740 is RS690 with new graphics I decided to test the RS690 code on the board. So, after nearly a month of cut-and-paste from mahogany_fam10 and dmb690t, new code in RS690, borrowed from RS780, ACPI from mahogany_fam10 for the board and some modifications I ended up with something usable. The CPU is Sempron 140 (AM3/AM2+ socket). I have some basic and blurry understanding of the boot process. I do not know why exactly all that I've done worked. It is fair to say that I have read almost zero documentation. All was achieved only by reading the available code and observing the logic. Maybe it wasn't the smartest and safest thing to do, but worth it. So carefully review the code. Some of it is there so I could build. It might be irrelevant. Patches are attached. I used a cmos.layout from mahogany_fam10 to build, but images with enabled CONFIG_USE_OPTION_TABLE (use CMOS/NVRAM values instead of hard coded ones) in menuconfig do not boot at all - not even single serial line of output. With recent changes and the move of CMOS to CBFS I can't build with that option. I am able to boot GNU/Linux. USB, network, sound, ATA and SATA are working. PCI worked with external graphic and network card. PCIe is not tested. The master and stable releases of SeaBIOS hang when there is a USB mouse connected after printing "USB mouse initialized". USB works fine under GNU/Linux. HT is initialized to 200MHz. The lspci output (also attached) after coreboot loads, shows that 1.6GHz link frequency is possible. The documented limit for RS690 is 1GHz. The RS780 code is implemented differently, so it has k8 and fam10 support. Do you think it will be possible to use something from RS780 code? I am not confident and competent to make the changes myself, but I am willing to test patches (any). The lspci output for the board with coreboot running differs(in places). I think it is ACPI and devicetree.cb related. Don't know how to fix it right now. After coreboot initializes the board, the CPU has two states - 1.9 GHz and 2.7GHz. With proprietary BIOS the CPU can do two more - 1.5GHz and 800MHz. That is ACPI issue, righ? Before adding ACPI the only possible frequency was 2.7GHz. The code that prints the CPU revision (in get_cpu_revision) is taken from RS780. I think it prints (only that!) wrong revision - "K8_10" instead of "Fam 10". It seems it should be "eax <= 0x100fff" instead of "eax <= 0x100f00", but as I've said I didn't read enough documentation. I've extracted a VGA BIOS image from the proprietary BIOS and the internal graphics card worked. Both DVI and VGA connectors work. Xorg loads, but if the resolution is higher than or equal to 1024x768 the screen flickers and I see horizontal lines. [4] When the display is refreshed (key press, mouse move, by programs) it is awful. [5] For lower resolutions it is not noticeable or even missing. This is tested on deblobed Linux-libre kernel only, and the drivers do not load the binary-blob firmware for 3D acceleration. Is it possible to initialize the internal graphics on RS690/RS740 from coreboot code and use VGA BIOS image from SeaBIOS? Like it is done for the M2V-MX SE board? Yes I know it uses VIA chipset and it has documentation. I guess what I am asking is, is it there enough documentation released by AMD to make it work. I've hacked a PCI header for the VGA BIOS image from SeaBIOS, so it can be loaded by coreboot (vendor/device ID complains). The ROM is loaded, but SeaBIOS hangs. Not that I was expecting to just work. There are microcode patches for some CPUs that are non-free binary-blobs (examine their license headers). Is it possible to make loading such microcode configurable? I am unable to build the fam10 code without a microcode filename. I understand that AMD (and other companies) might not want to release such information for various reasons, but I prefer to use "crippled" CPU instead of non-free microcode, when I am running free software BIOS. Do I really need them for Sempron anyway? It works without them. Didn't notice any difference in performance with them. Not that the current state of the board can be used for measuring performance. The work-around I am using right now is zero-filled microcode patch file in the board directory, that does nothing. Images of the board and the chips can be found on my "web site" [6]. I've copied the copyright notices from files that had such and I've used code from. For the rest I've put a comment pointing to the file I've borrowed from. Hope that is the right way to do it. Unfortunately the code I used restricts me to GPLv2 only, I prefer GPLv2(or later). What is the policy on GPLv3 (or later) code for that matter? Just thinking for possible future contributions. P.S. This is a lot of information (and issues). If anything has to go in the issue tracker I will do it. [1] http://www.ecs.com.tw/ECSWebSite/Product/Product_Detail.aspx?CategoryID=1&D… [2] http://e-valkov.org/coreboot/ecs-a740gm-m-bios-chip.jpg [3] http://www.mxic.com.tw/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Inde… [4] http://e-valkov.org/coreboot/video-card-1.ogv [5] http://e-valkov.org/coreboot/video-card-2.ogv [6] http://e-valkov.org/coreboot/

4 10

[commit] r6562 - trunk/src/include/device
by repository service 09 May '11

09 May '11

Author: mjones Date: Mon May 9 22:53:38 2011 New Revision: 6562 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6562 Log: Adds RS740 HT and internal graphics PCI ids. Signed-off-by: Ivaylo Valkov <ivaylo(a)e-valkov.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/include/device/pci_ids.h Modified: trunk/src/include/device/pci_ids.h ============================================================================== --- trunk/src/include/device/pci_ids.h Sat May 7 11:15:02 2011 (r6561) +++ trunk/src/include/device/pci_ids.h Mon May 9 22:53:38 2011 (r6562) @@ -332,6 +332,7 @@ #define PCI_DEVICE_ID_ATI_SB800_GEC 0x1699 #define PCI_DEVICE_ID_ATI_RS690_HT 0x7910 +#define PCI_DEVICE_ID_ATI_RS740_HT 0x7911 #define PCI_DEVICE_ID_ATI_RS690_PCIE 0x7912 #define PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2 0x7913 #define PCI_DEVICE_ID_ATI_RS690_PCIE_DEV3 0x791B @@ -342,6 +343,7 @@ #define PCI_DEVICE_ID_ATI_RS690_PCIE_DEV8 0x7918 #define PCI_DEVICE_ID_ATI_RS690_INT_GFX 0x791e #define PCI_DEVICE_ID_ATI_RS690MT_INT_GFX 0x791f +#define PCI_DEVICE_ID_ATI_RS740_INT_GFX 0x796e #define PCI_DEVICE_ID_AMD_RS780_HT 0x9600 #define PCI_DEVICE_ID_AMD_RS780_PCIE 0x9602

1 0

Re: [coreboot] [PATCH] Fixes the build error while generating option_table.h
by Vikram Narayanan 09 May '11

09 May '11

> Am 08.05.2011 20:01, schrieb Peter Stuge: >> if(!strncmp(line[strspn(line," ")],"\r\n",2) continue; > More like: > char val=line[strspn(line," ")]; > if (val=='#' || val=='\n' || val=='\r') continue; > > This has the benefit of handling > " # comment" > and mac-style newlines, too. Thanks for all your comments. As Patrick suggested, here is the new patch. Signed-off by: Vikram Narayanan <vikram186(a)gmail.com> Signed-off by: Patrick Georgi <patrick(a)georgi-clan.de> --- --- C:/coreboot/util/options/build_opt_tbl.c.orig Sun May 8 22:18:54 2011 +++ C:/coreboot/util/options/build_opt_tbl.c Mon May 9 19:09:32 2011 @@ -276,6 +276,7 @@ int enum_length; int len; char buf[16]; + char val; for(i=1;i<argc;i++) { if(argv[i][0]!='-') { @@ -371,8 +372,9 @@ } /* skip commented and blank lines */ - if(line[0]=='#') continue; - if(line[strspn(line," ")]=='\n') continue; + val = line[strspn(line," ")]; + /* takes care of *nix,Mac and Windows line ending formats */ + if (val=='#' || val=='\n' || val=='\r') continue; /* scan in the input data */ sscanf(line,"%d %d %c %d %s", &ce->bit,&ce->length,&uc,&ce->config_id,&ce->name[0]); - Thanks, Vikram

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coreboot May 2011