coreboot May 2011

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[commit] r6555 - in trunk: . src/vendorcode/amd/agesa/Include
by repository service 05 May '11

05 May '11

Author: mjones Date: Thu May 5 18:45:36 2011 New Revision: 6555 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6555 Log: Remove AMD Agesa requirement for standard include files This change modifies Makefile.inc to add the -nostdinc flag to the default CFLAGS value and removes the test for non-AMD Agesa builds. Other code is added to the gcc-intrin.h file in the Agesa Include folder to make the requirement for the standard includes obsolete from the Agesa perspective. Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/Makefile.inc trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h Modified: trunk/Makefile.inc ============================================================================== --- trunk/Makefile.inc Tue May 3 09:55:43 2011 (r6554) +++ trunk/Makefile.inc Thu May 5 18:45:36 2011 (r6555) @@ -106,16 +106,13 @@ # abspath is a workaround for romcc INCLUDES += -include $(abspath $(obj)/config.h) -CFLAGS = $(INCLUDES) -Os -pipe -g +CFLAGS = $(INCLUDES) -Os -pipe -g -nostdinc CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS += -Wstrict-aliasing -Wshadow ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) CFLAGS += -Werror endif -ifneq ($(CONFIG_AMD_AGESA),y) -CFLAGS += -nostdinc -endif CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/options Modified: trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h ============================================================================== --- trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h Tue May 3 09:55:43 2011 (r6554) +++ trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h Thu May 5 18:45:36 2011 (r6555) @@ -27,8 +27,6 @@ */ #if defined (__GNUC__) -#include <pmmintrin.h> - /* I/O intrin functions. */ static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port) @@ -558,6 +556,10 @@ return value; } +#ifdef __SSE3__ +typedef long long __v2di __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__)); + static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B) { __asm__(".byte 0x64"); // fs prefix @@ -567,9 +569,10 @@ static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B) { __m128i data; - data = _mm_lddqu_si128 (__B); + data = (__m128i) __builtin_ia32_lddqu ((char const *)__B); _mm_stream_si128_fs2 (__A, data); } +#endif static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A) { @@ -577,6 +580,16 @@ __builtin_ia32_clflush (__A); } +static __inline __attribute__(( __always_inline__)) void _mm_mfence (void) +{ + __builtin_ia32_mfence (); +} + +static __inline __attribute__(( __always_inline__)) void _mm_sfence (void) +{ + __builtin_ia32_sfence (); +} + static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count) { __asm__ __volatile__ (

1 0

[PATCH] replace while with do; while to avoid repetition
by Noe Rubinstein 05 May '11

05 May '11

Cosmetic only; replaces some 'while' loops with 'do; while' loops to avoid repetition. Replacement performed by the Ruby expression: t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/, "\\1do \\2\n\\1\\3;") Signed-off-by: Noe Rubinstein <nrubinstein(a)proformatique.com> --- src/northbridge/intel/e7520/raminit.c | 55 +++++++++-------------- src/northbridge/intel/e7525/raminit.c | 55 +++++++++-------------- src/northbridge/intel/i3100/raminit.c | 55 +++++++++-------------- src/northbridge/intel/i3100/raminit_ep80579.c | 60 ++++++++++--------------- 4 files changed, 90 insertions(+), 135 deletions(-) diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index 6eed196..499698e 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -1128,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+0x100, (0x83000000 | (i<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } @@ -1139,9 +1138,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1152,9 +1150,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* EMRS dll's enabled */ @@ -1166,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000001); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* MRS reset dll's */ do_delay(); @@ -1187,9 +1183,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1202,25 +1197,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do 2 refreshes */ do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ @@ -1253,9 +1245,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do only if DDR2 EMRS dll's enabled */ @@ -1264,9 +1255,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (0x0b940001)); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } } @@ -1310,9 +1300,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Bring memory subsystem on line */ diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index aabe8cf..6eb9956 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -1104,9 +1104,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+0x100, (0x83000000 | (i<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } @@ -1115,9 +1114,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1128,9 +1126,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* EMRS dll's enabled */ @@ -1142,9 +1139,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000001); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* MRS reset dll's */ do_delay(); @@ -1163,9 +1159,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1178,25 +1173,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* DDR1 */ write32(BAR+DCALADDR, 0x00000000); write32(BAR+DCALCSR, (0x83000002 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do 2 refreshes */ do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ @@ -1229,9 +1221,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Do only if DDR2 EMRS dll's enabled */ @@ -1240,9 +1231,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (0x0b940001)); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } } @@ -1283,9 +1273,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); - data32 = read32(BAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while(data32 & 0x80000000); } /* Bring memory subsystem on line */ diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 86e610f..ced3de1 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -1020,9 +1020,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(MCBAR+DCALCSR, (0x01000000 | (i<<20))); write32(MCBAR+DCALCSR, (0x81000000 | (i<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Apply NOP */ @@ -1030,9 +1029,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1040,9 +1038,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* EMRS dll's enabled */ @@ -1051,9 +1048,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* fixme hard code AL additive latency */ write32(MCBAR+DCALADDR, 0x0b940001); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* MRS reset dll's */ do_delay(); @@ -1064,9 +1060,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, mode_reg); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Precharg all banks */ @@ -1076,25 +1071,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, 0x04000000); write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Do 2 refreshes */ do_delay(); for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); /* for good luck do 6 more */ @@ -1127,9 +1119,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24))); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Do only if DDR2 EMRS dll's enabled */ @@ -1137,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALADDR, (0x0b940001)); write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } do_delay(); @@ -1173,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(cs=0;cs<8;cs+=2) { write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20))); - data32 = read32(MCBAR+DCALCSR); - while(data32 & 0x80000000) - data32 = read32(MCBAR+DCALCSR); + do data32 = read32(MCBAR+DCALCSR); + while(data32 & 0x80000000); } /* Bring memory subsystem on line */ diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 8967594..de3ffce 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -534,9 +534,8 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21)); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } } @@ -603,9 +602,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) udelay(16); write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21))); write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* Apply NOP */ @@ -615,9 +613,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug_hex8(cs); print_debug("\n"); write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* Precharge all banks */ @@ -628,9 +625,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, 0x04000000); write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* EMRS: Enable DLLs, set OCD calibration mode to default */ @@ -641,9 +637,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* MRS: Reset DLLs */ udelay(16); @@ -653,9 +648,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* Precharge all banks */ @@ -666,9 +660,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, 0x04000000); write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* Do 2 refreshes */ @@ -679,9 +672,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug_hex8(cs); print_debug("\n"); write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } } @@ -693,9 +685,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } /* EMRS: Enable DLLs */ @@ -706,9 +697,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } udelay(16); @@ -729,9 +719,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug_hex8(cs); print_debug("\n"); write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21))); - data32 = read32(BAR+DCALCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+DCALCSR); + do data32 = read32(BAR+DCALCSR); + while (data32 & 0x80000000); } dump_dcal_regs(); @@ -756,9 +745,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug_hex8(cs); print_debug("\n"); write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16)); - data32 = read32(BAR+MBCSR); - while (data32 & 0x80000000) - data32 = read32(BAR+MBCSR); + do data32 = read32(BAR+MBCSR); + while (data32 & 0x80000000); if (data32 & 0x40000000) print_debug("failed!\n"); } -- Noé Rubinstein Proformatique (groupe Avencall) - XiVO IPBX OpenHardware 10 bis, rue Lucien VOILIN - 92800 Puteaux Tél. : +33 (0)1 41 38 99 60 ext 123 Fax. : +33 (0)1 41 38 99 70

1 0

[PATCH]Change all type declaration to uintxx_t
by Hamo 04 May '11

04 May '11

We mixed normal type declaration and uintxx_t in the definition of CBFS headers before, this may confuse newbies who want to study CBFS structure. Signed-off-by: Yang Bai <hamo.by(a)gmail.com> Index: util/cbfstool/cbfs.h =================================================================== --- util/cbfstool/cbfs.h (revision 6534) +++ util/cbfstool/cbfs.h (working copy) @@ -37,11 +37,11 @@ } __attribute__ ((packed)); struct cbfs_stage { - unsigned int compression; - unsigned long long entry; - unsigned long long load; - unsigned int len; - unsigned int memlen; + uint32_t compression; + uint64_t entry; + uint64_t load; + uint32_t len; + uint32_t memlen; } __attribute__ ((packed)); #define PAYLOAD_SEGMENT_CODE 0x45444F43 @@ -51,12 +51,12 @@ #define PAYLOAD_SEGMENT_ENTRY 0x52544E45 struct cbfs_payload_segment { - unsigned int type; - unsigned int compression; - unsigned int offset; - unsigned long long load_addr; - unsigned int len; - unsigned int mem_len; + uint32_t type; + uint32_t compression; + uint32_t offset; + uint64_t load_addr; + uint32_t len; + uint32_t mem_len; } __attribute__ ((packed)); struct cbfs_payload {

4 5

u-boot as payload
by Rudolf Marek 04 May '11

04 May '11

Hello, I wrote a blog post about this: http://blogs.coreboot.org/blog/2011/04/30/u-boot-as-coreboot-payload/ I'm attaching patches so you see what I have right now. Please consider them just a "test" I did not change the copyrights etc. Maybe they are just a big mess. Maybe you find them useful. The current problems are: 1) I have PCI resource conflicts with QEMU and coreboot This is just now a showstopper. Definetely no time to investigate right now/ 2) I have in plan to get rid of u-boot relocation by relocating it exactly 0 bytes ;) 3) I still don't know git despite F1 from Carebear ;) Thanks, Rudolf

1 2

[commit] r6553 - trunk/src/southbridge/intel/i82801gx
by repository service 03 May '11

03 May '11

Author: svens Date: Tue May 3 09:55:30 2011 New Revision: 6553 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6553 Log: i82801gx: enable SPI prefetching Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Added: trunk/src/southbridge/intel/i82801gx/bootblock.c Modified: trunk/src/southbridge/intel/i82801gx/Kconfig Modified: trunk/src/southbridge/intel/i82801gx/Kconfig ============================================================================== --- trunk/src/southbridge/intel/i82801gx/Kconfig Mon May 2 21:53:04 2011 (r6552) +++ trunk/src/southbridge/intel/i82801gx/Kconfig Tue May 3 09:55:30 2011 (r6553) @@ -38,5 +38,10 @@ int default 1 +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/intel/i82801gx/bootblock.c" + depends on SOUTHBRIDGE_INTEL_I82801GX + endif Added: trunk/src/southbridge/intel/i82801gx/bootblock.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/intel/i82801gx/bootblock.c Tue May 3 09:55:30 2011 (r6553) @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> + +static void enable_spi_prefetch(void) +{ + u8 reg8; + device_t dev; + + dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); +} + +static void bootblock_southbridge_init(void) +{ + enable_spi_prefetch(); +} +

5 6

[PATCH] Add option 'compress ramstage'
by Sven Schnelle 03 May '11

03 May '11

Add an option to make compression of ramstage configurable. Right now it is always compressed. On my Thinkpad, the complete boot to grub takes 4s, with around 1s required for decompressing ramstage. This is probably caused by the fact the decompression does a lot of single byte/word/qword accesses, which are really slow on SPI buses. So give the user the option to store ramstage uncompressed, if he has enough memory. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- Makefile.inc | 4 ++++ src/Kconfig | 8 ++++++++ 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 6c4a16a..6267539 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -85,7 +85,11 @@ cbfs-files-handler= \ ####################################################################### # a variety of flags for our build +CBFS_COMPRESS_FLAG:= +ifeq ($(CONFIG_COMPRESS_RAMSTAGE),y) CBFS_COMPRESS_FLAG:=l +endif + CBFS_PAYLOAD_COMPRESS_FLAG:= CBFS_PAYLOAD_COMPRESS_NAME:=none ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y) diff --git a/src/Kconfig b/src/Kconfig index 76e77f8..a782315 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -98,6 +98,14 @@ config USE_OPTION_TABLE Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard coded values. +config COMPRESS_RAMSTAGE + bool "Compress ramstage with LZMA" + default y + help + Compress ramstage to save memory in the flash image. Note + that decompression might slow down booting if the BIOS flash + is connected through a slow Link (i.e. SPI) + endmenu source src/mainboard/Kconfig -- 1.7.4.4

6 11

[commit] r6552 - in trunk: . src
by repository service 02 May '11

02 May '11

Author: svens Date: Mon May 2 21:53:04 2011 New Revision: 6552 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6552 Log: Add option 'compress ramstage' Add an option to make compression of ramstage configurable. Right now it is always compressed. On my Thinkpad, the complete boot to grub takes 4s, with around 1s required for decompressing ramstage. This is probably caused by the fact the decompression does a lot of single byte/word/qword accesses, which are really slow on SPI buses. So give the user the option to store ramstage uncompressed, if he has enough memory. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/Makefile.inc trunk/src/Kconfig Modified: trunk/Makefile.inc ============================================================================== --- trunk/Makefile.inc Sat Apr 30 02:22:04 2011 (r6551) +++ trunk/Makefile.inc Mon May 2 21:53:04 2011 (r6552) @@ -85,7 +85,11 @@ ####################################################################### # a variety of flags for our build +CBFS_COMPRESS_FLAG:= +ifeq ($(CONFIG_COMPRESS_RAMSTAGE),y) CBFS_COMPRESS_FLAG:=l +endif + CBFS_PAYLOAD_COMPRESS_FLAG:= CBFS_PAYLOAD_COMPRESS_NAME:=none ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y) Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Sat Apr 30 02:22:04 2011 (r6551) +++ trunk/src/Kconfig Mon May 2 21:53:04 2011 (r6552) @@ -98,6 +98,14 @@ Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard coded values. +config COMPRESS_RAMSTAGE + bool "Compress ramstage with LZMA" + default y + help + Compress ramstage to save memory in the flash image. Note + that decompression might slow down booting if the boot flash + is connected through a slow Link (i.e. SPI) + endmenu source src/mainboard/Kconfig

1 0

use gcc 4.6.0 link time optimization to reduce coreboot execution time
by Scott Duplichan 02 May '11

02 May '11

Adds a kconfig option to enable gcc link time optimization. Link time optimization reduces both rom stage and ram stage image size by removing unused functions and data. Reducing the image size saves boot time by minimizing the flash memory read and decompress time for ram stage. The option is off by default because of side effects such as long build time and unusable dwarf2 debug output. This option cuts persimmon+seabios DOS boot from SSD time from 690 ms to 640 ms. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: Makefile =================================================================== --- Makefile (revision 6549) +++ Makefile (working copy) @@ -211,7 +211,7 @@ de$(EMPTY)fine $(1)-objs_$(2)_template $(obj)/$$(1).$(1).o: src/$$(1).$(2) $(obj)/config.h $(4) @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" - $(CC) $(3) -MMD $$$$(CFLAGS) -c -o $$$$@ $$$$< + $(CC) $(3) -MMD $$$$(CFLAGS) $$$$(LTO_OPTIMIZE) -c -o $$$$@ $$$$< en$(EMPTY)def end$(EMPTY)if endef Index: Makefile.inc =================================================================== --- Makefile.inc (revision 6549) +++ Makefile.inc (working copy) @@ -66,7 +66,7 @@ $(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl iasl -p $$(obj)/$(1) -tc $$(basename $$(a)).asl mv $$(obj)/$(1).hex $$(basename $$(a)).c - $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c + $(CC) $$(CFLAGS) $$(LTO_OPTIMIZE) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c # keep %.o: %.c rule from catching the temporary .c file after a make clean mv $$(basename $$(a)).c $$(basename $$(a)).hex endef @@ -101,8 +101,17 @@ INCLUDES += -Isrc/devices/oprom/include # abspath is a workaround for romcc INCLUDES += -include $(abspath $(obj)/config.h) + +# when '-flto' is used, optimization flags must be passed to both compile and link steps +# pass $(LTO_OPTIMIZE) to compile and link steps to support the LTO_OPTIMIZE option +# use $(OPTIMIZE) to compile files not compatible with link time optimization +OPTIMIZE :=-Os -fomit-frame-pointer $(CONFIG_EXTRA_OPTIMIZE) +LTO_OPTIMIZE :=$(OPTIMIZE) +ifeq ($(CONFIG_LTO_OPTIMIZE),y) +LTO_OPTIMIZE :=$(LTO_OPTIMIZE) -flto +endif -CFLAGS = $(INCLUDES) -Os -pipe -g +CFLAGS = $(INCLUDES) -pipe -g CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS += -Wstrict-aliasing -Wshadow @@ -112,7 +121,7 @@ ifneq ($(CONFIG_AMD_AGESA),y) CFLAGS += -nostdinc endif -CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer +CFLAGS += -fno-common -ffreestanding -fno-builtin additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/options @@ -180,7 +189,7 @@ $(obj)/%.ramstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -c -o $@ $< + $(CC) -MMD $(CFLAGS) $(LTO_OPTIMIZE) -c -o $@ $< ####################################################################### # Clean up rules Index: src/arch/x86/init/bootblock.ld =================================================================== --- src/arch/x86/init/bootblock.ld (revision 6549) +++ src/arch/x86/init/bootblock.ld (working copy) @@ -22,7 +22,6 @@ OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") OUTPUT_ARCH(i386) -TARGET(binary) SECTIONS { . = CONFIG_ROMBASE; Index: src/arch/x86/Makefile.bootblock.inc =================================================================== --- src/arch/x86/Makefile.bootblock.inc (revision 6549) +++ src/arch/x86/Makefile.bootblock.inc (working copy) @@ -76,13 +76,13 @@ $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" printf "CONFIG_ROMBASE = 0x0;\nAUTO_XIP_ROM_BASE = 0x0;\n" > $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) - $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin + $(CC) $(LTO_OPTIMIZE) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) + $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt cat $(obj)/location.txt >> $(obj)/location.ld printf ';\nAUTO_XIP_ROM_BASE = CONFIG_ROMBASE & ~(CONFIG_XIP_ROM_SIZE - 1);\n' >> $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) + $(CC) $(LTO_OPTIMIZE) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug $(OBJCOPY) --strip-debug $(obj)/romstage.elf Index: src/arch/x86/Makefile.inc =================================================================== --- src/arch/x86/Makefile.inc (revision 6549) +++ src/arch/x86/Makefile.inc (working copy) @@ -136,7 +136,7 @@ $(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld #ldoptions @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $(obj)/coreboot_ram.o + $(CC) $(LTO_OPTIMIZE) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $(obj)/coreboot_ram.o $(obj)/coreboot.a $(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map $(OBJCOPY) --only-keep-debug $@ $(obj)/coreboot_ram.debug $(OBJCOPY) --strip-debug $@ @@ -232,11 +232,11 @@ $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ + $(CC) -MMD $(CFLAGS) $(OPTIMIZE) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" - $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ + $(CC) -MMD $(CFLAGS) $(OPTIMIZE) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc @printf " POST romstage.inc\n" Index: src/Kconfig =================================================================== --- src/Kconfig (revision 6549) +++ src/Kconfig (working copy) @@ -59,6 +59,14 @@ bool "LLVM/clang" endchoice +config LTO_OPTIMIZE + bool "Use gcc -flto link time optimization" + default n + depends on COMPILER_GCC + help + Use with gcc 4.6.0 or later to reduce code size by + removing unused functions and data. + config SCANBUILD_ENABLE bool "Build with scan-build for static analysis" default n

4 7

Trac reminder: list of new ticket(s)
by coreboot tracker 02 May '11

02 May '11

1 0

Fwd: use gcc 4.6.0 link time optimization to reduce coreboot execution time
by Антон Кочков 01 May '11

01 May '11

May be add something like profiling option with patch for implementing such feature? Best regards, Anton Kochkov. On Sun, May 1, 2011 at 07:37, Scott Duplichan <scott(a)notabs.org> wrote: > Kevin O'Connor wrote: > > ] That's a great boot time! Do you have a breakdown of where the 640ms > ] is spent? > ] > ] -Kevin > > Hello Kevin, > > I tried adding some serial logging to get an idea about where > the time is spent. The logging adds 8 ms to the boot time: > > Time in ms > 0 cold reset > 366 memory initialization complete > 469 seabios: maininit(void) > 483 seabios: vga_setup() called > 604 seabios: vga_setup() returned > 621 seabios: startBoot(void) > 648 dos autoexec utility logs pmtimer value > > It looks like the lengthy operations are memory init and VBIOS > execution, which is consistent with past experience. > > UEFI BIOS on this same hardware platform is taking more than > 10 seconds. > > Here seabios kconfig options I changed: > > Build for coreboot y > Hardware init during option ROM execution y > Bootmenu n > ATA controllers n > AHCI controllers y > Floppy controller n > PS/2 port n > USB UHCI controllers n > Parallel port n > PCIBIOS interface n > APM interface n > PnP BIOS interface n > S3 resume n > SMBIOS n > Serial port debugging y > Show screen writes on debug ports n > > Thanks, > Scott > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

4 3

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coreboot May 2011