coreboot May 2011

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[commit] r6559 - in trunk/src: southbridge/amd/cimx_wrapper/sb800 vendorcode/amd/cimx/sb800
by repository service 07 May '11

07 May '11

Author: kerry Date: Sat May 7 10:43:40 2011 New Revision: 6559 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6559 Log: SB800 CIMX code can share the AGESA V5 lib code, some platform only use sb800 cimx code, not use AGESA v5 code. for such platform, one can compile the sb800 cimx and AGESA v5 lib code. Signed-off-by: Kerry She <kerry.she(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sat May 7 10:37:38 2011 (r6558) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/Amd.h Sat May 7 10:43:40 2011 (r6559) @@ -161,7 +161,7 @@ IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX -} SB_CPUID_DATA; +} CPUID_DATA; #define WARM_RESET 1 #define COLD_RESET 2 // Cold reset Modified: trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h Sat May 7 10:37:38 2011 (r6558) +++ trunk/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h Sat May 7 10:43:40 2011 (r6559) @@ -104,3 +104,14 @@ * */ void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length); + + +/* SB800 CIMx and AGESA V5 can share lib functions */ +unsigned char ReadIo8(IN unsigned short Address); +unsigned short ReadIo16(IN unsigned short Address); +unsigned int ReadIo32(IN unsigned short Address); +void WriteIo8(IN unsigned short Address, IN unsigned char Data); +void WriteIo16(IN unsigned short Address, IN unsigned short Data); +void WriteIo32(IN unsigned short Address, IN unsigned int Data); +void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value); +unsigned char ReadNumberOfCpuCores(void); Modified: trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c Sat May 7 10:37:38 2011 (r6558) +++ trunk/src/vendorcode/amd/cimx/sb800/SBCMN.c Sat May 7 10:43:40 2011 (r6559) @@ -329,7 +329,7 @@ { UINT32 abValue; UINT16 dwTempVar; - SB_CPUID_DATA CpuId; + CPUID_DATA CpuId; UINT8 cimNativepciesupport; UINT8 cimIrConfig; UINT8 Data;

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[commit] r6558 - in trunk/src/vendorcode/amd/agesa: Include Lib
by repository service 07 May '11

07 May '11

Author: kerry Date: Sat May 7 10:37:38 2011 New Revision: 6558 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6558 Log: 1. move _mm_clflush_fs() to __SSE3__ block, because __builtin_ia32_sfence() is the sse built-in function 2. move the Amd Lib functions using sse build-in functions to __SSE3__ block Signed-off-by: Kerry She <kerry.she(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h trunk/src/vendorcode/amd/agesa/Lib/amdlib.c Modified: trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h ============================================================================== --- trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h Sat May 7 10:33:14 2011 (r6557) +++ trunk/src/vendorcode/amd/agesa/Include/gcc-intrin.h Sat May 7 10:37:38 2011 (r6558) @@ -572,7 +572,6 @@ data = (__m128i) __builtin_ia32_lddqu ((char const *)__B); _mm_stream_si128_fs2 (__A, data); } -#endif static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A) { @@ -589,6 +588,7 @@ { __builtin_ia32_sfence (); } +#endif static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count) { Modified: trunk/src/vendorcode/amd/agesa/Lib/amdlib.c ============================================================================== --- trunk/src/vendorcode/amd/agesa/Lib/amdlib.c Sat May 7 10:33:14 2011 (r6557) +++ trunk/src/vendorcode/amd/agesa/Lib/amdlib.c Sat May 7 10:37:38 2011 (r6558) @@ -401,6 +401,8 @@ }; ((VOID (*)(VOID)) (size_t) opcode) (); // call the function } + +#ifdef __SSE3__ VOID F10RevDProbeFilterCritical ( IN PCI_ADDR PciAddress, IN UINT32 PciRegister @@ -416,23 +418,7 @@ _mm_mfence (); __writemsr (0xC001001F, msrsave); } -VOID -IdsOutPort ( - IN UINT32 Addr, - IN UINT32 Value, - IN UINT32 Flag - ) -{ - __outdword ((UINT16) Addr, Value); -} -VOID -StopHere ( - VOID - ) -{ - VOLATILE UINTN x = 1; - while (x); -} + VOID LibAmdCLFlush ( IN UINT64 Address, @@ -450,7 +436,25 @@ } RestoreHwcr (hwcrSave); } +#endif //__SSE3__ +VOID +IdsOutPort ( + IN UINT32 Addr, + IN UINT32 Value, + IN UINT32 Flag + ) +{ + __outdword ((UINT16) Addr, Value); +} +VOID +StopHere ( + VOID + ) +{ + VOLATILE UINTN x = 1; + while (x); +} /*---------------------------------------------------------------------------------------*/ /**

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[commit] r6557 - trunk/src/vendorcode/amd/agesa
by repository service 07 May '11

07 May '11

Author: kerry Date: Sat May 7 10:33:14 2011 New Revision: 6557 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6557 Log: put the amdlib and agesa constant to .rodata segment. so amdlib.c would not complain "Do not use global variables in romstage" Signed-off-by: Kerry She <kerry.she(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/vendorcode/amd/agesa/Porting.h Modified: trunk/src/vendorcode/amd/agesa/Porting.h ============================================================================== --- trunk/src/vendorcode/amd/agesa/Porting.h Thu May 5 18:49:11 2011 (r6556) +++ trunk/src/vendorcode/amd/agesa/Porting.h Sat May 7 10:33:14 2011 (r6557) @@ -226,9 +226,7 @@ #define VOLATILE volatile #define TRUE 1 #define FALSE 0 - //#define CONST const - avoid const until the large job of making agesa use it consistently is complete -#undef CONST - #define CONST + #define CONST const #define ROMDATA #define CALLCONV #define _16BYTE_ALIGN __attribute__ ((aligned (16)))

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[PATCH 3/4] RS780 DDI Lanes configure support
by She, Kerry 06 May '11

06 May '11

Hello, RS780 DDI Lanes configure support Signed-off-by: Kerry She <Kerry.she(a)amd.com> Regards, Kerry She < kerry.she(a)amd.com> Tel: 86-10-6280-1415 Mobile: 86 - 152 1018 2083

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[PATCH 4/4] RS780 PCIE GEN2 Software Compliance support
by She, Kerry 06 May '11

06 May '11

Hello, RS780 PCIE GEN2 Software Compliance support Signed-off-by: Kerry She <Kerry.she(a)amd.com> Regards, Kerry She < kerry.she(a)amd.com> Tel: 86-10-6280-1415 Mobile: 86 - 152 1018 2083

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[Patch 2/4] compile sb800 code without agesav5
by She, Kerry 06 May '11

06 May '11

Hello, SB800 CIMX code can share the AGESA V5 lib code, some platform only use sb800 cimx code, not use AGESA v5 code, compile the sb800 cimx and AGESA v5 lib code. Signed-off-by: Kerry She <Kerry.she(a)amd.com> Regards, Kerry She < kerry.she(a)amd.com> Tel: 86-10-6280-1415 Mobile: 86 - 152 1018 2083

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[PATCH] AMD Persimmon: disable memory clear for boot time reduction
by Scott Duplichan 06 May '11

06 May '11

The attached patch (along with the 04/30/2011 Persimmon patch set) is needed to get the 640 ms coreboot+seabios+dos boot time. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: src/mainboard/amd/persimmon/BiosCallOuts.c =================================================================== --- src/mainboard/amd/persimmon/BiosCallOuts.c (revision 6556) +++ src/mainboard/amd/persimmon/BiosCallOuts.c (working copy) @@ -512,6 +512,9 @@ Data8 &= ~(UINT8)BIT6; Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); } + + // disable memory clear for boot time reduction + MemData->ParameterListPtr->EnableMemClr = FALSE; return Status; } /* Call the host environment interface to provide a user hook opportunity. */

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A patch to add VOID to empty parameter lists to get rid of some build warnings.
by Vibrans, Frank 05 May '11

05 May '11

Adds VOID to empty parameter lists to get rid of some build warnings. This change modifies a collection of files by adding the VOID parameter to empty parameter lists to cut down on the number of warnings produced when compiling the AMD Agesa code. This should cut down the number of warnings by about 1100 each for rom- and ramstage. Signed-off by Frank Vibrans <frank.vibrans(a)amd.com> -- This patch is compressed to retain line endings. My Windows environment has the tendency to change them.

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[commit] r6556 - in trunk/src/vendorcode/amd/agesa/Proc: CPU Common GNB/Nb/Family GNB/Nb/Family/0x14 Mem Mem/Main Mem/Tech
by repository service 05 May '11

05 May '11

Author: mjones Date: Thu May 5 18:49:11 2011 New Revision: 6556 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6556 Log: Adds VOID to empty parameter lists to get rid of some build warnings. This change modifies a collection of files by adding the VOID parameter to empty parameter lists to cut down on the number of warnings produced when compiling the AMD Agesa code. This should cut down the number of warnings by about 1100 each for rom- and ramstage. Signed-off-by: Frank Vibrans <frank.vibrans(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h trunk/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h trunk/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c trunk/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c trunk/src/vendorcode/amd/agesa/Proc/Mem/mm.h trunk/src/vendorcode/amd/agesa/Proc/Mem/mn.h trunk/src/vendorcode/amd/agesa/Proc/Mem/mt.h trunk/src/vendorcode/amd/agesa/Proc/Mem/mu.h Modified: trunk/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h ============================================================================== --- trunk/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h Thu May 5 18:45:36 2011 (r6555) +++ trunk/src/vendorcode/amd/agesa/Proc/CPU/cpuServices.h Thu May 5 18:49:11 2011 (r6556) @@ -151,14 +151,14 @@ * */ UINT32 -GetPlatformNumberOfSockets (); +GetPlatformNumberOfSockets (VOID); /** * Get the number of Modules to check presence in each Processor. * */ UINT32 -GetPlatformNumberOfModules (); +GetPlatformNumberOfModules (VOID); BOOLEAN IsProcessorPresent ( Modified: trunk/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c ============================================================================== --- trunk/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c Thu May 5 18:45:36 2011 (r6555) +++ trunk/src/vendorcode/amd/agesa/Proc/Common/CommonReturns.c Thu May 5 18:49:11 2011 (r6556) @@ -70,7 +70,7 @@ * @retval TRUE Default case, no special action */ BOOLEAN -CommonReturnTrue () +CommonReturnTrue (VOID) { return TRUE; } @@ -83,7 +83,7 @@ * @retval FALSE Default case, no special action */ BOOLEAN -CommonReturnFalse () +CommonReturnFalse (VOID) { return FALSE; } @@ -96,7 +96,7 @@ * @retval zero None, or only case zero. */ UINT8 -CommonReturnZero8 () +CommonReturnZero8 (VOID) { return 0; } @@ -109,7 +109,7 @@ * @retval zero None, or only case zero. */ UINT32 -CommonReturnZero32 () +CommonReturnZero32 (VOID) { return 0; } @@ -122,7 +122,7 @@ * @retval zero None, or only case zero. */ UINT64 -CommonReturnZero64 () +CommonReturnZero64 (VOID) { return 0; } @@ -134,7 +134,7 @@ * @retval NULL pointer to nothing */ VOID * -CommonReturnNULL () +CommonReturnNULL (VOID) { return NULL; } @@ -146,7 +146,7 @@ * @retval AGESA_SUCCESS Success. */ AGESA_STATUS -CommonReturnAgesaSuccess () +CommonReturnAgesaSuccess (VOID) { return AGESA_SUCCESS; } @@ -158,7 +158,7 @@ * */ VOID -CommonVoid () +CommonVoid (VOID) { } @@ -168,7 +168,7 @@ * */ VOID -CommonAssert () +CommonAssert (VOID) { ASSERT (FALSE); } Modified: trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c ============================================================================== --- trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c Thu May 5 18:45:36 2011 (r6555) +++ trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/0x14/F14NbServices.c Thu May 5 18:49:11 2011 (r6556) @@ -115,6 +115,7 @@ FUSE_TABLE* NbFmGetFuseTranslationTable ( + VOID ) { return &FuseTable; Modified: trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h ============================================================================== --- trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h Thu May 5 18:45:36 2011 (r6555) +++ trunk/src/vendorcode/amd/agesa/Proc/GNB/Nb/Family/NbFamilyServices.h Thu May 5 18:49:11 2011 (r6556) @@ -86,6 +86,7 @@ FUSE_TABLE* NbFmGetFuseTranslationTable ( + VOID ); VOID Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c ============================================================================== --- trunk/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c Thu May 5 18:45:36 2011 (r6555) +++ trunk/src/vendorcode/amd/agesa/Proc/Mem/Main/mdef.c Thu May 5 18:49:11 2011 (r6556) @@ -89,7 +89,7 @@ */ VOID -memDefRet () +memDefRet (VOID) { } @@ -100,7 +100,7 @@ * */ BOOLEAN -memDefTrue () +memDefTrue (VOID) { return TRUE; } @@ -112,7 +112,7 @@ * */ BOOLEAN -memDefFalse () +memDefFalse (VOID) { return FALSE; } @@ -137,7 +137,7 @@ * */ AGESA_STATUS -memDefRetSuccess () +memDefRetSuccess (VOID) { return AGESA_SUCCESS; } Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c ============================================================================== --- trunk/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c Thu May 5 18:45:36 2011 (r6555) +++ trunk/src/vendorcode/amd/agesa/Proc/Mem/Tech/mttdimbt.c Thu May 5 18:49:11 2011 (r6556) @@ -150,11 +150,11 @@ UINT8 STATIC -MemTMaxByteLanesByte (); +MemTMaxByteLanesByte (VOID); UINT8 STATIC -MemTDlyTableWidthByte (); +MemTDlyTableWidthByte (VOID); VOID STATIC @@ -689,7 +689,7 @@ UINT8 STATIC -MemTMaxByteLanesByte () +MemTMaxByteLanesByte (VOID) { return MAX_BYTELANES; } @@ -704,7 +704,7 @@ UINT8 STATIC -MemTDlyTableWidthByte () +MemTDlyTableWidthByte (VOID) { return MAX_DELAYS; } Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/mm.h ============================================================================== --- trunk/src/vendorcode/amd/agesa/Proc/Mem/mm.h Thu May 5 18:45:36 2011 (r6555) +++ trunk/src/vendorcode/amd/agesa/Proc/Mem/mm.h Thu May 5 18:49:11 2011 (r6556) @@ -984,10 +984,10 @@ ); VOID -MemRecDefRet (); +MemRecDefRet (VOID); BOOLEAN -MemRecDefTrue (); +MemRecDefTrue (VOID); VOID SetMemRecError ( @@ -996,7 +996,7 @@ ); AGESA_STATUS -memDefRetSuccess (); +memDefRetSuccess (VOID); #endif /* _MM_H_ */ Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/mn.h ============================================================================== --- trunk/src/vendorcode/amd/agesa/Proc/Mem/mn.h Thu May 5 18:45:36 2011 (r6555) +++ trunk/src/vendorcode/amd/agesa/Proc/Mem/mn.h Thu May 5 18:49:11 2011 (r6556) @@ -548,7 +548,7 @@ VOID (*Feature) (struct _MEM_NB_BLOCK *NBPtr); ///< Feature support. UINT8 (*GetSocketRelativeChannel) (struct _MEM_NB_BLOCK *NBPtr, UINT8 Dct, UINT8 Channel); ///< Get channel number relative to a socket. VOID (*SetDramOdtRec) (struct _MEM_NB_BLOCK *NBPtr, ODT_MODE OdtMode, UINT8 ChipSelect, UINT8 TargetCS); ///< Set Dram ODT. - UINT32 (*GetSysAddrRec) (); ///< Get system address for training. + UINT32 (*GetSysAddrRec) (VOID); ///< Get system address for training. VOID (*SwitchNodeRec) (struct _MEM_NB_BLOCK *NBPtr, UINT8 NodeID); ///< Switch to current node. VOID (*TechBlockSwitch) (struct _MEM_NB_BLOCK *NBPtr); ///< Selects appropriate Tech functions for the NB. VOID (*SetEccSymbolSize) (struct _MEM_NB_BLOCK *NBPtr); ///< Set Ecc Symbol Size. @@ -979,6 +979,7 @@ UINT32 MemRecNGetMCTSysAddrNb ( + VOID ); UINT32 Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/mt.h ============================================================================== --- trunk/src/vendorcode/amd/agesa/Proc/Mem/mt.h Thu May 5 18:45:36 2011 (r6555) +++ trunk/src/vendorcode/amd/agesa/Proc/Mem/mt.h Thu May 5 18:49:11 2011 (r6556) @@ -206,11 +206,11 @@ VOID (*SkipChipSelPass1) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above. VOID (*SkipChipSelPass2) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above. UINT16 (*CompareTestPatternFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< compare training pattern with filter. - UINT8 (*MaxByteLanes) (); ///< return maximum number of bytelanes. + UINT8 (*MaxByteLanes) (VOID); ///< return maximum number of bytelanes. VOID (*SetDQSDelayCSR) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 Dly); ///< Set CSR. VOID (*DQSWindowSave) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 DlyMin, UINT8 DlyMax); ///< programs the trained DQS delay for the specified byte lane and stores its DQS window for reference. BOOLEAN (*FindMaxDlyForMaxRdLat) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< Find maximum receiver enable delay value. - UINT8 (*DlyTableWidth) (); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes. + UINT8 (*DlyTableWidth) (VOID); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes. UINT16 (*Compare1ClPatternOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT8 Side, UINT8 Receiver, BOOLEAN Side1En); ///< Compare training pattern of 1 cache line. VOID (*LoadRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value. VOID (*SetRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value. Modified: trunk/src/vendorcode/amd/agesa/Proc/Mem/mu.h ============================================================================== --- trunk/src/vendorcode/amd/agesa/Proc/Mem/mu.h Thu May 5 18:45:36 2011 (r6555) +++ trunk/src/vendorcode/amd/agesa/Proc/Mem/mu.h Thu May 5 18:49:11 2011 (r6556) @@ -230,6 +230,7 @@ VOID MemUMFenceInstr ( + VOID ); #endif /* _MU_H_ */

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A patch to remove AMD Agesa requirement for standard include files
by Vibrans, Frank 05 May '11

05 May '11

Remove AMD Agesa requirement for standard include files This change modifies Makefile.inc to add the -nostdinc flag to the default CFLAGS value and removes the test for non-AMD Agesa builds. Other code is added to the gcc-intrin.h file in the Agesa Include folder to make the requirement for the standard includes obsolete from the Agesa perspective. Signed-off by Frank Vibrans <frank.vibrans(a)amd.com> -- This patch is compressed to retain Linux line endings.

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coreboot May 2011