Author: mjones
Date: Mon May 16 00:00:23 2011
New Revision: 6587
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6587
Log:
Declare RTC as not PIIX4 compatible to match AMD hardware.
Signed-off-by: Scott Duplichan <scott(a)notabs.org>
Acked-by: Marc Jones <marcj303(a)gmail.com>
Modified:
trunk/src/mainboard/amd/persimmon/dsdt.asl
Modified: trunk/src/mainboard/amd/persimmon/dsdt.asl
==============================================================================
--- trunk/src/mainboard/amd/persimmon/dsdt.asl Sun May 15 23:59:19 2011 (r6586)
+++ trunk/src/mainboard/amd/persimmon/dsdt.asl Mon May 16 00:00:23 2011 (r6587)
@@ -1379,7 +1379,7 @@
/* Real Time Clock Device */
Device(RTC0) {
- Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
+ Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
Name(_CRS, ResourceTemplate() {
IRQNoFlags(){8}
IO(Decode16,0x0070, 0x0070, 0, 2)
Author: mjones
Date: Sun May 15 23:51:31 2011
New Revision: 6583
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6583
Log:
Switch processor cores to pstate 0 early to reduce boot time.
Signed-off-by: Scott Duplichan <scott(a)notabs.org>
Acked-by: Marc Jones <marcj303(a)gmail.com>
Modified:
trunk/src/mainboard/amd/persimmon/romstage.c
Modified: trunk/src/mainboard/amd/persimmon/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:48:22 2011 (r6582)
+++ trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:51:31 2011 (r6583)
@@ -47,6 +47,9 @@
u32 val;
u8 reg8;
+ // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+ __writemsr (0xc0010062, 0);
+
// early enable of SPI 33 MHz fast mode read
if (boot_cpu())
{
Author: mjones
Date: Sun May 15 23:41:00 2011
New Revision: 6580
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6580
Log:
Program the I/O APIC ID.
Signed-off-by: Scott Duplichan <scott(a)notabs.org>
Acked-by: Marc Jones <marcj303(a)gmail.com>
Modified:
trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c
==============================================================================
--- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Sun May 15 23:38:08 2011 (r6579)
+++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Sun May 15 23:41:00 2011 (r6580)
@@ -352,6 +352,25 @@
break;
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
+ {
+ u8 byte;
+ u32 ioapic_base;
+
+ printk(BIOS_INFO, "sm_init().\n");
+ ioapic_base = 0xFEC00000;
+ clear_ioapic(ioapic_base);
+ /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
+ #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
+ /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
+ setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+ #elif (CONFIG_APIC_ID_OFFSET > 0)
+ /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
+ setup_ioapic(ioapic_base, 0);
+ #else
+ #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
+ #endif
+ }
+
break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */