coreboot May 2011

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BIOS Protection Guidelines from NIST
by Антон Кочков 17 May '11

17 May '11

April 2011: http://csrc.nist.gov/publications/nistpubs/800-147/NIST-SP800-147-April2011…

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Re: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
by Anders jenbo 17 May '11

17 May '11

Is there any benefit to actually disabling this stuff? Mvh Anders ----- Reply message ----- Fra: "Andrew" <nitr0(a)seti.kr.ua> Dato: man., maj 16, 2011 19:02 Emne: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options? Til: <coreboot(a)coreboot.org> 16.05.2011 19:31, Marc Jones пишет: > > 2. CMOS is not a good place for platform options either. It is good > for runtime options, but I don't think that there are many options for > users to change. What options users would change and how will they > change them? CMOS options could even go into the device tree. > IMHO device operation modes (for ex., AHCI/legacy IDE for SATA, LPT port modes, etc) should be in CMOS. Also switches for enabling/disabling devices (LPT, FDD, IDE/SATA, etc) should be in CMOS. -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

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[commit] r6585 - trunk/src/mainboard/amd/persimmon
by repository service 16 May '11

16 May '11

Author: mjones Date: Sun May 15 23:56:03 2011 New Revision: 6585 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6585 Log: Enable SPI cacheline prefetch early to reduce boot time. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/mainboard/amd/persimmon/romstage.c Modified: trunk/src/mainboard/amd/persimmon/romstage.c ============================================================================== --- trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:54:04 2011 (r6584) +++ trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:56:03 2011 (r6585) @@ -50,6 +50,21 @@ // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0); + if (boot_cpu()) + { + u8 reg8; + // SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register + outb(0x24, 0xCD6); + reg8 = inb(0xCD7); + reg8 |= 1; + reg8 &= ~(1 << 1); + outb(reg8, 0xCD7); + + // program SB800 MiscCntrl + *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ + *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ + } + // early enable of PrefetchEnSPIFromHost if (boot_cpu()) { @@ -78,17 +93,6 @@ f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } - //reg8 = pmio_read(0x24); - outb(0x24, 0xCD6); - reg8 = inb(0xCD7); - reg8 |= 1; - reg8 &= ~(1 << 1); - //pmio_write(0x24, reg8); - outb(0x24, 0xCD6); - outb(reg8, 0xCD7); - - *(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */ /* Halt if there was a built in self test failure */ post_code(0x34);

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[commit] r6592 - in trunk/src: mainboard/amd/persimmon southbridge/amd/cimx_wrapper/sb800
by repository service 16 May '11

16 May '11

Author: mjones Date: Mon May 16 00:07:56 2011 New Revision: 6592 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6592 Log: Update gpp port configuration. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/mainboard/amd/persimmon/devicetree.cb trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Modified: trunk/src/mainboard/amd/persimmon/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/persimmon/devicetree.cb Mon May 16 00:06:09 2011 (r6591) +++ trunk/src/mainboard/amd/persimmon/devicetree.cb Mon May 16 00:07:56 2011 (r6592) @@ -81,13 +81,13 @@ end end # f81865f end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - register "gpp_configuration" = "4" #1:1:1:1 + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE end #southbridge/amd/cimx_wrapper/sb800 # end # device pci 18.0 Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c Mon May 16 00:06:09 2011 (r6591) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.c Mon May 16 00:07:56 2011 (r6592) @@ -99,10 +99,6 @@ sb_config->GppFunctionEnable = GPP_CONTROLLER; sb_config->GppLinkConfig = GPP_CFGMODE; //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE; - sb_config->PORTCONFIG[0].PortCfg.PortPresent = ENABLED; - sb_config->PORTCONFIG[1].PortCfg.PortPresent = ENABLED; - sb_config->PORTCONFIG[2].PortCfg.PortPresent = ENABLED; - sb_config->PORTCONFIG[3].PortCfg.PortPresent = ENABLED; sb_config->GppUnhidePorts = TRUE; //visable always, even port empty //sb_config->NbSbGen2 = TRUE; //sb_config->GppGen2 = TRUE; Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Mon May 16 00:06:09 2011 (r6591) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Mon May 16 00:07:56 2011 (r6592) @@ -315,7 +315,6 @@ */ static void sb800_enable(device_t dev) { - u8 gpp_port = 0; struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip = (struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info); @@ -414,15 +413,16 @@ break; case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ + sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled; + return; case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */ + sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled; + return; case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */ + sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled; + return; case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */ - gpp_port = (dev->path.pci.devfn) & 0x03; - if (dev->enabled) { - sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED; - } else { - sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED; - } + sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled; /* * GPP_CFGMODE_X4000: PortA Lanes[3:0]

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Re: [coreboot] Kconfig vs. devicetree vs. CMOS policy for options?
by Anders jenbo 16 May '11

16 May '11

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Ok, let's move on. What shold we do to CBFS?
by Hamo 16 May '11

16 May '11

Dear lists, I have got the idea on how to deal with xcompile script for ARM. Now, let's move on to CBFS. It is one of the most difficult part since CBFS is almost hard-coded to X86 architecture. On ARM, we need CBFS like this: /---------------\ <-- Start of ROM | /-----------\ | | | Reset | | <- 0x0 | |-----------| | | |IVs | | | |-----------| | | |Boot | | | |Block | | | \-----------/ | | | | /-----------\ | --| | | Header| | | | |-----------| | | | | Name | | | | |-----------| | |-- Component | |Data | | | | |.. | | | | \-----------/ | --| | | | ... | | /-----------\ | --| | | Header| | | | |-----------| | | | | Name | | | | |-----------| | |-- Component | |Data | | | | |.. | | | | \-----------/ | --| \---------------/ Where should we put the CBFS master header and the pointer to it? I have no idea of how to implement it and not break it on X86 architecture. Any comment or suggestion is very welcome.

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Win7 on Intel Eagle Heights
by Thomas JOURDAN 16 May '11

16 May '11

Hi guys I'm trying to get Windows 7 booting on my Intel Eagle Heights evaluation board. I tried to follow all the ACPI tips to get Window$ to boot but I can't figure out the bug I'm facing. I'm using a checked build version of Win 7 64-bits. When I start the installer, the first text screen is ok (windows is copying files...) then it switches to graphics mode (green progress bar with logo). Less than a second after switching from text to graphics mode : BSOD. With windbg I tried to dump as much as possible and the analyser tell me a write operation occured at an invalid address. According to the stack frame, the error occured in PowerPolicyProcessEvent when the kernel starts all devices (enter D0 state). Does the device states only applies to PCI devices, or all devices ? How can I know which device causes this problem ? I can't even figure out if it's an ACPI related problem, or something wrong in a device initialization function. Regards, Thomas

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[commit] r6599 - trunk
by repository service 16 May '11

16 May '11

Author: oxygene Date: Mon May 16 17:32:28 2011 New Revision: 6599 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6599 Log: Move crossgcc rules to coreboot specific Makefile Toplevel Makefile should (as far as possible) be coreboot-agnostic, we have Makefile.inc for that. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/Makefile trunk/Makefile.inc Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Mon May 16 03:35:03 2011 (r6598) +++ trunk/Makefile Mon May 16 17:32:28 2011 (r6599) @@ -242,12 +242,6 @@ cscope: cscope -bR -crossgcc: clean-for-update - $(MAKE) -C util/crossgcc build - -crossgcc-clean: clean-for-update - $(MAKE) -C util/crossgcc clean - doxy: doxygen doxygen: $(DOXYGEN) documentation/Doxyfile.coreboot Modified: trunk/Makefile.inc ============================================================================== --- trunk/Makefile.inc Mon May 16 03:35:03 2011 (r6598) +++ trunk/Makefile.inc Mon May 16 17:32:28 2011 (r6599) @@ -230,3 +230,10 @@ done; \ test $$FAILED -eq 0 || { echo "ERROR: $$FAILED test(s) failed." && exit 1; }; \ rm -f $$LINTLOG + +crossgcc: clean-for-update + $(MAKE) -C util/crossgcc build + +crossgcc-clean: clean-for-update + $(MAKE) -C util/crossgcc clean +

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[commit] r6582 - trunk/src/mainboard/amd/persimmon
by repository service 16 May '11

16 May '11

Author: mjones Date: Sun May 15 23:48:22 2011 New Revision: 6582 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6582 Log: Enable 33 MHz fast mode SPI read early to reduce boot time. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/mainboard/amd/persimmon/romstage.c Modified: trunk/src/mainboard/amd/persimmon/romstage.c ============================================================================== --- trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:45:46 2011 (r6581) +++ trunk/src/mainboard/amd/persimmon/romstage.c Sun May 15 23:48:22 2011 (r6582) @@ -47,6 +47,19 @@ u32 val; u8 reg8; + // early enable of SPI 33 MHz fast mode read + if (boot_cpu()) + { + volatile u32 *spiBase = (void *) 0xa0000000; + u32 save; + __outdword (0xcf8, 0x8000a3a0); + save = __indword (0xcfc); + __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base + spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14); + spiBase [0] |= 1 << 18; // fast read enable + __outdword (0xcfc, save); // clear temp base + } + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init();

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Issue #16: I2C driver and mainboard Config.lb
by Vikram Narayanan 16 May '11

16 May '11

Hi, Can any one share the latest info on this ticket? While discussing this with Stefan Reinauer, he shared me some info on this. I am also adding this here. >From Ollie Lho: >There are a lot of mainboards using driver/generic/generic as the i2c driver of their HW monitor. They should be changed to driver/i2c/*. Stefan Reinauer: And it seems drivers/generic/generic does not exist anymore or potentially never existed. >Rename driver/i2c/i2cmux to driver/i2c/pca9556 Stefan Reinauer: I think the problem was that i2cmux was not a generic i2cmux driver but instead a driver for the pca9556 but i am not sure anymore. it would take someone to look into that. - Thanks, Vikram

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coreboot May 2011