coreboot May 2011

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Trac reminder: list of new ticket(s)
by coreboot tracker 16 May '11

16 May '11

1 0

AMD Persimmon update
by Scott Duplichan 16 May '11

16 May '11

The attached changes for the AMD Persimmon board improve OS support and reduce boot time. DOS boot from SSD drive is 640 ms. Windows 7, Windows XP, and linux can install from DVD and boot from hard disk. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Thanks, Scott

2 3

[commit] r6591 - trunk/src/mainboard/amd/persimmon
by repository service 16 May '11

16 May '11

Author: mjones Date: Mon May 16 00:06:09 2011 New Revision: 6591 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6591 Log: Enable rom cache early to reduce boot time. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/mainboard/amd/persimmon/agesawrapper.c trunk/src/mainboard/amd/persimmon/romstage.c Modified: trunk/src/mainboard/amd/persimmon/agesawrapper.c ============================================================================== --- trunk/src/mainboard/amd/persimmon/agesawrapper.c Mon May 16 00:05:00 2011 (r6590) +++ trunk/src/mainboard/amd/persimmon/agesawrapper.c Mon May 16 00:06:09 2011 (r6591) @@ -157,13 +157,6 @@ PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - Status = AGESA_SUCCESS; return (UINT32)Status; } Modified: trunk/src/mainboard/amd/persimmon/romstage.c ============================================================================== --- trunk/src/mainboard/amd/persimmon/romstage.c Mon May 16 00:05:00 2011 (r6590) +++ trunk/src/mainboard/amd/persimmon/romstage.c Mon May 16 00:06:09 2011 (r6591) @@ -47,6 +47,11 @@ u32 val; u8 reg8; + // all cores: allow caching of flash chip code and data + // (there are no cache-as-ram reliability concerns with family 14h) + __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); + __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0);

4 3

[patch] crossgcc make target
by Cristi Magherusan 16 May '11

16 May '11

Please see the patch below. Signed-off-by: Cristian Magherusan-Stanciu <cristi.magherusan(a)gmail.com> diff --git a/Makefile b/Makefile index ac7115d..69e32a4 100644 --- a/Makefile +++ b/Makefile @@ -242,6 +242,12 @@ $(shell mkdir -p $(obj) $(objutil)/kconfig/lxdialog $(additional-dirs) $(alldirs cscope: cscope -bR +crossgcc: clean-for-update + $(MAKE) -C util/crossgcc build + +crossgcc-clean: clean-for-update + $(MAKE) -C util/crossgcc clean + doxy: doxygen doxygen: $(DOXYGEN) documentation/Doxyfile.coreboot diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile new file mode 100644 index 0000000..ea19e6f --- /dev/null +++ b/util/crossgcc/Makefile @@ -0,0 +1,12 @@ +all: build + +build: + ./buildgcc + +clean: + rm -rf xgcc + +distclean: clean + rm -rf tarballs/* + +.PHONY: all clean distclean build

2 1

[commit] r6598 - in trunk: . util/crossgcc
by repository service 16 May '11

16 May '11

Author: stuge Date: Mon May 16 03:35:03 2011 New Revision: 6598 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6598 Log: Add crossgcc target to automatically build reference toolchain This means that a simple: $ make crossgcc creates the reference toolchain in the correct directory. Thanks to the dependency on the clean-for-update target, an existing .xcompile along with any compiled objects in build/ will be cleaned out, so the next build will automatically use the newly created reference toolchain. Signed-off-by: Cristian Magherusan-Stanciu <cristi.magherusan(a)gmail.com> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/util/crossgcc/Makefile Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Mon May 16 02:05:50 2011 (r6597) +++ trunk/Makefile Mon May 16 03:35:03 2011 (r6598) @@ -242,6 +242,12 @@ cscope: cscope -bR +crossgcc: clean-for-update + $(MAKE) -C util/crossgcc build + +crossgcc-clean: clean-for-update + $(MAKE) -C util/crossgcc clean + doxy: doxygen doxygen: $(DOXYGEN) documentation/Doxyfile.coreboot Added: trunk/util/crossgcc/Makefile ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/util/crossgcc/Makefile Mon May 16 03:35:03 2011 (r6598) @@ -0,0 +1,9 @@ +all: build + +build: + ./buildgcc + +clean: + rm -rf xgcc + +.PHONY: all build clean

1 0

[commit] r6597 - trunk/src/southbridge/amd/cimx_wrapper/sb800
by repository service 16 May '11

16 May '11

Author: stuge Date: Mon May 16 02:05:50 2011 New Revision: 6597 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6597 Log: cimx_wrapper/sb800: Fix indent in late.c:sb800_enable() Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Mon May 16 01:13:54 2011 (r6596) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Mon May 16 02:05:50 2011 (r6597) @@ -413,16 +413,16 @@ break; case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ - sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled; - return; + sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled; + return; case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */ - sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled; - return; + sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled; + return; case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */ - sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled; - return; + sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled; + return; case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */ - sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled; + sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled; /* * GPP_CFGMODE_X4000: PortA Lanes[3:0]

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[commit] r6578 - in trunk/src: mainboard/amd/persimmon northbridge/amd/agesa_wrapper/family14 vendorcode/amd/cimx/sb800
by repository service 15 May '11

15 May '11

Author: mjones Date: Sun May 15 23:26:04 2011 New Revision: 6578 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6578 Log: Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/mainboard/amd/persimmon/dsdt.asl trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig trunk/src/vendorcode/amd/cimx/sb800/OEM.h Modified: trunk/src/mainboard/amd/persimmon/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/persimmon/dsdt.asl Sun May 15 23:19:54 2011 (r6577) +++ trunk/src/mainboard/amd/persimmon/dsdt.asl Sun May 15 23:26:04 2011 (r6578) @@ -36,7 +36,7 @@ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(PCBA, 0xF8000000) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Modified: trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig ============================================================================== --- trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig Sun May 15 23:19:54 2011 (r6577) +++ trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig Sun May 15 23:26:04 2011 (r6578) @@ -41,12 +41,12 @@ config MMCONF_BASE_ADDRESS hex - default 0xe0000000 + default 0xf8000000 depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14 config MMCONF_BUS_NUMBER int - default 256 + default 16 depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14 config DIMM_DDR3 Modified: trunk/src/vendorcode/amd/cimx/sb800/OEM.h ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/OEM.h Sun May 15 23:19:54 2011 (r6577) +++ trunk/src/vendorcode/amd/cimx/sb800/OEM.h Sun May 15 23:26:04 2011 (r6578) @@ -48,7 +48,7 @@ #ifdef MOVE_PCIEBAR_TO_F0000000 #define PCIEX_BASE_ADDRESS 0xF7000000 #else - #define PCIEX_BASE_ADDRESS 0xE0000000 + #define PCIEX_BASE_ADDRESS 0xF8000000 #endif /**

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[commit] r6596 - in trunk/src: mainboard/amd/persimmon vendorcode/amd/cimx/sb800
by repository service 15 May '11

15 May '11

Author: mjones Date: Mon May 16 01:13:54 2011 New Revision: 6596 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6596 Log: Remove multiple mmconf settings and just use kconfig setting. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/mainboard/amd/persimmon/dsdt.asl trunk/src/vendorcode/amd/cimx/sb800/OEM.h Modified: trunk/src/mainboard/amd/persimmon/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/persimmon/dsdt.asl Mon May 16 00:40:40 2011 (r6595) +++ trunk/src/mainboard/amd/persimmon/dsdt.asl Mon May 16 01:13:54 2011 (r6596) @@ -36,7 +36,7 @@ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ - Name(PCBA, 0xF8000000) /* Base address of PCIe config space */ + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Modified: trunk/src/vendorcode/amd/cimx/sb800/OEM.h ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/OEM.h Mon May 16 00:40:40 2011 (r6595) +++ trunk/src/vendorcode/amd/cimx/sb800/OEM.h Mon May 16 01:13:54 2011 (r6596) @@ -48,7 +48,7 @@ #ifdef MOVE_PCIEBAR_TO_F0000000 #define PCIEX_BASE_ADDRESS 0xF7000000 #else - #define PCIEX_BASE_ADDRESS 0xF8000000 + #define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #endif /**

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[commit] r6590 - trunk/src/mainboard/amd/persimmon
by repository service 15 May '11

15 May '11

Author: mjones Date: Mon May 16 00:05:00 2011 New Revision: 6590 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6590 Log: Fix memory allocation problem in amdInitLate. Disabled until further debug. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/mainboard/amd/persimmon/agesawrapper.c Modified: trunk/src/mainboard/amd/persimmon/agesawrapper.c ============================================================================== --- trunk/src/mainboard/amd/persimmon/agesawrapper.c Mon May 16 00:03:45 2011 (r6589) +++ trunk/src/mainboard/amd/persimmon/agesawrapper.c Mon May 16 00:05:00 2011 (r6590) @@ -444,33 +444,32 @@ ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AMD_INTERFACE_PARAMS AmdParamStruct = {0}; + AMD_LATE_PARAMS *AmdLateParams; - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; + return 0; // this causes bad ACPI SSDT, need to debug - Status = AmdInitLate (&AmdLateParams); + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdCreateStruct (&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + Status = AmdInitLate (AmdLateParams); if (Status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); ASSERT(Status == AGESA_SUCCESS); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - AcpiAlib = AmdLateParams.AcpiAlib; + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AmdReleaseStruct (&AmdParamStruct); return (UINT32)Status; }

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[commit] r6589 - trunk/src/mainboard/amd/persimmon
by repository service 15 May '11

15 May '11

Author: mjones Date: Mon May 16 00:03:45 2011 New Revision: 6589 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6589 Log: Remove some non-essential agesa options to reduce boot time. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/mainboard/amd/persimmon/buildOpts.c Modified: trunk/src/mainboard/amd/persimmon/buildOpts.c ============================================================================== --- trunk/src/mainboard/amd/persimmon/buildOpts.c Mon May 16 00:02:27 2011 (r6588) +++ trunk/src/mainboard/amd/persimmon/buildOpts.c Mon May 16 00:03:45 2011 (r6589) @@ -80,16 +80,16 @@ #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE #define BLDOPT_REMOVE_ECC_SUPPORT FALSE //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE #define BLDOPT_REMOVE_DQS_TRAINING FALSE -//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE #define BLDOPT_REMOVE_ACPI_PSTATES FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE @@ -97,17 +97,17 @@ #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -//#define BLDOPT_REMOVE_SRAT TRUE -//#define BLDOPT_REMOVE_SLIT TRUE -//#define BLDOPT_REMOVE_WHEA TRUE -//#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_HT_ASSIST TRUE -//#define BLDOPT_REMOVE_ATM_MODE TRUE +#define BLDOPT_REMOVE_SRAT TRUE +#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE //#define BLDOPT_REMOVE_C6_STATE TRUE -//#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE /* @@ -123,7 +123,7 @@ #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE /* * Agesa configuration values selection.

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coreboot May 2011