coreboot April 2010

coreboot@coreboot.org

64 participants
402 discussions

build service results for r5512
by coreboot information 30 Apr '10

30 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5512 to the coreboot repository. This caused the following changes: Change Log: Get rid of a few more warnings. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of intel:mtarvon has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5512&device=mtarvon&vendor… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5512 - in trunk/src: mainboard/arima/hdama mainboard/pcengines/alix1c northbridge/amd/amdfam10 northbridge/amd/amdk8 northbridge/amd/amdmct/mct northbridge/intel/i3100 northbridge/via/vx8...
by repository service 30 Apr '10

30 Apr '10

Author: myles Date: Fri Apr 30 19:11:03 2010 New Revision: 5512 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5512 Log: Get rid of a few more warnings. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/northbridge/amd/amdfam10/Makefile.inc trunk/src/northbridge/amd/amdfam10/debug.c trunk/src/northbridge/amd/amdfam10/get_pci1234.c trunk/src/northbridge/amd/amdfam10/northbridge.h trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/northbridge/amd/amdmct/mct/mct_d.c trunk/src/northbridge/intel/i3100/raminit.c trunk/src/northbridge/via/vx800/vga.c trunk/src/southbridge/intel/esb6300/esb6300_smbus.h trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/mainboard/arima/hdama/romstage.c Fri Apr 30 19:11:03 2010 (r5512) @@ -1,10 +1,10 @@ #include <stdint.h> +#include <string.h> #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> -#include <stdlib.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Fri Apr 30 19:11:03 2010 (r5512) @@ -36,7 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) /* The ALIX1.C has no SMBus; the setup is hard-wired. */ -void cs5536_enable_smbus(void) +static void cs5536_enable_smbus(void) { } Modified: trunk/src/northbridge/amd/amdfam10/Makefile.inc ============================================================================== --- trunk/src/northbridge/amd/amdfam10/Makefile.inc Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdfam10/Makefile.inc Fri Apr 30 19:11:03 2010 (r5512) @@ -10,4 +10,3 @@ obj-$(CONFIG_GENERATE_ACPI_TABLES) += sspr5.o obj-y += get_pci1234.o - Modified: trunk/src/northbridge/amd/amdfam10/debug.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/debug.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdfam10/debug.c Fri Apr 30 19:11:03 2010 (r5512) @@ -26,7 +26,7 @@ static inline void print_debug_addr(const char *str, void *val) { -#if CACHE_AS_RAM_ADDRESS_DEBUG == 1 +#if defined(CACHE_AS_RAM_ADDRESS_DEBUG) && CACHE_AS_RAM_ADDRESS_DEBUG == 1 printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); #endif } Modified: trunk/src/northbridge/amd/amdfam10/get_pci1234.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/get_pci1234.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdfam10/get_pci1234.c Fri Apr 30 19:11:03 2010 (r5512) @@ -55,6 +55,7 @@ * */ +#include "northbridge.h" void get_pci1234(void) { Modified: trunk/src/northbridge/amd/amdfam10/northbridge.h ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.h Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdfam10/northbridge.h Fri Apr 30 19:11:03 2010 (r5512) @@ -21,5 +21,6 @@ #define NORTHBRIDGE_AMD_AMDFAM10_H u32 amdfam10_scan_root_bus(device_t root, u32 max); +void get_pci1234(void); #endif /* NORTHBRIDGE_AMD_AMDFAM10_H */ Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Fri Apr 30 19:11:03 2010 (r5512) @@ -2511,9 +2511,8 @@ unsigned SlowAccessMode = 0; #endif - long dimm_mask = meminfo->dimm_mask & 0x0f; - #if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */ + long dimm_mask = meminfo->dimm_mask & 0x0f; /* for REG DIMM */ dword = 0x00111222; dwordx = 0x002f0000; @@ -2578,6 +2577,7 @@ #endif #if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ + long dimm_mask = meminfo->dimm_mask & 0x0f; /* for UNBUF DIMM */ dword = 0x00111222; dwordx = 0x002f2f00; Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Fri Apr 30 19:11:03 2010 (r5512) @@ -528,7 +528,7 @@ unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128; #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 - unsigned cpu_f0_f1; + unsigned cpu_f0_f1 = 0; #endif if(Pass == DQS_FIRST_PASS) { Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c Fri Apr 30 19:11:03 2010 (r5512) @@ -42,8 +42,6 @@ struct DCTStatStruc *pDCTstatA); static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); -static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, @@ -478,6 +476,8 @@ #ifdef UNUSED_CODE static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA); +static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { /* Clear MC4_STS for all Nodes in the system. This is required in some Modified: trunk/src/northbridge/intel/i3100/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i3100/raminit.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/intel/i3100/raminit.c Fri Apr 30 19:11:03 2010 (r5512) @@ -944,7 +944,7 @@ u32 drc; u32 data32; u32 mode_reg; - u32 *iptr; + u32 const *iptr; u16 data16; static const struct { u32 clkgr[4]; Modified: trunk/src/northbridge/via/vx800/vga.c ============================================================================== --- trunk/src/northbridge/via/vx800/vga.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/northbridge/via/vx800/vga.c Fri Apr 30 19:11:03 2010 (r5512) @@ -126,6 +126,7 @@ return res; } +#ifdef UNUSED_CODE void write_protect_vgabios(void) { device_t dev; @@ -141,6 +142,7 @@ //if(dev) // pci_write_config8(dev, 0x61, 0xff); */ } +#endif extern u8 acpi_sleep_type; static void vga_init(device_t dev) Modified: trunk/src/southbridge/intel/esb6300/esb6300_smbus.h ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_smbus.h Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/southbridge/intel/esb6300/esb6300_smbus.h Fri Apr 30 19:11:03 2010 (r5512) @@ -14,6 +14,8 @@ #define SMBUS_TIMEOUT (100*1000*10) +#include <delay.h> + static int smbus_wait_until_ready(unsigned smbus_io_base) { unsigned loops = SMBUS_TIMEOUT; Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Tue Apr 27 17:00:18 2010 (r5511) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Fri Apr 30 19:11:03 2010 (r5512) @@ -19,9 +19,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val); #ifdef UNUSED_CODE +int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val); + static int set_ht_link_mcp55(uint8_t ht_c_num) { unsigned vendorid = 0x10de;

1 0

suport for AMD 770 (RX781) ? SATA III ?
by Xavi Drudis Ferran 30 Apr '10

30 Apr '10

Hello. I know I said I'd pick one of the GSoC motherboards, but after that coreboot got DDR3 support, and since I want to have a computer for a long time, and it may help compiling quicker, and so... I'd like to go for AM3 for the DDR3 support (I'm thinking Phenom II X4 910e or 905e) . I've seen this motherboard but I'm not sure the chipset is supported in coreboot. M4A77TD PRO/U3S6 http://www.asus.com/product.aspx?P_ID=bjOkrdsFHkTzz4Q6 (it has a serial port and, from the picture, socketed BIOS ROM) It lists AMD 770/SB710 I think AMD 770 is an alias for RX781, and I think this is an RS780 without IGP . Is it included in the RS780 support contributed by AMD ? It's not listed in http://www.coreboot.org/Supported_Chipsets_and_Devices Maybe because it's not yet tested ? I imagine it is implemented (maybe not tested on bare metal) because I saw this message: Vadim Girlin , on Fri Apr 9 07:12:05 CEST 2010, wrote: > I'm going to try coreboot on Gigabyte GA-MA770-UD3. > It's AMD 770 (RX780 / SB700). > > I've prepared the image for it based on code for mahogany fam10 with > some modifications. > > I've tried it with simnow using the configuration close to mine as much > as possible - it even boots with my native BIOS. And it boots with > coreboot image. But I'd like confirmation of the status before buying the board just in case I'm doing something really silly. Another question is about the U3S6 sold with this card. It's a PCIe 2.0 (x1 ?) card with 2 USB3 ports and 2 SATA III (6Gb ) ports. I think it has a Marvell 88SE9123 SATA III controller. I don't find it in the supported chipset list. Yet it appears to have some linux driver (I still haven't foudn if there is some blob issue, Mavell calls it "open source linux driver"). Does it mean coreboot (payloads?) can't boot an OS from a disk connected to it,so I should have a disk connected to the 3Gb SATA in the motherboard ? I can buy the same card without the SATA III (6Gb) add on card, and I could at any time buy another add on card, so I'll probably do that if I can't use SATA III with coreboot anyway. I'll buy two 4Gb 1333MHz DDR3 SODIMMs if I can find them, and leave two more sockets for the future ,and a second hand Nvidia PCIe x16 fanless card for graphics. Sorry not to be able to send the required information since I still don't have these components and can't run diagnostics tools. I'm just asking if at first sight there's somethign weird with this. Thank you. I copy the specifications page from the motherboard vendor, since the link seems not to lead to it directly. Specifications CPU AMD Socket AM3 ;PhenomII /AthlonII /Sempron 100 Series Processors AMD 140W CPU Support AMD Cool 'n' Quiet 2.0 Technology (by CPU type) Support 45nm CPU *Refer to www.asus.com for the AMD CPU support list Chipset AMD 770/SB710 System Bus Up to 5200 MT/s HyperTransport 3.0 interface Memory 4 x DIMM, Max. 16 GB, DDR3 1800(O.C.)/1600(O.C.)/1333/1066 ECC,Non-ECC,Un-buffered Memory Dual Channel memory architecture *AMD AM3 100 and 200 series CPU support up to DDR3 1066MHz **Due to OS limitation, when installing total memory of 4GB capacity or more, Windows® 32-bit operation system may only recognize less than 3GB. Install a 64-bit WindowsWindows® OS when you want to install 4GB or more memory on the motherboard. ***Refer to www.asus.com or user manual for Memory QVL (Qualify Vendor List) Expansion Slots 2 x PCIe 2.0 x16 (*blue@ x16 mode, black@ x4 mode) 1 x PCIe x1 3 x PCI Storage SB710 Chipset 1 xUltraDMA 133/100 5 x Serial ATA 3Gb/s Support RAID 0,1,10 1 x eSATA 3Gb/s ports U3S6 card: - 2 x SATA 6Gb/s ports LAN Realtek 8112L PCIe Gb LAN Audio VT1708S High Definition Audio 8-Channel CODEC - Supports Jack-detect and Multistreaming teconologies, and Front Panel Jack-Retasking - Optical S/PDIF Out ports at back I/O USB 2 x USB 3.0 ports at U3S6 card 12 USB2.0/1.1 ports (6 ports at mid-board, 6 ports at back panel) ASUS Unique Features ASUS EPU-4 Engine ASUS Express Gate ASUS Turbo Key ASUS Q-Fan ASUS CrashFree BIOS 3 ASUS EZ Flash 2 ASUS MyLogo 2 ASUS AI NET 2 Overclocking Features Intelligent overclocking tools - Turbo Key SFS (Stepless Frequency Selection) - FSB tuning from 200MHz up to 550MHz at 1MHz increment - PCI Express frequency tuning from 100MHz up to 150MHz at 1MHz increment Overclocking Protection - ASUS C.P.R.(CPU Parameter Recall) Special Features True SATA 6Gb/s & USB 3.0 support 100% All High-quality Conductive Polymer Capacitors Back Panel I/O Ports 1 x PS/2 Keyboard/Mouse Combo port 1 x Parallel port 1 x S/PDIF Out (Optical) 1 x LAN(RJ45) port 1 x COM port 8 -Channel Audio I/O 2 x USB 3.0 ports(@ U3S6 card ) / 6 x USB 2.0ports 1 x ESATA 3Gb/s Internal I/O Connectors 3 x USB connectors supports additional 6 USB 2.0 ports 1 x IDE connector 1 x CPU / 1 x Power / 1 x Chassis Fan connectors 1 x S/PDIF Out connector 1 x System Panel connector 1 x CD audio-in connector 1 x High Definition Front panel audio connector 1 x 24-pin EATX power connector 1 x 4-pin ATX 12V Power connector 2 x SATA 6Gb/s connectors (@ U3S6 card) 5 x SATA 3Gb/s connectors BIOS 8 Mb Flash ROM AMI BIOS, PnP, DMI v2.0, WfM2.0, ACPI v2.0a, SMBIOS 2.5 Accessories 1 x I/O Shield 1 x UltraDMA 133/100/66 cable 2 x SATA 3Gb/s cables 2 x SATA 6Gb/s cables 1 x U3S6 card 1 x User's manual & Support DVD for U3S6 1 x User's manual & Support DVD for M4A77TD PRO Support Disc Drivers ASUS PC Probe II Express Gate Anti-virus software (OEM version) ASUS Update Form Factor ATX Form Factor 12 inch x 8.8 inch ( 30.5 cm x 22.4 cm ) AMD Socket AM3 ; Phenom II/Athlon II/Sempron 100 Series Processors This motherboard supports AMD® Socket AM3 multi-core processors with unique L3 cache and delivers better overclocking capabilities with less power consumption. It features dual-channel DDR3 1333 memory support and accelerates data transfer rate up to 5200MT/s via HyperTransport 3.0 based system bus. This motherboard also supports AMD® CPUs in the new 45nm manufacturing process. AMD 770 chipset AMD 770 Chipset is designed to support up to 5200MT/s HyperTransport 3.0 (HT 3.0) interface speed and PCI Express 2.0 x16 graphics. It is optimized with AMD®s latest AM3 and multi-core CPUs to provide excellent system performance and overclocking capabilities. ASUS EPU The ASUS EPU (Energy Processing Unit) provides total system power management by detecting current PC loadings and intelligently moderating power in real-time. It automatically provides the most appropriate power usage to save power and money! HyperTransport 3.0 Suport Provides 2.6 times more bandwidth than HT1.0 that radically improves system efficiency for a smoother, faster computing environment Dual-Channel DDR3 1800(O.C.) This motherboard supports DDR3 1800(O.C.) that provides faster data transfer rate and more bandwith to increase memory computing efficiency, enhancing system performance in 3D graphics and other memory demanding applications. PCIe 2.0 support This motherboard supports the latest PCIe 2.0 devices for double speed and bandwidth which enhances system performance. True USB 3.0 Support Unique PCIe x4 Bridge Chip for Ultra Performance Experience ultra-fast data transfers at 4.8Gbps with USB 3.0--the latest connectivity standard. Built to connect easily with next-generation components and peripherals, USB 3.0 transfers data 10X faster and is also backward compatible with USB 2.0 components. True SATA 6Gb/s Support Unique PCIe x4 Bridge Chip for Ultra PerformanceSupporting next-generation Serial ATA (SATA) storage interface, this motherboard delivers up to 6.0Gbps data transfer rates. Additionally, get enhanced scalability, faster data retrieval, double the bandwidth of current bus systems. ATI CrossFireX Technology ATI´s CrossFireX boosts image quality along with rendering speed, eliminating the need to scale down screen resolution to get high quality images. CrossFireX allows higher anti-aliasing, anisotropic filtering, shading, and texture settings. Adjust your display configurations, experiment with the advanced 3D settings, and check the effects with a real-time 3D-rendered previews within ATI Catalyst Control Center. 8+1 Phase Power Design To fully unleash the AM3 CPU´s potential, the ASUS M4 Series motherboards have adopted a brand new 8-phase VRM power design. It delivers high power efficiency and supreme overclocking ability. Furthermore, high quality power components can effectively lower system temperature to ensure longer component lifespan. This series also features an extra 1 phase power dedicated to integrated memory/HT controller. SATA on the Go The motherboard supports hard drives based on the Serial ATA (SATA) 3Gb/s storage specification, delivering enhanced scalability and doubling the bus bandwidth for high-speed data retrieval and saves. The external SATA port located at the back I/O provides smart setup and hot-plug functions. Easily backup photos, videos and other entertainment contents on external devices. Turbo Key ASUS Turbo Key allows the user to turn the PC power button into an overclocking button. After the easy setup, Turbo Key can boost performances without interrupting ongoing work or games - with just one touch!! High Definition Audio Enjoy high-end sound system on your PC! The onboard 8-channel HD audio (High Definition Audio, previously codenamed Azalia) CODEC enables high-quality 192KHz/24-bit audio output, jack-sensing feature, retasking functions and multi-streaming technology that simultaneously sends different audio streams to different destinations. You can now talk to your partners on the headphone while playing a multi-channel network games. All of these are done on one computer. Gigabit Lan This capability ensures rapid transfer of data from WAN to LAN without any added arbitration or latency. ASUS Express Gate 0 to Internet in Seconds! Express Gate is an ASUS exclusive OS that provides you with quick access to the Internet and key applications before entering Windows®. ASUS Q-Fan ASUS Q-Fan technology intelligently adjusts CPU fan speeds according to system loading to ensure quiet, cool and efficient operation. ASUS CrashFree BIOS 3 The ASUS CrashFree BIOS 3 allows users to restore corrupted BIOS data from a USB flash disk containing the BIOS file. This utility saves users the cost and hassle of buying a replacement BIOS chip. ASUS EZ Flash 2 EZ Flash 2 is a user-friendly BIOS update utility. Simply launch this tool and update BIOS from a USB flash disk before entering the OS. You can update your BIOS only in a few clicks without preparing an additional floppy diskette or using an OS-based flash utility. C.P.R.(CPU Parameter Recall) When the system hangs due to overclocking failure, there is no need to open the case to clear CMOS data. Just simply restart the system, the BIOS would show the previous setting and then users can amend the CPU setting again. MyLogo 2 You can convert your favorite photo into a 256-color boot logo for a more colorful and vivid image on your screen. S/PDIF-out on Back I/O Port This motherboard provides convenient connectivity to external home theater audio systems via coaxial and optical S/PDIF-out (SONY-PHILIPS Digital Interface) jacks. It allows to transfer digital audio without converting to analog format and keeps the best signal quality. Uses 100% All High-quality Conductive Polymer Capacitors! This motherboard uses all high-quality conductive polymer capacitors onboard for durability, improved lifespan, and enhanced thermal capacity. GreenASUS The motherboard and its packaging comply with the European Union´s Restriction on the use of Hazardous Substances (RoHS). This is in line with the ASUS vision of creating environment-friendly and recyclable products and packaging to safeguard consumers´ health while minimizing the impact on the environment. Accessories The product (electrical , electronic equipment, Mercury-containing button cell battery) should not be placed in municipal waste. Check local regulations for disposal of electronic products. * All specifications are subject to change without notice. Please check with your supplier for exact offers. Products may not be available in all markets. * PCB color and bundled software versions are subject to change without notice. * Brand and product names mentioned are trademarks of their respective companies.

1 0

Re: [coreboot] Patch: Update Geode LX code to avoid FILO/Kernel problems
by Stefan Reinauer 30 Apr '10

30 Apr '10

Hi Edwin, I know it's a while back but it looks like this patch is not really doing what it says because c0000 - fffff were ram_resource'd before, too. Just with a separate call. Did this not work? I think we do this in many places. Stefan On 1/27/10 6:17 PM, Edwin Beasant wrote: > > This patch adds e- and f-segment as an available RAM area on the AMD > lx-northbridge platforms and fixes FILO compatibility > > - Allows SeaBios to become resident correctly > > - Prevents Linux kernel resource problems when booted with > FILO and VGA MSR's written > > - Allows use of the Geode VGA patches > > > > Signed-off-by: Edwin Beasant <edwin_beasant(a)virtensys.com> > > > > > Index: src/northbridge/amd/lx/northbridge.c > =================================================================== > --- src/northbridge/amd/lx/northbridge.c (revision 5057) > +++ src/northbridge/amd/lx/northbridge.c (working copy) > @@ -414,8 +414,8 @@ > /* Report the memory regions */ > idx = 10; > ram_resource(dev, idx++, 0, 640); > - ram_resource(dev, idx++, 768, 1024); // c0000-fffff > are usable > - ram_resource(dev, idx++, 1024, tomk - 1024); // > Systop - 1 MB -> KB > + //ram_resource(dev, idx++, 768, 1024); // c0000-fffff > are usable > + ram_resource(dev, idx++, 768, tomk - 768); // > Systop - 1 MB -> KB > > #if CONFIG_WRITE_HIGH_TABLES==1 > /* Leave some space for ACPI, PIRQ and MP tables */

1 0

r5511 broke my compile
by Keith Hui 30 Apr '10

30 Apr '10

$ make GEN build.h ROMCC romstage.inc GEN crt0.S CC mainboard/asus/p2b-ls/crt0.s CC mainboard/asus/p2b-ls/crt0.initobj.o LINK coreboot OBJCOPY coreboot.bootblock make: *** No rule to make target `src/arch/i386/include/arch/asm.h', needed by `build/arch/i386/lib/c_start.o'. Stop.

2 1

I'm not able to extract the VGA BIOS from phoenix BIOS
by Joop Boonen 30 Apr '10

30 Apr '10

Hello All, I have the Arima HDAMA server. The BIOS can be found here: http://www.arimacorp.com/server/Product/ViewDownload.asp?View=HDAMA%20rev.G I want to extract the VGA.ROM but I can succeed. I have been following this instruction: http://www.coreboot.org/VGA_support When I execute this command: cat /proc/iomem | grep 'Video ROM' Nothing is returned. When i check via command: cat /proc/iomem I also don't see anything that is related to the display. I have a feeling that the reason why I don't see anything is because the VGA BIOS option ROM isn't loaded in RAM? I've also tried the phnxdeco tool. I don't see any modules that can be extracted when I use this tool. phnxdeco hdmag217.rom -l -=PhoenixDeco, version 0.33 (Linux)=- Filelength : 80786 (526214 bytes) Filename : hdmag217.rom PhoenixBIOS hook found at : 77500 System Information at : 77526 BootBlock : 8000 bytes BankSize : 512 KB Version : DEVEL4E0 Start : 200000715E1 Offset : 70000 BCP Modules : 23 BCPFCP : 7CA53 FCP 1st module : 9485 (79485) Released : �=@ at 14:37:39 /* Copyrighted Information */ NAPI /* ----------------------- */ +------------------------------------------------------------------------------+ | Class.Instance (Name) Packed ---> Expanded Compression Offset | +------------------------------------------------------------------------------+ Total Sections: 0 Can someone help me to find a way de extract the VGA ROM of this main board? Regards, Joop.

3 5

[Review Request 0/2] Preliminary D900T work v2
by Pat Erley 29 Apr '10

29 Apr '10

This is just a request for review on what I've done so far. This is not ready for commit. I'm working on adding Clevo D900T support. Project notes are available here: http://pat.erley.org/Other/D900TCoreboot My specific problem so far, when I do a 'make', it doesn't compile src/cpu/intel/socket_LGA775/*, which may be the correct behavior, I just don't know. Is this the appropriate approach? Aside: Is sending patch bombs like this from git rather than learning SVN acceptable to everyone? Pat Erley (2): Subject: Prepare for Clevo D900T Subject: LGA775 and P4-6x0 Support src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/model_f4x/model_f4x_init.c | 1 + src/cpu/intel/socket_LGA775/Kconfig | 8 + src/cpu/intel/socket_LGA775/Makefile.inc | 13 + src/cpu/intel/socket_LGA775/chip.h | 4 + src/cpu/intel/socket_LGA775/socket_LGA775.c | 7 + src/mainboard/Kconfig | 8 + src/mainboard/clevo/Kconfig | 28 +++ src/mainboard/clevo/d900t/Kconfig | 97 ++++++++ src/mainboard/clevo/d900t/Makefile.inc | 19 ++ src/mainboard/clevo/d900t/chip.h | 23 ++ src/mainboard/clevo/d900t/cmos.layout | 142 +++++++++++ src/mainboard/clevo/d900t/devicetree.cb | 108 +++++++++ src/mainboard/clevo/d900t/mainboard.c | 34 +++ src/mainboard/clevo/d900t/romstage.c | 344 +++++++++++++++++++++++++++ 16 files changed, 838 insertions(+), 0 deletions(-) create mode 100644 src/cpu/intel/socket_LGA775/Kconfig create mode 100644 src/cpu/intel/socket_LGA775/Makefile.inc create mode 100644 src/cpu/intel/socket_LGA775/chip.h create mode 100644 src/cpu/intel/socket_LGA775/socket_LGA775.c create mode 100644 src/mainboard/clevo/Kconfig create mode 100644 src/mainboard/clevo/d900t/Kconfig create mode 100644 src/mainboard/clevo/d900t/Makefile.inc create mode 100644 src/mainboard/clevo/d900t/chip.h create mode 100644 src/mainboard/clevo/d900t/cmos.layout create mode 100644 src/mainboard/clevo/d900t/devicetree.cb create mode 100644 src/mainboard/clevo/d900t/mainboard.c create mode 100644 src/mainboard/clevo/d900t/romstage.c

1 2

[review 0/2] Introductory Patchset Questions
by Pat Erley 29 Apr '10

29 Apr '10

This is just a request for review on what I've done so far. I'm working on adding Clevo D900T support. Project notes are available here: http://pat.erley.org/Other/D900TCoreboot My specific problem so far, when I do a 'make', it doesn't compile src/cpu/intel/socket_LGA775/*, which may be the correct behavior, I just don't know. Is this the appropriate approach? Aside: Is sending patch bombs like this from git rather than learning SVN acceptable to everyone? SOBs left off as I'm not comfortable with what is written so far Pat Erley (2): Subject: Prepare for Clevo D900T Subject: LGA775 and P4-6x0 Support src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/model_f4x/model_f4x_init.c | 1 + src/cpu/intel/socket_LGA775/Kconfig | 8 + src/cpu/intel/socket_LGA775/Makefile.inc | 13 + src/cpu/intel/socket_LGA775/chip.h | 4 + src/cpu/intel/socket_LGA775/socket_LGA775.c | 7 + src/mainboard/Kconfig | 8 + src/mainboard/clevo/Kconfig | 28 +++ src/mainboard/clevo/d900t/Kconfig | 97 ++++++++ src/mainboard/clevo/d900t/Makefile.inc | 19 ++ src/mainboard/clevo/d900t/chip.h | 23 ++ src/mainboard/clevo/d900t/cmos.layout | 142 +++++++++++ src/mainboard/clevo/d900t/devicetree.cb | 108 +++++++++ src/mainboard/clevo/d900t/mainboard.c | 34 +++ src/mainboard/clevo/d900t/romstage.c | 344 +++++++++++++++++++++++++++ 16 files changed, 838 insertions(+), 0 deletions(-) create mode 100644 src/cpu/intel/socket_LGA775/Kconfig create mode 100644 src/cpu/intel/socket_LGA775/Makefile.inc create mode 100644 src/cpu/intel/socket_LGA775/chip.h create mode 100644 src/cpu/intel/socket_LGA775/socket_LGA775.c create mode 100644 src/mainboard/clevo/Kconfig create mode 100644 src/mainboard/clevo/d900t/Kconfig create mode 100644 src/mainboard/clevo/d900t/Makefile.inc create mode 100644 src/mainboard/clevo/d900t/chip.h create mode 100644 src/mainboard/clevo/d900t/cmos.layout create mode 100644 src/mainboard/clevo/d900t/devicetree.cb create mode 100644 src/mainboard/clevo/d900t/mainboard.c create mode 100644 src/mainboard/clevo/d900t/romstage.c

1 2

Trouble building coreboot with SeaBIOS for QEMU.
by Neil Turton 29 Apr '10

29 Apr '10

I'm having difficulty building coreboot with SeaBIOS for use with the development version of QEMU. Two of the bios.bin files (0.5.1 and 0.6.0) downloaded from http://linuxtogo.org/~kevin/SeaBIOS/ work, but when I try to build from source, I get problems. I tried to follow the instructions from http://www.coreboot.org/QEMU_Build_Tutorial and http://www.coreboot.org/SeaBIOS but they make references to coreboot-v2 which doesn't seem to exist and targets/..../Config.lb which doesn't exist in coreboot-v3. I haven't applied the QEMU patches since they don't apply to qemu-0.12 and weren't needed for the downloaded bios.bin files. I'm using vgabios-cirrus.bin from the coreboot website and pxe-e1000.bin contains 64k of zeros (just to keep QEMU happy). I'd like to be able to compile coreboot from source and boot from the hard disk as normal, not necessarily using SeaBIOS but that seemed like a sensible option. I ran the following commands: dd if=/dev/zero of=pxe-e1000.bin bs=64k count=1 wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip unzip Vgabios-cirrus.zip svn co svn://coreboot.org/repository/coreboot-v3 wget 'http://linuxtogo.org/~kevin/SeaBIOS/bios.bin.elf-0.6.0' cd coreboot-v3 make menuconfig # Set ROM size to 128k # Add an ELF payload (payload.elf) cp ../bios.bin.elf-0.6.0 payload.elf make cp -f build/coreboot.rom ../bios.bin qemu -no-reboot -m 256 -L .. -serial /dev/tty I got lots of output from qemu (below) and it hangs with the VGA BIOS output on the screen. Any help would be appreciated. Cheers, Neil. coreboot-3.0.1177 Wed Apr 28 16:16:49 BST 2010 starting... (console_loglevel=8) Choosing fallback boot. LAR: Attempting to open 'fallback/initram/segment0'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: seen member normal/stage2/segment2@0xfffe5320, size 379 LAR: seen member normal/payload/segment0@0xfffe54f0, size 40387 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: Run file fallback/initram/segment0 failed: No such file. Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: CHECK normal/initram/segment0 @ 0xfffe0400 start 0xfffe0450 len 440 reallen 440 compression 0 entry 0x00000020 loadaddress 0x00000000 Entry point is 0xfffe0470 RAM init code started. Nothing to do. printktest1: If the immediately preceding line does not say "Nothing to do.", then execution did not start at main() Trying absolute call from non-_MAINOBJECT XIP code. Absolute call successful. Done. run_file returns with 0 Done RAM init code Done printk() buffer move LAR: Attempting to open 'normal/stage2/segment0'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: CHECK normal/stage2/segment0 @ 0xfffe0610 start 0xfffe0660 len 1 reallen 194784 compression 3 entry 0x00002048 loadaddress 0x0000db80 LAR: Compression algorithm #3 (zeroes) used LAR: Attempting to open 'normal/stage2/segment1'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: CHECK normal/stage2/segment1 @ 0xfffe0670 start 0xfffe06c0 len 19549 reallen 37740 compression 1 entry 0x00002048 loadaddress 0x00002000 LAR: Compression algorithm #1 (lzma) used LAR: Attempting to open 'normal/stage2/segment2'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: seen member normal/stage2/segment2@0xfffe5320, size 379 LAR: CHECK normal/stage2/segment2 @ 0xfffe5320 start 0xfffe5370 len 379 reallen 6164 compression 1 entry 0x00002048 loadaddress 0x0000c36c LAR: Compression algorithm #1 (lzma) used LAR: Attempting to open 'normal/stage2/segment3'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: seen member normal/stage2/segment2@0xfffe5320, size 379 LAR: seen member normal/payload/segment0@0xfffe54f0, size 40387 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: load_file: No such file 'normal/stage2/segment3' LAR: load_file_segments: All loaded, entry 0x00002048 cpu_phase1: Coldboot: nothing to do. Phase 1: Very early setup... Phase 1: done Show all devs...After phase 1. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 0 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 0 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 0 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 0 resources Phase 2: Early setup... Phase 2: Done. Show all devs...After phase 2. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 0 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 0 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 0 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 0 resources Phase 3: Enumerating buses... dev_phase3_scan: scanning root(Root Device) scan_static_bus for root (Root Device) cpus(CPU: 00) enabled domain_0(PCI_DOMAIN: 0000) enabled domain_0(PCI_DOMAIN: 0000) scanning... dev_phase3_scan: scanning domain_0(PCI_DOMAIN: 0000) pci_domain_scan_bus: calling pci_scan_bus pci_scan_bus start bus->dev domain_0 bus 0 ERROR: pci_scan_bus called with incorrect bus->dev->path.type, path is PCI_DOMAIN: 0000 PCI: pci_scan_bus for bus 00 pci_scan_bus: old_devices domain_0_pci_0_0, dev for this bus domain_0 PCI: scan devfn 0x0 to 0xff PCI: devfn 0x0 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_pci_0_0 pci_get_dev: check dev domain_0_pci_0_0 it has devfn 0x00 PCI: pci_scan_bus pci_get_dev returns dev domain_0_pci_0_0 set_pci_ops: dev domain_0_pci_0_0 already has ops of type 20504349 PCI: 00:00.0 [PCI: 8086:1237] enabled PCI: pci_scan_bus pci_probe_dev returns dev domain_0_pci_0_0 Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x8 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_pci_1_0 pci_get_dev: check dev domain_0_pci_1_0 it has devfn 0x08 PCI: pci_scan_bus pci_get_dev returns dev domain_0_pci_1_0 set_pci_ops: dev domain_0_pci_1_0 already has ops of type 20504349 PCI: 00:01.0 [PCI: 8086:7000] enabled PCI: pci_scan_bus pci_probe_dev returns dev domain_0_pci_1_0 PCI: devfn 0x9 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_pci_1_1 pci_get_dev: check dev domain_0_pci_1_1 it has devfn 0x09 PCI: pci_scan_bus pci_get_dev returns dev domain_0_pci_1_1 set_pci_ops: dev domain_0_pci_1_1 already has ops of type 20504349 PCI: 00:01.1 [PCI: 8086:7010] enabled PCI: pci_scan_bus pci_probe_dev returns dev domain_0_pci_1_1 PCI: devfn 0xa pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_pci_1_3 pci_get_dev: check dev domain_0_pci_1_3 it has devfn 0x0b PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xa, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xb pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_pci_1_3 pci_get_dev: check dev domain_0_pci_1_3 it has devfn 0x0b PCI: pci_scan_bus pci_get_dev returns dev domain_0_pci_1_3 set_pci_ops: dev domain_0_pci_1_3 already has ops of type 20504349 PCI: 00:01.3 [PCI: 8086:7113] enabled PCI: pci_scan_bus pci_probe_dev returns dev domain_0_pci_1_3 PCI: devfn 0xc pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xc, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xd pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xd, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xe pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xe, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xf pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xf, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0x10 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) new_device: devcnt 1 find_device_operations: check all_device_operations[0] find_device_operations: cons id PCI: 1013:00b8 find_device_operations: match PCI: 1013:00b8 constructor: constructor has ID PCI: 1013:00b8 default device constructor called set_pci_ops: dev dynamic PCI: 00:02.0 already has ops of type 20504349 PCI: 00:02.0 [PCI: 1013:00b8] enabled PCI: pci_scan_bus pci_probe_dev returns dev dynamic PCI: 00:02.0 Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x18 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) new_device: devcnt 2 find_device_operations: check all_device_operations[0] find_device_operations: cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[1] find_device_operations: cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[2] find_device_operations: cons id PCI: 8086:1237 find_device_operations: check all_device_operations[3] find_device_operations: cons id PCI: 8086:7000 find_device_operations: check all_device_operations[4] find_device_operations: cons id PCI: 8086:7010 find_device_operations: check all_device_operations[5] find_device_operations: cons id PCI: 8086:7113 No ops found and no constructor called for PCI: 8086:100e. find_device_operations: check all_device_operations[0] find_device_operations: cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[1] find_device_operations: cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[2] find_device_operations: cons id PCI: 8086:1237 find_device_operations: check all_device_operations[3] find_device_operations: cons id PCI: 8086:7000 find_device_operations: check all_device_operations[4] find_device_operations: cons id PCI: 8086:7010 find_device_operations: check all_device_operations[5] find_device_operations: cons id PCI: 8086:7113 set_pci_ops: dev dynamic PCI: 00:03.0 set ops to type 0 PCI: 00:03.0 [PCI: 8086:100e] enabled PCI: pci_scan_bus pci_probe_dev returns dev dynamic PCI: 00:03.0 Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x20 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x20, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x28 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x28, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x30 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x30, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x38 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x38, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x40 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x40, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x48 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x48, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x50 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x50, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x58 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x58, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x60 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x60, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x68 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x68, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x70 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x70, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x78 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x78, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x80 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x80, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x88 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x88, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x90 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x90, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x98 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x98, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xa0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xa0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xa8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xa8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xb0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xb0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xb8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xb8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xc0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xc0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xc8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xc8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xd0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xd0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xd8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xd8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xe0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xe0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xe8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xe8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xf0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xf0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xf8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: Done for loop dev_phase3_scan: busdevice domain_0_pci_0_0: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: busdevice domain_0_pci_1_0: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: busdevice domain_0_pci_1_1: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: busdevice domain_0_pci_1_3: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: busdevice dynamic PCI: 00:02.0: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: busdevice dynamic PCI: 00:03.0: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 PCI: pci_scan_bus returning with curr_bus=000 dev_phase3_scan: returning 0 scan_static_bus for root(Root Device) done dev_phase3_scan: returning 0 Phase 3: Done. Show all devs in tree form...After phase 3. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 0 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 0 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 0 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1, 0 resources dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1, 0 resources Phase 4: Allocating resources... Phase 4: Reading resources... read_resources: root(Root Device) read_resources bus 0 link: 0 read_resources: root(Root Device) dtsname cpus enabled 1 read_resources: cpus(CPU: 00) missing phase4_read_resources read_resources: root(Root Device) dtsname domain_0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) read_resources bus 0 link: 0 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname domain_0_pci_0_0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname domain_0_pci_1_0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname domain_0_pci_1_1 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname domain_0_pci_1_3 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:02.0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:03.0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) read_resources bus 0 link: 0 done read_resources: root(Root Device) read_resources bus 0 link: 0 done Phase 4: Done reading resources. Phase 4: Constrain resources. Show resources in subtree (root)...Original. Root Device links 1 child on link 0 cpus CPU: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0 PCI_DOMAIN: 0000 resource base 1000 size 0 align 0 gran 0 limit ffff flags 400c0100 index 10000000 PCI_DOMAIN: 0000 resource base c0000 size 0 align 0 gran 0 limit febfffff flags 400c0200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff flags c0040200 index 1 PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags e0000100 index 0 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 00:03.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 14 PCI: 00:03.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI_DOMAIN: 0000 compute_resource_needs_io: base: 1000 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:03.0 14 * [0x1000 - 0x103f] io PCI: 00:01.1 20 * [0x1040 - 0x104f] io PCI_DOMAIN: 0000 compute_resource_needs_io: base: 1050 size: 50 align: 6 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resource_needs_mem: base: c0000 size: 0 align: 0 gran: 0 limit: febfffff PCI: 00:02.0 10 * [0x2000000 - 0x3ffffff] prefmem PCI: 00:03.0 10 * [0x4000000 - 0x401ffff] mem PCI: 00:02.0 30 * [0x4020000 - 0x402ffff] mem PCI: 00:03.0 30 * [0x4030000 - 0x403ffff] mem PCI: 00:02.0 14 * [0x4040000 - 0x4040fff] mem PCI_DOMAIN: 0000 compute_resource_needs_mem: base: 4041000 size: 2041000 align: 25 gran: 0 limit: febfffff done Show resources in subtree (root)...After summations. Root Device links 1 child on link 0 cpus CPU: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0 PCI_DOMAIN: 0000 resource base 1000 size 50 align 6 gran 0 limit ffff flags 400c0100 index 10000000 PCI_DOMAIN: 0000 resource base c0000 size 2041000 align 25 gran 0 limit febfffff flags 400c0200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff flags c0040200 index 1 PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags e0000100 index 0 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 1040 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base 2000000 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 4040000 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:02.0 resource base 4020000 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base 4000000 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 00:03.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 100 index 14 PCI: 00:03.0 resource base 4030000 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 Allocating VGA resource PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Show resources in subtree (root)...After VGA. Root Device links 1 child on link 0 cpus CPU: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0 PCI_DOMAIN: 0000 resource base 1000 size 50 align 6 gran 0 limit ffff flags 400c0100 index 10000000 PCI_DOMAIN: 0000 resource base fc000000 size 2041000 align 25 gran 0 limit febfffff flags 400c0200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff flags c0040200 index 1 PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags e0000100 index 0 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 1040 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base 2000000 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 4040000 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:02.0 resource base 4020000 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base 4000000 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 00:03.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 100 index 14 PCI: 00:03.0 resource base 4030000 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI_DOMAIN: 0000 assign_resource_values_io: base:1000 size:50 align:6 gran:0 limit:ffff Assigned: PCI: 00:03.0 14 * [0x1000 - 0x103f] io Assigned: PCI: 00:01.1 20 * [0x1040 - 0x104f] io PCI_DOMAIN: 0000 assign_resource_values_io: next_base: 1050 size: 50 align: 6 gran: 0 done PCI_DOMAIN: 0000 assign_resource_values_mem: base:fc000000 size:2041000 align:25 gran:0 limit:febfffff Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem Assigned: PCI: 00:03.0 10 * [0xfe000000 - 0xfe01ffff] mem Assigned: PCI: 00:02.0 30 * [0xfe020000 - 0xfe02ffff] mem Assigned: PCI: 00:03.0 30 * [0xfe030000 - 0xfe03ffff] mem Assigned: PCI: 00:02.0 14 * [0xfe040000 - 0xfe040fff] mem PCI_DOMAIN: 0000 assign_resource_values_mem: next_base: fe041000 size: 2041000 align: 25 gran: 0 done Show resources in subtree (root)...After assigning values. Root Device links 1 child on link 0 cpus CPU: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0 PCI_DOMAIN: 0000 resource base 1000 size 50 align 6 gran 0 limit ffff flags 400c0100 index 10000000 PCI_DOMAIN: 0000 resource base fc000000 size 2041000 align 25 gran 0 limit febfffff flags 400c0200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff flags c0040200 index 1 PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags e0000100 index 0 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 1040 size 10 align 4 gran 4 limit ffff flags 40000100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit ffffffff flags 40001200 index 10 PCI: 00:02.0 resource base fe040000 size 1000 align 12 gran 12 limit ffffffff flags 40000200 index 14 PCI: 00:02.0 resource base fe020000 size 10000 align 16 gran 16 limit ffffffff flags 40002200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base fe000000 size 20000 align 17 gran 17 limit ffffffff flags 40000200 index 10 PCI: 00:03.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 40000100 index 14 PCI: 00:03.0 resource base fe030000 size 10000 align 16 gran 16 limit ffffffff flags 40002200 index 30 Phase 4: Setting resources... phase4_set_resources(root) Root Device, bus 0 link: 0 phase4_set_resources(domain_0) PCI_DOMAIN: 0000, bus 0 link: 0 Using CMOS settings of 245760 kB RAM. Adding RAM resource (655360 bytes) Adding RAM resource (250871808 bytes) PCI: 00:01.1 20 <- [0x0000001040 - 0x000000104f] size 0x00000010 gran 0x04 io pci_set_resource PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem pci_set_resource PCI: 00:02.0 14 <- [0x00fe040000 - 0x00fe040fff] size 0x00001000 gran 0x0c mem pci_set_resource PCI: 00:02.0 30 <- [0x00fe020000 - 0x00fe02ffff] size 0x00010000 gran 0x10 romem pci_set_resource PCI: 00:03.0 10 <- [0x00fe000000 - 0x00fe01ffff] size 0x00020000 gran 0x11 mem pci_set_resource PCI: 00:03.0 14 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io pci_set_resource PCI: 00:03.0 30 <- [0x00fe030000 - 0x00fe03ffff] size 0x00010000 gran 0x10 romem pci_set_resource phase4_set_resources(domain_0) PCI_DOMAIN: 0000 done, bus 0 link: 0 phase4_set_resources(root) Root Device done, bus 0 link: 0 Show resources in subtree (root)...After setting resources. Root Device links 1 child on link 0 cpus CPU: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0 PCI_DOMAIN: 0000 resource base 1000 size 50 align 6 gran 0 limit ffff flags 400c0100 index 10000000 PCI_DOMAIN: 0000 resource base fc000000 size 2041000 align 25 gran 0 limit febfffff flags 400c0200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff flags c0040200 index 1 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI: 00:00.0 resource base c0000 size ef40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags e0000100 index 0 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 1040 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit ffffffff flags 60001200 index 10 PCI: 00:02.0 resource base fe040000 size 1000 align 12 gran 12 limit ffffffff flags 60000200 index 14 PCI: 00:02.0 resource base fe020000 size 10000 align 16 gran 16 limit ffffffff flags 60002200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base fe000000 size 20000 align 17 gran 17 limit ffffffff flags 60000200 index 10 PCI: 00:03.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 60000100 index 14 PCI: 00:03.0 resource base fe030000 size 10000 align 16 gran 16 limit ffffffff flags 60002200 index 30 Phase 4: Done allocating resources. Show all devs...After phase 4. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 3 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 1 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 1 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 4 resources dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1, 3 resources dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1, 3 resources Phase 5: Enabling resources... dev_phase5: cpus(CPU: 00) missing ops PCI: 00:01.0: Setting subsystem VID/DID to 1af4/1100 pci_dev_enable_resources: domain_0_pci_1_0 (PCI: 00:01.0) cmd <- 147 PCI: 00:01.1: Setting subsystem VID/DID to 1af4/1100 pci_dev_enable_resources: domain_0_pci_1_1 (PCI: 00:01.1) cmd <- 141 PCI: 00:01.3: Setting subsystem VID/DID to 1af4/1100 pci_dev_enable_resources: domain_0_pci_1_3 (PCI: 00:01.3) cmd <- 140 PCI: 00:02.0: Device not on_mainboard pci_dev_enable_resources: dynamic PCI: 00:02.0 (PCI: 00:02.0) cmd <- 143 PCI: 00:03.0: Device not on_mainboard pci_dev_enable_resources: dynamic PCI: 00:03.0 (PCI: 00:03.0) cmd <- 143 Phase 5: Done. Show all devs...After phase 5. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 3 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 1 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 1 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 4 resources dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1, 3 resources dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1, 3 resources Phase 6: Initializing devices... Phase 6: Root Device init. Phase 6: PCI_DOMAIN: 0000 init. Phase 6: PCI: 00:00.0 init. Phase 6: PCI: 00:01.0 init. Initializing realtime clock. RTC: Checksum invalid zeroing cmos Invalid coreboot CMOS checksum. Phase 6: PCI: 00:01.1 init. Enabling IDE channel 1 Enabling IDE channel 2 Enabling Legacy IDE Phase 6: PCI: 00:01.3 init. Enabling SMBus. Enable Power Management Functions Phase 6: PCI: 00:02.0 init. Init VGA device PCI: pci_dev_init dynamic PCI: 00:02.0 Probing for option ROM ROM address for PCI: 00:02.0 = c0000 PCI Expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x0038 PCI ROM Image, @0x000c003c, Vendor 1013, Device 00b8, PCI ROM Image, Class Code 030000, Code Type 00 Phase 6: PCI: 00:03.0 init. PCI: pci_dev_init dynamic PCI: 00:03.0 Probing for option ROM ROM address for PCI: 00:03.0 = fe030000 PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000 Incorrect Expansion ROM Header Signature 0000 Phase 6: Devices initialized. Show all devs...After phase 6. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 3 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 1 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 1 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 4 resources dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1, 3 resources dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1, 3 resources cpu_phase2: Coldboot: nothing to do. search_global_resources: mask 4200 type 4200 search_global_resources: dev root, #resources 0 search_global_resources: dev cpus, #resources 0 search_global_resources: dev domain_0_pci_0_0, #resources 3 search_global_resources: dev domain_0_pci_0_0, resource 0, flags c0040200 base 0xa0000 size 0x20000 search_global_resources: dev domain_0_pci_0_0, resource 1, flags e0004200 base 0x0 size 0xa0000 search_global_resources: dev domain_0_pci_0_0, resource 2, flags e0004200 base 0xc0000 size 0xef40000 search_global_resources: dev domain_0_pci_1_0, #resources 1 search_global_resources: dev domain_0_pci_1_0, resource 0, flags e0000100 base 0x0 size 0x1000 search_global_resources: dev domain_0_pci_1_1, #resources 1 search_global_resources: dev domain_0_pci_1_1, resource 0, flags 60000100 base 0x1040 size 0x10 search_global_resources: dev domain_0_pci_1_3, #resources 0 search_global_resources: dev domain_0, #resources 4 search_global_resources: dev domain_0, resource 0, flags 400c0100 base 0x1000 size 0x50 search_global_resources: dev domain_0, resource 1, flags 400c0200 base 0xfc000000 size 0x2041000 search_global_resources: dev domain_0, resource 2, flags e0000200 base 0xfec00000 size 0x100000 search_global_resources: dev domain_0, resource 3, flags e0000200 base 0xfee00000 size 0x10000 search_global_resources: dev dynamic PCI: 00:02.0, #resources 3 search_global_resources: dev dynamic PCI: 00:02.0, resource 0, flags 60001200 base 0xfc000000 size 0x2000000 search_global_resources: dev dynamic PCI: 00:02.0, resource 1, flags 60000200 base 0xfe040000 size 0x1000 search_global_resources: dev dynamic PCI: 00:02.0, resource 2, flags 60002200 base 0xfe020000 size 0x10000 search_global_resources: dev dynamic PCI: 00:03.0, #resources 3 search_global_resources: dev dynamic PCI: 00:03.0, resource 0, flags 60000200 base 0xfe000000 size 0x20000 search_global_resources: dev dynamic PCI: 00:03.0, resource 1, flags 60000100 base 0x1000 size 0x40 search_global_resources: dev dynamic PCI: 00:03.0, resource 2, flags 60002200 base 0xfe030000 size 0x10000 Multiboot Information structure has been written. LAR: Attempting to open 'normal/option_table'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: CHECK normal/option_table @ 0xfffe0000 start 0xfffe0050 len 932 reallen 932 compression 0 entry 0x00000000 loadaddress 0x00000000 search_global_resources: mask 4200 type 4200 search_global_resources: dev root, #resources 0 search_global_resources: dev cpus, #resources 0 search_global_resources: dev domain_0_pci_0_0, #resources 3 search_global_resources: dev domain_0_pci_0_0, resource 0, flags c0040200 base 0xa0000 size 0x20000 search_global_resources: dev domain_0_pci_0_0, resource 1, flags e0004200 base 0x0 size 0xa0000 lb_memory_range: start 0x0 size 0xa0000 search_global_resources: dev domain_0_pci_0_0, resource 2, flags e0004200 base 0xc0000 size 0xef40000 lb_memory_range: start 0xc0000 size 0xef40000 search_global_resources: dev domain_0_pci_1_0, #resources 1 search_global_resources: dev domain_0_pci_1_0, resource 0, flags e0000100 base 0x0 size 0x1000 search_global_resources: dev domain_0_pci_1_1, #resources 1 search_global_resources: dev domain_0_pci_1_1, resource 0, flags 60000100 base 0x1040 size 0x10 search_global_resources: dev domain_0_pci_1_3, #resources 0 search_global_resources: dev domain_0, #resources 4 search_global_resources: dev domain_0, resource 0, flags 400c0100 base 0x1000 size 0x50 search_global_resources: dev domain_0, resource 1, flags 400c0200 base 0xfc000000 size 0x2041000 search_global_resources: dev domain_0, resource 2, flags e0000200 base 0xfec00000 size 0x100000 search_global_resources: dev domain_0, resource 3, flags e0000200 base 0xfee00000 size 0x10000 search_global_resources: dev dynamic PCI: 00:02.0, #resources 3 search_global_resources: dev dynamic PCI: 00:02.0, resource 0, flags 60001200 base 0xfc000000 size 0x2000000 search_global_resources: dev dynamic PCI: 00:02.0, resource 1, flags 60000200 base 0xfe040000 size 0x1000 search_global_resources: dev dynamic PCI: 00:02.0, resource 2, flags 60002200 base 0xfe020000 size 0x10000 search_global_resources: dev dynamic PCI: 00:03.0, #resources 3 search_global_resources: dev dynamic PCI: 00:03.0, resource 0, flags 60000200 base 0xfe000000 size 0x20000 search_global_resources: dev dynamic PCI: 00:03.0, resource 1, flags 60000100 base 0x1000 size 0x40 search_global_resources: dev dynamic PCI: 00:03.0, resource 2, flags 60002200 base 0xfe030000 size 0x10000 lb_cleanup_memory_ranges: # entries 2 #0: base 0x00000000 size 0xa0000 #1: base 0x000c0000 size 0xef40000 lb_memory_range: start 0x0 size 0x500 lb_cleanup_memory_ranges: # entries 3 #0: base 0x00000500 size 0x9fb00 #1: base 0x000c0000 size 0xef40000 #2: base 0x00000000 size 0x500 lb_memory_range: start 0xf0000 size 0xd0 lb_cleanup_memory_ranges: # entries 5 #0: base 0x00000000 size 0x500 #1: base 0x00000500 size 0x9fb00 #2: base 0x000c0000 size 0x30000 #3: base 0x000f00d0 size 0xef0ff30 #4: base 0x000f0000 size 0xd0 Wrote coreboot table at: 0x00000500 - 0x00000ad4 checksum 7cf4 Show all devs...After writing tables. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 3 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 1 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 1 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 4 resources dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1, 3 resources dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1, 3 resources Stage2 code done. LAR: Attempting to open 'normal/payload/segment0'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: seen member normal/stage2/segment2@0xfffe5320, size 379 LAR: seen member normal/payload/segment0@0xfffe54f0, size 40387 LAR: CHECK normal/payload/segment0 @ 0xfffe54f0 start 0xfffe5540 len 40387 reallen 80896 compression 1 entry 0x000fdf82 loadaddress 0x000ec400 LAR: Compression algorithm #1 (lzma) used Decoding error = 1 LAR: Attempting to open 'normal/payload/segment1'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: seen member normal/stage2/segment2@0xfffe5320, size 379 LAR: seen member normal/payload/segment0@0xfffe54f0, size 40387 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: load_file: No such file 'normal/payload/segment1' LAR: load_file_segments: All loaded, entry 0x000fdf82

4 8

simnow and SB700/RS780
by Rudolf Marek 29 Apr '10

29 Apr '10

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, It took me whole evening to setup the beast (tm), but I managed to create a very similar board to what I have - socket 939 K8 + AMD 785G + W83627DHG. It boots with the asrock image up to SeaBIOS. I think it is nice platform for the tests, because the existing BSDs dont have any SB700/RS780 target. I used simnow-linux64-4.5.2pub.tar.gz which allows to set own motherboards. download http://assembler.cz/rom/asrock7.bsd We could do also an AM2 and FAM10 target... but it is really horrible on this machine with 1GB of ram, also it produces a lot of SIGSEGV especially while clicking on memory dimm configuration. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvYunYACgkQ3J9wPJqZRNXAywCgzHgIAuAJKj23NLkx4KBfj8Zg DaYAoLrT2Bu9wliSO5h1NkgRU0X1rdMb =wXxq -----END PGP SIGNATURE-----

1 0

← Newer
1
2
3
4
5
6
7
8
...
41
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2010