coreboot April 2010

coreboot@coreboot.org

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402 discussions

[commit] r5518 - trunk/src/superio/winbond/w83627hf
by repository service 30 Apr '10

30 Apr '10

Author: stepan Date: Fri Apr 30 22:30:47 2010 New Revision: 5518 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5518 Log: Remove some warnings. For code that is called from the mainboard romstage.c files using prototypes is the way to go I think. It would make our life a lot easier should we ever decide to move (some mainboards) over to not #include all those .c files in romstage.c anymore. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/superio/winbond/w83627hf/w83627hf.h trunk/src/superio/winbond/w83627hf/w83627hf_early_init.c Modified: trunk/src/superio/winbond/w83627hf/w83627hf.h ============================================================================== --- trunk/src/superio/winbond/w83627hf/w83627hf.h Fri Apr 30 22:28:35 2010 (r5517) +++ trunk/src/superio/winbond/w83627hf/w83627hf.h Fri Apr 30 22:30:47 2010 (r5518) @@ -109,3 +109,9 @@ #define W83627HF_HAP1 0x14 #define W83627HF_XSCNF 0x15 #define W83627HF_XWBCNF 0x16 + +#if defined(__PRE_RAM__) && !defined(__ROMCC__) +void w83627hf_disable_dev(device_t dev); +void w83627hf_enable_dev(device_t dev, unsigned iobase); +#endif + Modified: trunk/src/superio/winbond/w83627hf/w83627hf_early_init.c ============================================================================== --- trunk/src/superio/winbond/w83627hf/w83627hf_early_init.c Fri Apr 30 22:28:35 2010 (r5517) +++ trunk/src/superio/winbond/w83627hf/w83627hf_early_init.c Fri Apr 30 22:30:47 2010 (r5518) @@ -23,13 +23,13 @@ #include <arch/romcc_io.h> #include "w83627hf.h" -static void w83627hf_disable_dev(device_t dev) +void w83627hf_disable_dev(device_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void w83627hf_enable_dev(device_t dev, unsigned iobase) +void w83627hf_enable_dev(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0);

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[commit] r5517 - trunk/src/northbridge/amd/amdfam10
by repository service 30 Apr '10

30 Apr '10

Author: stepan Date: Fri Apr 30 22:28:35 2010 New Revision: 5517 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5517 Log: Remove some more warnings. The code is only used by functions protected by the same preprocessor check Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c Fri Apr 30 21:21:01 2010 (r5516) +++ trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c Fri Apr 30 22:28:35 2010 (r5517) @@ -152,6 +152,7 @@ return sel_m; } +#if CONFIG_AMDMCT == 0 #ifdef UNUSED_CODE static void set_DctSelHiEn(u32 i, u32 val) { @@ -219,8 +220,6 @@ } #endif -#if CONFIG_AMDMCT == 0 - static u32 get_one_DCT(struct mem_info *meminfo) { u32 one_DCT = 1;

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Warnings
by Myles Watson 30 Apr '10

30 Apr '10

As of 5512, these are the last four warnings that are not "defined but not used" warnings. src/northbridge/amd/gx2/chipsetinit.c:271: warning: suggest parentheses around '-' inside '<<' src/northbridge/amd/lx/raminit.c:334: warning: array subscript is above array bounds src/northbridge/via/vx800/pci_rawops.h:43:2: warning: #warning "FIXME: get rid of this extra copy of pci access functions." src/southbridge/intel/pxhd/pxhd_bridge.c:70:2: warning: #warning "Please review lots of dead code here." Thanks, Myles

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[commit] r5516 - in trunk/src: northbridge/via/vx800 southbridge/amd/sb600
by repository service 30 Apr '10

30 Apr '10

Author: stepan Date: Fri Apr 30 21:21:01 2010 New Revision: 5516 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5516 Log: get rid of some more warnings.. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/via/vx800/vx800_lpc.c trunk/src/southbridge/amd/sb600/sb600.h trunk/src/southbridge/amd/sb600/sb600_early_setup.c Modified: trunk/src/northbridge/via/vx800/vx800_lpc.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_lpc.c Fri Apr 30 19:50:53 2010 (r5515) +++ trunk/src/northbridge/via/vx800/vx800_lpc.c Fri Apr 30 21:21:01 2010 (r5516) @@ -342,9 +342,11 @@ /* turn on keyboard and RTC, no need to visit this reg twice */ pc_keyboard_init(0); + printk(BIOS_DEBUG, "ps2 usb lid, you set who can wakeup system from s3 sleep\n"); S3_ps2_kb_ms_wakeup(dev); S3_usb_wakeup(dev); + S3_lid_wakeup(dev); /* enable acpi cpu c3 state. (c2 state need not do anything.) #1 Modified: trunk/src/southbridge/amd/sb600/sb600.h ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600.h Fri Apr 30 19:50:53 2010 (r5515) +++ trunk/src/southbridge/amd/sb600/sb600.h Fri Apr 30 21:21:01 2010 (r5516) @@ -37,4 +37,7 @@ void sb600_enable(device_t dev); +void sb600_lpc_port80(void); +void sb600_pci_port80(void); + #endif /* SB600_H */ Modified: trunk/src/southbridge/amd/sb600/sb600_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_early_setup.c Fri Apr 30 19:50:53 2010 (r5515) +++ trunk/src/southbridge/amd/sb600/sb600_early_setup.c Fri Apr 30 21:21:01 2010 (r5516) @@ -213,7 +213,7 @@ outb(0x06, 0x0cf9); } -static void sb600_pci_port80(void) +void sb600_pci_port80(void) { u8 byte; device_t dev; @@ -258,7 +258,7 @@ pci_write_config8(dev, 0x4A, byte); } -static void sb600_lpc_port80(void) +void sb600_lpc_port80(void) { u8 byte; device_t dev;

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build service results for r5515
by coreboot information 30 Apr '10

30 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5515 to the coreboot repository. This caused the following changes: Change Log: fix compilation of mtarvon Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of intel:mtarvon has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5514
by coreboot information 30 Apr '10

30 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5514 to the coreboot repository. This caused the following changes: Change Log: Doesn't need to be a warning. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of intel:mtarvon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5514&device=mtarvon&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5513
by coreboot information 30 Apr '10

30 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5513 to the coreboot repository. This caused the following changes: Change Log: drop extra pci access functions. these are exact copies of romcc_io.h. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of intel:mtarvon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5513&device=mtarvon&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5515 - trunk/src/northbridge/intel/i3100
by repository service 30 Apr '10

30 Apr '10

Author: stepan Date: Fri Apr 30 19:50:53 2010 New Revision: 5515 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5515 Log: fix compilation of mtarvon Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/intel/i3100/raminit.c Modified: trunk/src/northbridge/intel/i3100/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i3100/raminit.c Fri Apr 30 19:46:16 2010 (r5514) +++ trunk/src/northbridge/intel/i3100/raminit.c Fri Apr 30 19:50:53 2010 (r5515) @@ -944,7 +944,7 @@ u32 drc; u32 data32; u32 mode_reg; - u32 const *iptr; + const u32 *iptr; u16 data16; static const struct { u32 clkgr[4];

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[commit] r5514 - trunk/src/southbridge/intel/pxhd
by repository service 30 Apr '10

30 Apr '10

Author: stepan Date: Fri Apr 30 19:46:16 2010 New Revision: 5514 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5514 Log: Doesn't need to be a warning. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/intel/pxhd/pxhd_bridge.c Modified: trunk/src/southbridge/intel/pxhd/pxhd_bridge.c ============================================================================== --- trunk/src/southbridge/intel/pxhd/pxhd_bridge.c Fri Apr 30 19:44:39 2010 (r5513) +++ trunk/src/southbridge/intel/pxhd/pxhd_bridge.c Fri Apr 30 19:46:16 2010 (r5514) @@ -67,7 +67,7 @@ /* Bridge control ISA enable */ pci_write_config8(dev, 0x3e, 0x07); -#warning "Please review lots of dead code here." + // FIXME Please review lots of dead code here. #if 0 int nmi_option; uint32_t dword;

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[commit] r5513 - trunk/src/northbridge/via/vx800
by repository service 30 Apr '10

30 Apr '10

Author: stepan Date: Fri Apr 30 19:44:39 2010 New Revision: 5513 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5513 Log: drop extra pci access functions. these are exact copies of romcc_io.h. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/via/vx800/pci_rawops.h trunk/src/northbridge/via/vx800/uma_ram_setting.c Modified: trunk/src/northbridge/via/vx800/pci_rawops.h ============================================================================== --- trunk/src/northbridge/via/vx800/pci_rawops.h Fri Apr 30 19:11:03 2010 (r5512) +++ trunk/src/northbridge/via/vx800/pci_rawops.h Fri Apr 30 19:44:39 2010 (r5513) @@ -2,11 +2,11 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 One Laptop per Child, Association, Inc. + * Copyright (C) 2010 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -18,14 +18,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef ARCH_I386_PCI_RAWOPS_H -# define ARCH_I386_PCI_RAWOPS_H 1 -#include <stdint.h> +#ifndef NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H +#define NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H -#define PCI_RAWDEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) +#include <stdint.h> +#include <arch/romcc_io.h> struct VIA_PCI_REG_INIT_TABLE { u8 ChipRevisionStart; @@ -38,219 +35,31 @@ u8 Value; }; -typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */ - -#warning "FIXME: get rid of this extra copy of pci access functions." - -/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, - * We don't need to set %fs, and %gs anymore - * Before that We need to use %gs, and leave %fs to other RAM access - */ -static u8 pci_io_rawread_config8(device_t_raw dev, unsigned where) -{ - unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 - addr = (dev >> 4) | where; -#else - addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); //seg == 0 -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inb(0xCFC + (addr & 3)); -} - -#if CONFIG_MMCONF_SUPPORT -static u8 pci_mmio_rawread_config8(device_t_raw dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - return read8x(addr); -} -#endif -static u8 pci_rawread_config8(device_t_raw dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT - return pci_mmio_rawread_config8(dev, where); -#else - return pci_io_rawread_config8(dev, where); -#endif -} - -static u16 pci_io_rawread_config16(device_t_raw dev, unsigned where) -{ - unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 - addr = (dev >> 4) | where; -#else - addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inw(0xCFC + (addr & 2)); -} - -#if CONFIG_MMCONF_SUPPORT -static u16 pci_mmio_rawread_config16(device_t_raw dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - return read16x(addr); -} -#endif - -static u16 pci_rawread_config16(device_t_raw dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT - return pci_mmio_rawread_config16(dev, where); -#else - return pci_io_rawread_config16(dev, where); -#endif -} - -static u32 pci_io_rawread_config32(device_t_raw dev, unsigned where) -{ - unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 - addr = (dev >> 4) | where; -#else - addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#if CONFIG_MMCONF_SUPPORT -static u32 pci_mmio_rawread_config32(device_t_raw dev, unsigned where) -{ - unsigned addr; - addr = dev | where; - return read32x(addr); -} -#endif - -static u32 pci_rawread_config32(device_t_raw dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT - return pci_mmio_rawread_config32(dev, where); -#else - return pci_io_rawread_config32(dev, where); -#endif -} - -static void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) -{ - unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 - addr = (dev >> 4) | where; -#else - addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -#if CONFIG_MMCONF_SUPPORT -static void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) -{ - unsigned addr; - addr = dev | where; - write8x(addr, value); -} -#endif - -static void pci_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) -{ -#if CONFIG_MMCONF_SUPPORT - pci_mmio_rawwrite_config8(dev, where, value); -#else - pci_io_rawwrite_config8(dev, where, value); -#endif -} - -static void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) -{ - unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 - addr = (dev >> 4) | where; -#else - addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); -} - -#if CONFIG_MMCONF_SUPPORT -static void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, - u16 value) -{ - unsigned addr; - addr = dev | where; - write16x(addr, value); -} -#endif - -static void pci_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) -{ -#if CONFIG_MMCONF_SUPPORT - pci_mmio_rawwrite_config16(dev, where, value); -#else - pci_io_rawwrite_config16(dev, where, value); -#endif -} - -static void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) -{ - unsigned addr; -#if CONFIG_PCI_IO_CFG_EXT == 0 - addr = (dev >> 4) | where; -#else - addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -#if CONFIG_MMCONF_SUPPORT -static void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) -{ - unsigned addr; - addr = dev | where; - write32x(addr, value); -} -#endif - -static void pci_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) -{ -#if CONFIG_MMCONF_SUPPORT - pci_mmio_rawwrite_config32(dev, where, value); -#else - pci_io_rawwrite_config32(dev, where, value); -#endif -} - -static void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval, u8 mask) +static void pci_modify_config8(device_t dev, unsigned where, u8 orval, u8 mask) { - u8 data = pci_rawread_config8(dev, where); + u8 data = pci_read_config8(dev, where); data &= (~mask); data |= orval; - pci_rawwrite_config8(dev, where, data); + pci_write_config8(dev, where, data); } -static void pci_rawmodify_config16(device_t_raw dev, unsigned where, u16 orval, u16 mask) +static void pci_modify_config16(device_t dev, unsigned where, u16 orval, u16 mask) { - u16 data = pci_rawread_config16(dev, where); + u16 data = pci_read_config16(dev, where); data &= (~mask); data |= orval; - pci_rawwrite_config16(dev, where, data); + pci_write_config16(dev, where, data); } -static void pci_rawmodify_config32(device_t_raw dev, unsigned where, u32 orval, u32 mask) +static void pci_modify_config32(device_t dev, unsigned where, u32 orval, u32 mask) { - u32 data = pci_rawread_config32(dev, where); + u32 data = pci_read_config32(dev, where); data &= (~mask); data |= orval; - pci_rawwrite_config32(dev, where, data); + pci_write_config32(dev, where, data); } -static void io_rawmodify_config8(u16 where, u8 orval, u8 mask) +static void io_modify_config8(u16 where, u8 orval, u8 mask) { u8 data = inb(where); data &= (~mask); @@ -262,7 +71,7 @@ const struct VIA_PCI_REG_INIT_TABLE *initdata) { u8 i = 0; - device_t_raw devbxdxfx; + device_t devbxdxfx; for (i = 0;; i++) { if ((initdata[i].Mask == 0) && (initdata[i].Value == 0) && (initdata[i].Bus == 0) @@ -275,9 +84,9 @@ if ((chipversion >= initdata[i].ChipRevisionStart) && (chipversion <= initdata[i].ChipRevisionEnd)) { devbxdxfx = - PCI_RAWDEV(initdata[i].Bus, initdata[i].Device, + PCI_DEV(initdata[i].Bus, initdata[i].Device, initdata[i].Function); - pci_rawmodify_config8(devbxdxfx, + pci_modify_config8(devbxdxfx, initdata[i].Register, initdata[i].Value, initdata[i].Mask); Modified: trunk/src/northbridge/via/vx800/uma_ram_setting.c ============================================================================== --- trunk/src/northbridge/via/vx800/uma_ram_setting.c Fri Apr 30 19:11:03 2010 (r5512) +++ trunk/src/northbridge/via/vx800/uma_ram_setting.c Fri Apr 30 19:44:39 2010 (r5513) @@ -172,11 +172,11 @@ Tmp = VIACONFIG_VGA_PCI_14; pci_write_config32(vga_dev, 0x14, Tmp); -//enable direct cpu frame buffer access - i = pci_rawread_config8(PCI_RAWDEV(0, 0, 3), 0xa1); + //enable direct cpu frame buffer access + i = pci_read_config8(PCI_DEV(0, 0, 3), 0xa1); i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa1, i); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa0, 0x01); + pci_write_config8(PCI_DEV(0, 0, 3), 0xa1, i); + pci_write_config8(PCI_DEV(0, 0, 3), 0xa0, 0x01); //enable GFx memory space access control for S.L and mmio ByteVal = pci_read_config8(d0f0_dev, 0xD4);

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coreboot April 2010